arm64: errata: add workaround for cortex-a53 erratum #845719

When running a compat (AArch32) userspace on Cortex-A53, a load at EL0
from a virtual address that matches the bottom 32 bits of the virtual
address used by a recent load at (AArch64) EL1 might return incorrect
data.

This patch works around the issue by writing to the contextidr_el1
register on the exception return path when returning to a 32-bit task.
This workaround is patched in at runtime based on the MIDR value of the
processor.

Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

1 files changed, 21 insertions, 0 deletions

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 02f67a9d7426..23d51be7d60a 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -361,6 +361,27 @@ config ARM64_ERRATUM_832075
 
           If unsure, say Y.
 
+config ARM64_ERRATUM_845719
+        bool "Cortex-A53: 845719: a load might read incorrect data"
+        depends on COMPAT
+        default y
+        help
+          This option adds an alternative code sequence to work around ARM
+          erratum 845719 on Cortex-A53 parts up to r0p4.
+
+          When running a compat (AArch32) userspace on an affected Cortex-A53
+          part, a load at EL0 from a virtual address that matches the bottom 32
+          bits of the virtual address used by a recent load at (AArch64) EL1
+          might return incorrect data.
+
+          The workaround is to write the contextidr_el1 register on exception
+          return to a 32-bit task.
+          Please note that this does not necessarily enable the workaround,
+          as it depends on the alternative framework, which will only patch
+          the kernel if an affected CPU is detected.
+
+          If unsure, say Y.
+
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