diff options
author | Catalin Marinas <catalin.marinas@arm.com> | 2014-04-22 11:14:29 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-04-25 07:06:38 -0400 |
commit | 1417a6b8dc4db73055be9a3aa288b050e9dc06ab (patch) | |
tree | 82fe7a3cb59ff82ddb74a8ebc6ff2d2e9237733b /arch/arm/vfp | |
parent | bc94081c6ac823c4723d8e36e9604c6cf3eba0ef (diff) |
ARM: 8036/1: Enable IRQs before attempting to read user space in __und_usr
The Undef abort handler in the kernel reads the undefined instruction
from user space. If the page table was modified from another CPU, the
user access could fail and do_page_fault() will be executed with
interrupts disabled. This can potentially deadlock on ARM11MPCore or on
Cortex-A15 with erratum 798181 workaround enabled (both implying IPI for
TLB maintenance with page table lock held).
This patch enables the IRQs in __und_usr before attempting to read the
instruction from user space.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Arun KS <getarunks@gmail.com>
Cc: Hartley Sweeten <hsweeten@visionengravers.com>
Cc: Ryan Mallon <rmallon@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/vfp')
-rw-r--r-- | arch/arm/vfp/entry.S | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S index f0759e70fb86..fe6ca574d093 100644 --- a/arch/arm/vfp/entry.S +++ b/arch/arm/vfp/entry.S | |||
@@ -22,11 +22,10 @@ | |||
22 | @ r9 = normal "successful" return address | 22 | @ r9 = normal "successful" return address |
23 | @ r10 = this threads thread_info structure | 23 | @ r10 = this threads thread_info structure |
24 | @ lr = unrecognised instruction return address | 24 | @ lr = unrecognised instruction return address |
25 | @ IRQs disabled. | 25 | @ IRQs enabled. |
26 | @ | 26 | @ |
27 | ENTRY(do_vfp) | 27 | ENTRY(do_vfp) |
28 | inc_preempt_count r10, r4 | 28 | inc_preempt_count r10, r4 |
29 | enable_irq | ||
30 | ldr r4, .LCvfp | 29 | ldr r4, .LCvfp |
31 | ldr r11, [r10, #TI_CPU] @ CPU number | 30 | ldr r11, [r10, #TI_CPU] @ CPU number |
32 | add r10, r10, #TI_VFPSTATE @ r10 = workspace | 31 | add r10, r10, #TI_VFPSTATE @ r10 = workspace |