diff options
author | Tomasz Figa <tomasz.figa@gmail.com> | 2013-06-17 10:45:44 -0400 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2013-06-18 14:13:18 -0400 |
commit | db3824e6bf0b0f421b0d43f08d905935e826a965 (patch) | |
tree | 3510d6e305d924636e526edf13c00a256e83d27f /arch/arm/plat-samsung | |
parent | 56bc7a1949d3c088b2eebcf03d42d299e4bc5b64 (diff) |
ARM: SAMSUNG: Remove unused plat/regs-watchdog.h header
Since there are no remaining users of this header, it can be safely
dropped.
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Tested-by: Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/plat-samsung')
-rw-r--r-- | arch/arm/plat-samsung/include/plat/regs-watchdog.h | 41 |
1 files changed, 0 insertions, 41 deletions
diff --git a/arch/arm/plat-samsung/include/plat/regs-watchdog.h b/arch/arm/plat-samsung/include/plat/regs-watchdog.h deleted file mode 100644 index 4938492470f7..000000000000 --- a/arch/arm/plat-samsung/include/plat/regs-watchdog.h +++ /dev/null | |||
@@ -1,41 +0,0 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h | ||
2 | * | ||
3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * S3C2410 Watchdog timer control | ||
11 | */ | ||
12 | |||
13 | |||
14 | #ifndef __ASM_ARCH_REGS_WATCHDOG_H | ||
15 | #define __ASM_ARCH_REGS_WATCHDOG_H | ||
16 | |||
17 | #define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG) | ||
18 | |||
19 | #define S3C2410_WTCON S3C_WDOGREG(0x00) | ||
20 | #define S3C2410_WTDAT S3C_WDOGREG(0x04) | ||
21 | #define S3C2410_WTCNT S3C_WDOGREG(0x08) | ||
22 | |||
23 | /* the watchdog can either generate a reset pulse, or an | ||
24 | * interrupt. | ||
25 | */ | ||
26 | |||
27 | #define S3C2410_WTCON_RSTEN (0x01) | ||
28 | #define S3C2410_WTCON_INTEN (1<<2) | ||
29 | #define S3C2410_WTCON_ENABLE (1<<5) | ||
30 | |||
31 | #define S3C2410_WTCON_DIV16 (0<<3) | ||
32 | #define S3C2410_WTCON_DIV32 (1<<3) | ||
33 | #define S3C2410_WTCON_DIV64 (2<<3) | ||
34 | #define S3C2410_WTCON_DIV128 (3<<3) | ||
35 | |||
36 | #define S3C2410_WTCON_PRESCALE(x) ((x) << 8) | ||
37 | #define S3C2410_WTCON_PRESCALE_MASK (0xff00) | ||
38 | |||
39 | #endif /* __ASM_ARCH_REGS_WATCHDOG_H */ | ||
40 | |||
41 | |||