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authorBen Dooks <ben-linux@fluff.org>2010-01-19 21:09:28 -0500
committerBen Dooks <ben-linux@fluff.org>2010-01-20 23:45:51 -0500
commit6890556c140469622497bea98cf49bf93f92f922 (patch)
tree67bf70c1bc46e02b77f2be9e659bff57bc2e844f /arch/arm/plat-samsung
parent54b89177ac533dc7439491afd26baf59464b425c (diff)
ARM: SAMSUNG: Move more support into plat-samsung
Move header files which are not likely to be touched in any further support addition out of plat-s3c's include directory into plat-samsung. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-samsung')
-rw-r--r--arch/arm/plat-samsung/include/plat/dma-core.h22
-rw-r--r--arch/arm/plat-samsung/include/plat/hwmon.h41
-rw-r--r--arch/arm/plat-samsung/include/plat/iic-core.h35
-rw-r--r--arch/arm/plat-samsung/include/plat/iic.h62
-rw-r--r--arch/arm/plat-samsung/include/plat/nand.h67
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-ac97.h67
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-adc.h63
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-iic.h56
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-irqtype.h21
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-nand.h123
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-rtc.h61
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h82
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-sdhci.h87
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-timer.h124
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h50
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h377
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-watchdog.h41
-rw-r--r--arch/arm/plat-samsung/include/plat/sdhci.h226
-rw-r--r--arch/arm/plat-samsung/include/plat/udc-hs.h29
-rw-r--r--arch/arm/plat-samsung/include/plat/watchdog-reset.h49
20 files changed, 1683 insertions, 0 deletions
diff --git a/arch/arm/plat-samsung/include/plat/dma-core.h b/arch/arm/plat-samsung/include/plat/dma-core.h
new file mode 100644
index 000000000000..32ff2a92cb3c
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/dma-core.h
@@ -0,0 +1,22 @@
1/* arch/arm/plat-s3c/include/plat/dma.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Samsung S3C DMA core support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15extern struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel);
16
17extern struct s3c2410_dma_chan *s3c_dma_chan_map[];
18
19/* the currently allocated channel information */
20extern struct s3c2410_dma_chan s3c2410_chans[];
21
22
diff --git a/arch/arm/plat-samsung/include/plat/hwmon.h b/arch/arm/plat-samsung/include/plat/hwmon.h
new file mode 100644
index 000000000000..1ba88ea0aa31
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/hwmon.h
@@ -0,0 +1,41 @@
1/* linux/arch/arm/plat-s3c/include/plat/hwmon.h
2 *
3 * Copyright 2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C - HWMon interface for ADC
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_ADC_HWMON_H
15#define __ASM_ARCH_ADC_HWMON_H __FILE__
16
17/**
18 * s3c_hwmon_chcfg - channel configuration
19 * @name: The name to give this channel.
20 * @mult: Multiply the ADC value read by this.
21 * @div: Divide the value from the ADC by this.
22 *
23 * The value read from the ADC is converted to a value that
24 * hwmon expects (mV) by result = (value_read * @mult) / @div.
25 */
26struct s3c_hwmon_chcfg {
27 const char *name;
28 unsigned int mult;
29 unsigned int div;
30};
31
32/**
33 * s3c_hwmon_pdata - HWMON platform data
34 * @in: One configuration for each possible channel used.
35 */
36struct s3c_hwmon_pdata {
37 struct s3c_hwmon_chcfg *in[8];
38};
39
40#endif /* __ASM_ARCH_ADC_HWMON_H */
41
diff --git a/arch/arm/plat-samsung/include/plat/iic-core.h b/arch/arm/plat-samsung/include/plat/iic-core.h
new file mode 100644
index 000000000000..36397ca20962
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/iic-core.h
@@ -0,0 +1,35 @@
1/* arch/arm/mach-s3c2410/include/mach/iic-core.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C - I2C Controller core functions
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_IIC_CORE_H
15#define __ASM_ARCH_IIC_CORE_H __FILE__
16
17/* These functions are only for use with the core support code, such as
18 * the cpu specific initialisation code
19 */
20
21/* re-define device name depending on support. */
22static inline void s3c_i2c0_setname(char *name)
23{
24 /* currently this device is always compiled in */
25 s3c_device_i2c0.name = name;
26}
27
28static inline void s3c_i2c1_setname(char *name)
29{
30#ifdef CONFIG_S3C_DEV_I2C1
31 s3c_device_i2c1.name = name;
32#endif
33}
34
35#endif /* __ASM_ARCH_IIC_H */
diff --git a/arch/arm/plat-samsung/include/plat/iic.h b/arch/arm/plat-samsung/include/plat/iic.h
new file mode 100644
index 000000000000..3083df00dee6
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/iic.h
@@ -0,0 +1,62 @@
1/* arch/arm/plat-s3c/include/plat/iic.h
2 *
3 * Copyright 2004-2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C - I2C Controller platform_device info
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_IIC_H
14#define __ASM_ARCH_IIC_H __FILE__
15
16#define S3C_IICFLG_FILTER (1<<0) /* enable s3c2440 filter */
17
18/**
19 * struct s3c2410_platform_i2c - Platform data for s3c I2C.
20 * @bus_num: The bus number to use (if possible).
21 * @flags: Any flags for the I2C bus (E.g. S3C_IICFLK_FILTER).
22 * @slave_addr: The I2C address for the slave device (if enabled).
23 * @frequency: The desired frequency in Hz of the bus. This is
24 * guaranteed to not be exceeded. If the caller does
25 * not care, use zero and the driver will select a
26 * useful default.
27 * @sda_delay: The delay (in ns) applied to SDA edges.
28 * @cfg_gpio: A callback to configure the pins for I2C operation.
29 */
30struct s3c2410_platform_i2c {
31 int bus_num;
32 unsigned int flags;
33 unsigned int slave_addr;
34 unsigned long frequency;
35 unsigned int sda_delay;
36
37 void (*cfg_gpio)(struct platform_device *dev);
38};
39
40/**
41 * s3c_i2c0_set_platdata - set platform data for i2c0 device
42 * @i2c: The platform data to set, or NULL for default data.
43 *
44 * Register the given platform data for use with the i2c0 device. This
45 * call copies the platform data, so the caller can use __initdata for
46 * their copy.
47 *
48 * This call will set cfg_gpio if is null to the default platform
49 * implementation.
50 *
51 * Any user of s3c_device_i2c0 should call this, even if it is with
52 * NULL to ensure that the device is given the default platform data
53 * as the driver will no longer carry defaults.
54 */
55extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c);
56extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c);
57
58/* defined by architecture to configure gpio */
59extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
60extern void s3c_i2c1_cfg_gpio(struct platform_device *dev);
61
62#endif /* __ASM_ARCH_IIC_H */
diff --git a/arch/arm/plat-samsung/include/plat/nand.h b/arch/arm/plat-samsung/include/plat/nand.h
new file mode 100644
index 000000000000..226147b7e026
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/nand.h
@@ -0,0 +1,67 @@
1/* arch/arm/mach-s3c2410/include/mach/nand.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - NAND device controller platfrom_device info
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/**
14 * struct s3c2410_nand_set - define a set of one or more nand chips
15 * @disable_ecc: Entirely disable ECC - Dangerous
16 * @flash_bbt: Openmoko u-boot can create a Bad Block Table
17 * Setting this flag will allow the kernel to
18 * look for it at boot time and also skip the NAND
19 * scan.
20 * @options: Default value to set into 'struct nand_chip' options.
21 * @nr_chips: Number of chips in this set
22 * @nr_partitions: Number of partitions pointed to by @partitions
23 * @name: Name of set (optional)
24 * @nr_map: Map for low-layer logical to physical chip numbers (option)
25 * @partitions: The mtd partition list
26 *
27 * define a set of one or more nand chips registered with an unique mtd. Also
28 * allows to pass flag to the underlying NAND layer. 'disable_ecc' will trigger
29 * a warning at boot time.
30 */
31struct s3c2410_nand_set {
32 unsigned int disable_ecc:1;
33 unsigned int flash_bbt:1;
34
35 unsigned int options;
36 int nr_chips;
37 int nr_partitions;
38 char *name;
39 int *nr_map;
40 struct mtd_partition *partitions;
41 struct nand_ecclayout *ecc_layout;
42};
43
44struct s3c2410_platform_nand {
45 /* timing information for controller, all times in nanoseconds */
46
47 int tacls; /* time for active CLE/ALE to nWE/nOE */
48 int twrph0; /* active time for nWE/nOE */
49 int twrph1; /* time for release CLE/ALE from nWE/nOE inactive */
50
51 unsigned int ignore_unset_ecc:1;
52
53 int nr_sets;
54 struct s3c2410_nand_set *sets;
55
56 void (*select_chip)(struct s3c2410_nand_set *,
57 int chip);
58};
59
60/**
61 * s3c_nand_set_platdata() - register NAND platform data.
62 * @nand: The NAND platform data to register with s3c_device_nand.
63 *
64 * This function copies the given NAND platform data, @nand and registers
65 * it with the s3c_device_nand. This allows @nand to be __initdata.
66*/
67extern void s3c_nand_set_platdata(struct s3c2410_platform_nand *nand);
diff --git a/arch/arm/plat-samsung/include/plat/regs-ac97.h b/arch/arm/plat-samsung/include/plat/regs-ac97.h
new file mode 100644
index 000000000000..c3878f7acb83
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-ac97.h
@@ -0,0 +1,67 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-ac97.h
2 *
3 * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2440 AC97 Controller
11*/
12
13#ifndef __ASM_ARCH_REGS_AC97_H
14#define __ASM_ARCH_REGS_AC97_H __FILE__
15
16#define S3C_AC97_GLBCTRL (0x00)
17
18#define S3C_AC97_GLBCTRL_CODECREADYIE (1<<22)
19#define S3C_AC97_GLBCTRL_PCMOUTURIE (1<<21)
20#define S3C_AC97_GLBCTRL_PCMINORIE (1<<20)
21#define S3C_AC97_GLBCTRL_MICINORIE (1<<19)
22#define S3C_AC97_GLBCTRL_PCMOUTTIE (1<<18)
23#define S3C_AC97_GLBCTRL_PCMINTIE (1<<17)
24#define S3C_AC97_GLBCTRL_MICINTIE (1<<16)
25#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF (0<<12)
26#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO (1<<12)
27#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA (2<<12)
28#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK (3<<12)
29#define S3C_AC97_GLBCTRL_PCMINTM_OFF (0<<10)
30#define S3C_AC97_GLBCTRL_PCMINTM_PIO (1<<10)
31#define S3C_AC97_GLBCTRL_PCMINTM_DMA (2<<10)
32#define S3C_AC97_GLBCTRL_PCMINTM_MASK (3<<10)
33#define S3C_AC97_GLBCTRL_MICINTM_OFF (0<<8)
34#define S3C_AC97_GLBCTRL_MICINTM_PIO (1<<8)
35#define S3C_AC97_GLBCTRL_MICINTM_DMA (2<<8)
36#define S3C_AC97_GLBCTRL_MICINTM_MASK (3<<8)
37#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE (1<<3)
38#define S3C_AC97_GLBCTRL_ACLINKON (1<<2)
39#define S3C_AC97_GLBCTRL_WARMRESET (1<<1)
40#define S3C_AC97_GLBCTRL_COLDRESET (1<<0)
41
42#define S3C_AC97_GLBSTAT (0x04)
43
44#define S3C_AC97_GLBSTAT_CODECREADY (1<<22)
45#define S3C_AC97_GLBSTAT_PCMOUTUR (1<<21)
46#define S3C_AC97_GLBSTAT_PCMINORI (1<<20)
47#define S3C_AC97_GLBSTAT_MICINORI (1<<19)
48#define S3C_AC97_GLBSTAT_PCMOUTTI (1<<18)
49#define S3C_AC97_GLBSTAT_PCMINTI (1<<17)
50#define S3C_AC97_GLBSTAT_MICINTI (1<<16)
51#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE (0<<0)
52#define S3C_AC97_GLBSTAT_MAINSTATE_INIT (1<<0)
53#define S3C_AC97_GLBSTAT_MAINSTATE_READY (2<<0)
54#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE (3<<0)
55#define S3C_AC97_GLBSTAT_MAINSTATE_LP (4<<0)
56#define S3C_AC97_GLBSTAT_MAINSTATE_WARM (5<<0)
57
58#define S3C_AC97_CODEC_CMD (0x08)
59
60#define S3C_AC97_CODEC_CMD_READ (1<<23)
61
62#define S3C_AC97_STAT (0x0c)
63#define S3C_AC97_PCM_ADDR (0x10)
64#define S3C_AC97_PCM_DATA (0x18)
65#define S3C_AC97_MIC_DATA (0x1C)
66
67#endif /* __ASM_ARCH_REGS_AC97_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-adc.h b/arch/arm/plat-samsung/include/plat/regs-adc.h
new file mode 100644
index 000000000000..f43c8dab39e4
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-adc.h
@@ -0,0 +1,63 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-adc.h
2 *
3 * Copyright (c) 2004 Shannon Holland <holland@loser.net>
4 *
5 * This program is free software; yosu can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * S3C2410 ADC registers
10*/
11
12#ifndef __ASM_ARCH_REGS_ADC_H
13#define __ASM_ARCH_REGS_ADC_H "regs-adc.h"
14
15#define S3C2410_ADCREG(x) (x)
16
17#define S3C2410_ADCCON S3C2410_ADCREG(0x00)
18#define S3C2410_ADCTSC S3C2410_ADCREG(0x04)
19#define S3C2410_ADCDLY S3C2410_ADCREG(0x08)
20#define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C)
21#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10)
22#define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14)
23#define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18)
24#define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20)
25
26
27/* ADCCON Register Bits */
28#define S3C2410_ADCCON_ECFLG (1<<15)
29#define S3C2410_ADCCON_PRSCEN (1<<14)
30#define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6)
31#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6)
32#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3)
33#define S3C2410_ADCCON_MUXMASK (0x7<<3)
34#define S3C2410_ADCCON_STDBM (1<<2)
35#define S3C2410_ADCCON_READ_START (1<<1)
36#define S3C2410_ADCCON_ENABLE_START (1<<0)
37#define S3C2410_ADCCON_STARTMASK (0x3<<0)
38
39
40/* ADCTSC Register Bits */
41#define S3C2410_ADCTSC_YM_SEN (1<<7)
42#define S3C2410_ADCTSC_YP_SEN (1<<6)
43#define S3C2410_ADCTSC_XM_SEN (1<<5)
44#define S3C2410_ADCTSC_XP_SEN (1<<4)
45#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3)
46#define S3C2410_ADCTSC_AUTO_PST (1<<2)
47#define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0)
48
49/* ADCDAT0 Bits */
50#define S3C2410_ADCDAT0_UPDOWN (1<<15)
51#define S3C2410_ADCDAT0_AUTO_PST (1<<14)
52#define S3C2410_ADCDAT0_XY_PST (0x3<<12)
53#define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF)
54
55/* ADCDAT1 Bits */
56#define S3C2410_ADCDAT1_UPDOWN (1<<15)
57#define S3C2410_ADCDAT1_AUTO_PST (1<<14)
58#define S3C2410_ADCDAT1_XY_PST (0x3<<12)
59#define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF)
60
61#endif /* __ASM_ARCH_REGS_ADC_H */
62
63
diff --git a/arch/arm/plat-samsung/include/plat/regs-iic.h b/arch/arm/plat-samsung/include/plat/regs-iic.h
new file mode 100644
index 000000000000..2f7c17de8ac8
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-iic.h
@@ -0,0 +1,56 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-iic.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 I2C Controller
11*/
12
13#ifndef __ASM_ARCH_REGS_IIC_H
14#define __ASM_ARCH_REGS_IIC_H __FILE__
15
16/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
17
18#define S3C2410_IICREG(x) (x)
19
20#define S3C2410_IICCON S3C2410_IICREG(0x00)
21#define S3C2410_IICSTAT S3C2410_IICREG(0x04)
22#define S3C2410_IICADD S3C2410_IICREG(0x08)
23#define S3C2410_IICDS S3C2410_IICREG(0x0C)
24#define S3C2440_IICLC S3C2410_IICREG(0x10)
25
26#define S3C2410_IICCON_ACKEN (1<<7)
27#define S3C2410_IICCON_TXDIV_16 (0<<6)
28#define S3C2410_IICCON_TXDIV_512 (1<<6)
29#define S3C2410_IICCON_IRQEN (1<<5)
30#define S3C2410_IICCON_IRQPEND (1<<4)
31#define S3C2410_IICCON_SCALE(x) ((x)&15)
32#define S3C2410_IICCON_SCALEMASK (0xf)
33
34#define S3C2410_IICSTAT_MASTER_RX (2<<6)
35#define S3C2410_IICSTAT_MASTER_TX (3<<6)
36#define S3C2410_IICSTAT_SLAVE_RX (0<<6)
37#define S3C2410_IICSTAT_SLAVE_TX (1<<6)
38#define S3C2410_IICSTAT_MODEMASK (3<<6)
39
40#define S3C2410_IICSTAT_START (1<<5)
41#define S3C2410_IICSTAT_BUSBUSY (1<<5)
42#define S3C2410_IICSTAT_TXRXEN (1<<4)
43#define S3C2410_IICSTAT_ARBITR (1<<3)
44#define S3C2410_IICSTAT_ASSLAVE (1<<2)
45#define S3C2410_IICSTAT_ADDR0 (1<<1)
46#define S3C2410_IICSTAT_LASTBIT (1<<0)
47
48#define S3C2410_IICLC_SDA_DELAY0 (0 << 0)
49#define S3C2410_IICLC_SDA_DELAY5 (1 << 0)
50#define S3C2410_IICLC_SDA_DELAY10 (2 << 0)
51#define S3C2410_IICLC_SDA_DELAY15 (3 << 0)
52#define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0)
53
54#define S3C2410_IICLC_FILTER_ON (1<<2)
55
56#endif /* __ASM_ARCH_REGS_IIC_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-irqtype.h b/arch/arm/plat-samsung/include/plat/regs-irqtype.h
new file mode 100644
index 000000000000..c63cd3fc5ad3
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-irqtype.h
@@ -0,0 +1,21 @@
1/* arch/arm/plat-s3c/include/plat/regs-irqtype.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C - IRQ detection types.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14/* values for S3C2410_EXTINT0/1/2 and other cpus in the series, including
15 * the S3C64XX
16*/
17#define S3C2410_EXTINT_LOWLEV (0x00)
18#define S3C2410_EXTINT_HILEV (0x01)
19#define S3C2410_EXTINT_FALLEDGE (0x02)
20#define S3C2410_EXTINT_RISEEDGE (0x04)
21#define S3C2410_EXTINT_BOTHEDGE (0x06)
diff --git a/arch/arm/plat-samsung/include/plat/regs-nand.h b/arch/arm/plat-samsung/include/plat/regs-nand.h
new file mode 100644
index 000000000000..238efea7b9e4
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-nand.h
@@ -0,0 +1,123 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-nand.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 NAND register definitions
11*/
12
13#ifndef __ASM_ARM_REGS_NAND
14#define __ASM_ARM_REGS_NAND
15
16
17#define S3C2410_NFREG(x) (x)
18
19#define S3C2410_NFCONF S3C2410_NFREG(0x00)
20#define S3C2410_NFCMD S3C2410_NFREG(0x04)
21#define S3C2410_NFADDR S3C2410_NFREG(0x08)
22#define S3C2410_NFDATA S3C2410_NFREG(0x0C)
23#define S3C2410_NFSTAT S3C2410_NFREG(0x10)
24#define S3C2410_NFECC S3C2410_NFREG(0x14)
25
26#define S3C2440_NFCONT S3C2410_NFREG(0x04)
27#define S3C2440_NFCMD S3C2410_NFREG(0x08)
28#define S3C2440_NFADDR S3C2410_NFREG(0x0C)
29#define S3C2440_NFDATA S3C2410_NFREG(0x10)
30#define S3C2440_NFECCD0 S3C2410_NFREG(0x14)
31#define S3C2440_NFECCD1 S3C2410_NFREG(0x18)
32#define S3C2440_NFECCD S3C2410_NFREG(0x1C)
33#define S3C2440_NFSTAT S3C2410_NFREG(0x20)
34#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
35#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
36#define S3C2440_NFMECC0 S3C2410_NFREG(0x2C)
37#define S3C2440_NFMECC1 S3C2410_NFREG(0x30)
38#define S3C2440_NFSECC S3C2410_NFREG(0x34)
39#define S3C2440_NFSBLK S3C2410_NFREG(0x38)
40#define S3C2440_NFEBLK S3C2410_NFREG(0x3C)
41
42#define S3C2412_NFSBLK S3C2410_NFREG(0x20)
43#define S3C2412_NFEBLK S3C2410_NFREG(0x24)
44#define S3C2412_NFSTAT S3C2410_NFREG(0x28)
45#define S3C2412_NFMECC_ERR0 S3C2410_NFREG(0x2C)
46#define S3C2412_NFMECC_ERR1 S3C2410_NFREG(0x30)
47#define S3C2412_NFMECC0 S3C2410_NFREG(0x34)
48#define S3C2412_NFMECC1 S3C2410_NFREG(0x38)
49#define S3C2412_NFSECC S3C2410_NFREG(0x3C)
50
51#define S3C2410_NFCONF_EN (1<<15)
52#define S3C2410_NFCONF_512BYTE (1<<14)
53#define S3C2410_NFCONF_4STEP (1<<13)
54#define S3C2410_NFCONF_INITECC (1<<12)
55#define S3C2410_NFCONF_nFCE (1<<11)
56#define S3C2410_NFCONF_TACLS(x) ((x)<<8)
57#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
58#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
59
60#define S3C2410_NFSTAT_BUSY (1<<0)
61
62#define S3C2440_NFCONF_BUSWIDTH_8 (0<<0)
63#define S3C2440_NFCONF_BUSWIDTH_16 (1<<0)
64#define S3C2440_NFCONF_ADVFLASH (1<<3)
65#define S3C2440_NFCONF_TACLS(x) ((x)<<12)
66#define S3C2440_NFCONF_TWRPH0(x) ((x)<<8)
67#define S3C2440_NFCONF_TWRPH1(x) ((x)<<4)
68
69#define S3C2440_NFCONT_LOCKTIGHT (1<<13)
70#define S3C2440_NFCONT_SOFTLOCK (1<<12)
71#define S3C2440_NFCONT_ILLEGALACC_EN (1<<10)
72#define S3C2440_NFCONT_RNBINT_EN (1<<9)
73#define S3C2440_NFCONT_RN_FALLING (1<<8)
74#define S3C2440_NFCONT_SPARE_ECCLOCK (1<<6)
75#define S3C2440_NFCONT_MAIN_ECCLOCK (1<<5)
76#define S3C2440_NFCONT_INITECC (1<<4)
77#define S3C2440_NFCONT_nFCE (1<<1)
78#define S3C2440_NFCONT_ENABLE (1<<0)
79
80#define S3C2440_NFSTAT_READY (1<<0)
81#define S3C2440_NFSTAT_nCE (1<<1)
82#define S3C2440_NFSTAT_RnB_CHANGE (1<<2)
83#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1<<3)
84
85#define S3C2412_NFCONF_NANDBOOT (1<<31)
86#define S3C2412_NFCONF_ECCCLKCON (1<<30)
87#define S3C2412_NFCONF_ECC_MLC (1<<24)
88#define S3C2412_NFCONF_TACLS_MASK (7<<12) /* 1 extra bit of Tacls */
89
90#define S3C2412_NFCONT_ECC4_DIRWR (1<<18)
91#define S3C2412_NFCONT_LOCKTIGHT (1<<17)
92#define S3C2412_NFCONT_SOFTLOCK (1<<16)
93#define S3C2412_NFCONT_ECC4_ENCINT (1<<13)
94#define S3C2412_NFCONT_ECC4_DECINT (1<<12)
95#define S3C2412_NFCONT_MAIN_ECC_LOCK (1<<7)
96#define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5)
97#define S3C2412_NFCONT_nFCE1 (1<<2)
98#define S3C2412_NFCONT_nFCE0 (1<<1)
99
100#define S3C2412_NFSTAT_ECC_ENCDONE (1<<7)
101#define S3C2412_NFSTAT_ECC_DECDONE (1<<6)
102#define S3C2412_NFSTAT_ILLEGAL_ACCESS (1<<5)
103#define S3C2412_NFSTAT_RnB_CHANGE (1<<4)
104#define S3C2412_NFSTAT_nFCE1 (1<<3)
105#define S3C2412_NFSTAT_nFCE0 (1<<2)
106#define S3C2412_NFSTAT_Res1 (1<<1)
107#define S3C2412_NFSTAT_READY (1<<0)
108
109#define S3C2412_NFECCERR_SERRDATA(x) (((x) >> 21) & 0xf)
110#define S3C2412_NFECCERR_SERRBIT(x) (((x) >> 18) & 0x7)
111#define S3C2412_NFECCERR_MERRDATA(x) (((x) >> 7) & 0x3ff)
112#define S3C2412_NFECCERR_MERRBIT(x) (((x) >> 4) & 0x7)
113#define S3C2412_NFECCERR_SPARE_ERR(x) (((x) >> 2) & 0x3)
114#define S3C2412_NFECCERR_MAIN_ERR(x) (((x) >> 2) & 0x3)
115#define S3C2412_NFECCERR_NONE (0)
116#define S3C2412_NFECCERR_1BIT (1)
117#define S3C2412_NFECCERR_MULTIBIT (2)
118#define S3C2412_NFECCERR_ECCAREA (3)
119
120
121
122#endif /* __ASM_ARM_REGS_NAND */
123
diff --git a/arch/arm/plat-samsung/include/plat/regs-rtc.h b/arch/arm/plat-samsung/include/plat/regs-rtc.h
new file mode 100644
index 000000000000..d5837cf8e402
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-rtc.h
@@ -0,0 +1,61 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-rtc.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Internal RTC register definition
11*/
12
13#ifndef __ASM_ARCH_REGS_RTC_H
14#define __ASM_ARCH_REGS_RTC_H __FILE__
15
16#define S3C2410_RTCREG(x) (x)
17
18#define S3C2410_RTCCON S3C2410_RTCREG(0x40)
19#define S3C2410_RTCCON_RTCEN (1<<0)
20#define S3C2410_RTCCON_CLKSEL (1<<1)
21#define S3C2410_RTCCON_CNTSEL (1<<2)
22#define S3C2410_RTCCON_CLKRST (1<<3)
23
24#define S3C2410_TICNT S3C2410_RTCREG(0x44)
25#define S3C2410_TICNT_ENABLE (1<<7)
26
27#define S3C2410_RTCALM S3C2410_RTCREG(0x50)
28#define S3C2410_RTCALM_ALMEN (1<<6)
29#define S3C2410_RTCALM_YEAREN (1<<5)
30#define S3C2410_RTCALM_MONEN (1<<4)
31#define S3C2410_RTCALM_DAYEN (1<<3)
32#define S3C2410_RTCALM_HOUREN (1<<2)
33#define S3C2410_RTCALM_MINEN (1<<1)
34#define S3C2410_RTCALM_SECEN (1<<0)
35
36#define S3C2410_RTCALM_ALL \
37 S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
38 S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
39 S3C2410_RTCALM_SECEN
40
41
42#define S3C2410_ALMSEC S3C2410_RTCREG(0x54)
43#define S3C2410_ALMMIN S3C2410_RTCREG(0x58)
44#define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c)
45
46#define S3C2410_ALMDATE S3C2410_RTCREG(0x60)
47#define S3C2410_ALMMON S3C2410_RTCREG(0x64)
48#define S3C2410_ALMYEAR S3C2410_RTCREG(0x68)
49
50#define S3C2410_RTCRST S3C2410_RTCREG(0x6c)
51
52#define S3C2410_RTCSEC S3C2410_RTCREG(0x70)
53#define S3C2410_RTCMIN S3C2410_RTCREG(0x74)
54#define S3C2410_RTCHOUR S3C2410_RTCREG(0x78)
55#define S3C2410_RTCDATE S3C2410_RTCREG(0x7c)
56#define S3C2410_RTCDAY S3C2410_RTCREG(0x80)
57#define S3C2410_RTCMON S3C2410_RTCREG(0x84)
58#define S3C2410_RTCYEAR S3C2410_RTCREG(0x88)
59
60
61#endif /* __ASM_ARCH_REGS_RTC_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h b/arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h
new file mode 100644
index 000000000000..abf2fbc2eb2f
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h
@@ -0,0 +1,82 @@
1/* linux/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h
2 *
3 * Copyright 2007 Simtec Electronics <linux@simtec.co.uk>
4 * http://armlinux.simtec.co.uk/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2412 IIS register definition
11*/
12
13#ifndef __ASM_ARCH_REGS_S3C2412_IIS_H
14#define __ASM_ARCH_REGS_S3C2412_IIS_H
15
16#define S3C2412_IISCON (0x00)
17#define S3C2412_IISMOD (0x04)
18#define S3C2412_IISFIC (0x08)
19#define S3C2412_IISPSR (0x0C)
20#define S3C2412_IISTXD (0x10)
21#define S3C2412_IISRXD (0x14)
22
23#define S3C2412_IISCON_LRINDEX (1 << 11)
24#define S3C2412_IISCON_TXFIFO_EMPTY (1 << 10)
25#define S3C2412_IISCON_RXFIFO_EMPTY (1 << 9)
26#define S3C2412_IISCON_TXFIFO_FULL (1 << 8)
27#define S3C2412_IISCON_RXFIFO_FULL (1 << 7)
28#define S3C2412_IISCON_TXDMA_PAUSE (1 << 6)
29#define S3C2412_IISCON_RXDMA_PAUSE (1 << 5)
30#define S3C2412_IISCON_TXCH_PAUSE (1 << 4)
31#define S3C2412_IISCON_RXCH_PAUSE (1 << 3)
32#define S3C2412_IISCON_TXDMA_ACTIVE (1 << 2)
33#define S3C2412_IISCON_RXDMA_ACTIVE (1 << 1)
34#define S3C2412_IISCON_IIS_ACTIVE (1 << 0)
35
36#define S3C64XX_IISMOD_BLC_16BIT (0 << 13)
37#define S3C64XX_IISMOD_BLC_8BIT (1 << 13)
38#define S3C64XX_IISMOD_BLC_24BIT (2 << 13)
39#define S3C64XX_IISMOD_BLC_MASK (3 << 13)
40
41#define S3C64XX_IISMOD_IMS_PCLK (0 << 10)
42#define S3C64XX_IISMOD_IMS_SYSMUX (1 << 10)
43
44#define S3C2412_IISMOD_MASTER_INTERNAL (0 << 10)
45#define S3C2412_IISMOD_MASTER_EXTERNAL (1 << 10)
46#define S3C2412_IISMOD_SLAVE (2 << 10)
47#define S3C2412_IISMOD_MASTER_MASK (3 << 10)
48#define S3C2412_IISMOD_MODE_TXONLY (0 << 8)
49#define S3C2412_IISMOD_MODE_RXONLY (1 << 8)
50#define S3C2412_IISMOD_MODE_TXRX (2 << 8)
51#define S3C2412_IISMOD_MODE_MASK (3 << 8)
52#define S3C2412_IISMOD_LR_LLOW (0 << 7)
53#define S3C2412_IISMOD_LR_RLOW (1 << 7)
54#define S3C2412_IISMOD_SDF_IIS (0 << 5)
55#define S3C2412_IISMOD_SDF_MSB (1 << 5)
56#define S3C2412_IISMOD_SDF_LSB (2 << 5)
57#define S3C2412_IISMOD_SDF_MASK (3 << 5)
58#define S3C2412_IISMOD_RCLK_256FS (0 << 3)
59#define S3C2412_IISMOD_RCLK_512FS (1 << 3)
60#define S3C2412_IISMOD_RCLK_384FS (2 << 3)
61#define S3C2412_IISMOD_RCLK_768FS (3 << 3)
62#define S3C2412_IISMOD_RCLK_MASK (3 << 3)
63#define S3C2412_IISMOD_BCLK_32FS (0 << 1)
64#define S3C2412_IISMOD_BCLK_48FS (1 << 1)
65#define S3C2412_IISMOD_BCLK_16FS (2 << 1)
66#define S3C2412_IISMOD_BCLK_24FS (3 << 1)
67#define S3C2412_IISMOD_BCLK_MASK (3 << 1)
68#define S3C2412_IISMOD_8BIT (1 << 0)
69
70#define S3C64XX_IISMOD_CDCLKCON (1 << 12)
71
72#define S3C2412_IISPSR_PSREN (1 << 15)
73
74#define S3C2412_IISFIC_TXFLUSH (1 << 15)
75#define S3C2412_IISFIC_RXFLUSH (1 << 7)
76#define S3C2412_IISFIC_TXCOUNT(x) (((x) >> 8) & 0xf)
77#define S3C2412_IISFIC_RXCOUNT(x) (((x) >> 0) & 0xf)
78
79
80
81#endif /* __ASM_ARCH_REGS_S3C2412_IIS_H */
82
diff --git a/arch/arm/plat-samsung/include/plat/regs-sdhci.h b/arch/arm/plat-samsung/include/plat/regs-sdhci.h
new file mode 100644
index 000000000000..e34049ad44cc
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-sdhci.h
@@ -0,0 +1,87 @@
1/* linux/arch/arm/plat-s3c/include/plat/regs-sdhci.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C Platform - SDHCI (HSMMC) register definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C_SDHCI_REGS_H
16#define __PLAT_S3C_SDHCI_REGS_H __FILE__
17
18#define S3C_SDHCI_CONTROL2 (0x80)
19#define S3C_SDHCI_CONTROL3 (0x84)
20#define S3C64XX_SDHCI_CONTROL4 (0x8C)
21
22#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31)
23#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK (1 << 30)
24#define S3C_SDHCI_CTRL2_CDINVRXD3 (1 << 29)
25#define S3C_SDHCI_CTRL2_SLCARDOUT (1 << 28)
26
27#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
28#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
29#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
30
31#define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
32#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16)
33#define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
34
35#define S3C_SDHCI_CTRL2_ENFBCLKTX (1 << 15)
36#define S3C_SDHCI_CTRL2_ENFBCLKRX (1 << 14)
37#define S3C_SDHCI_CTRL2_SDCDSEL (1 << 13)
38#define S3C_SDHCI_CTRL2_SDSIGPC (1 << 12)
39#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11)
40
41#define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9)
42#define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9)
43#define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9)
44#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9)
45#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9)
46#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9)
47
48#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8)
49#define S3C_SDHCI_CTRL2_RWAITMODE (1 << 7)
50#define S3C_SDHCI_CTRL2_DISBUFRD (1 << 6)
51#define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4)
52#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4)
53#define S3C_SDHCI_CTRL2_PWRSYNC (1 << 3)
54#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1)
55#define S3C_SDHCI_CTRL2_HWINITFIN (1 << 0)
56
57#define S3C_SDHCI_CTRL3_FCSEL3 (1 << 31)
58#define S3C_SDHCI_CTRL3_FCSEL2 (1 << 23)
59#define S3C_SDHCI_CTRL3_FCSEL1 (1 << 15)
60#define S3C_SDHCI_CTRL3_FCSEL0 (1 << 7)
61
62#define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24)
63#define S3C_SDHCI_CTRL3_FIA3_SHIFT (24)
64#define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24)
65
66#define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16)
67#define S3C_SDHCI_CTRL3_FIA2_SHIFT (16)
68#define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16)
69
70#define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
71#define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
72#define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
73
74#define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0)
75#define S3C_SDHCI_CTRL3_FIA0_SHIFT (0)
76#define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0)
77
78#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16)
79#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16)
80#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16)
81#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16)
82#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16)
83#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16)
84
85#define S3C64XX_SDHCI_CONTROL4_BUSY (1)
86
87#endif /* __PLAT_S3C_SDHCI_REGS_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-timer.h b/arch/arm/plat-samsung/include/plat/regs-timer.h
new file mode 100644
index 000000000000..d097d92f8cc7
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-timer.h
@@ -0,0 +1,124 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-timer.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Timer configuration
11*/
12
13#ifndef __ASM_ARCH_REGS_TIMER_H
14#define __ASM_ARCH_REGS_TIMER_H
15
16#define S3C_TIMERREG(x) (S3C_VA_TIMER + (x))
17#define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c))
18
19#define S3C2410_TCFG0 S3C_TIMERREG(0x00)
20#define S3C2410_TCFG1 S3C_TIMERREG(0x04)
21#define S3C2410_TCON S3C_TIMERREG(0x08)
22
23#define S3C64XX_TINT_CSTAT S3C_TIMERREG(0x44)
24
25#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
26#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
27#define S3C2410_TCFG_PRESCALER1_SHIFT (8)
28#define S3C2410_TCFG_DEADZONE_MASK (255<<16)
29#define S3C2410_TCFG_DEADZONE_SHIFT (16)
30
31#define S3C2410_TCFG1_MUX4_DIV2 (0<<16)
32#define S3C2410_TCFG1_MUX4_DIV4 (1<<16)
33#define S3C2410_TCFG1_MUX4_DIV8 (2<<16)
34#define S3C2410_TCFG1_MUX4_DIV16 (3<<16)
35#define S3C2410_TCFG1_MUX4_TCLK1 (4<<16)
36#define S3C2410_TCFG1_MUX4_MASK (15<<16)
37#define S3C2410_TCFG1_MUX4_SHIFT (16)
38
39#define S3C2410_TCFG1_MUX3_DIV2 (0<<12)
40#define S3C2410_TCFG1_MUX3_DIV4 (1<<12)
41#define S3C2410_TCFG1_MUX3_DIV8 (2<<12)
42#define S3C2410_TCFG1_MUX3_DIV16 (3<<12)
43#define S3C2410_TCFG1_MUX3_TCLK1 (4<<12)
44#define S3C2410_TCFG1_MUX3_MASK (15<<12)
45
46
47#define S3C2410_TCFG1_MUX2_DIV2 (0<<8)
48#define S3C2410_TCFG1_MUX2_DIV4 (1<<8)
49#define S3C2410_TCFG1_MUX2_DIV8 (2<<8)
50#define S3C2410_TCFG1_MUX2_DIV16 (3<<8)
51#define S3C2410_TCFG1_MUX2_TCLK1 (4<<8)
52#define S3C2410_TCFG1_MUX2_MASK (15<<8)
53
54
55#define S3C2410_TCFG1_MUX1_DIV2 (0<<4)
56#define S3C2410_TCFG1_MUX1_DIV4 (1<<4)
57#define S3C2410_TCFG1_MUX1_DIV8 (2<<4)
58#define S3C2410_TCFG1_MUX1_DIV16 (3<<4)
59#define S3C2410_TCFG1_MUX1_TCLK0 (4<<4)
60#define S3C2410_TCFG1_MUX1_MASK (15<<4)
61
62#define S3C2410_TCFG1_MUX0_DIV2 (0<<0)
63#define S3C2410_TCFG1_MUX0_DIV4 (1<<0)
64#define S3C2410_TCFG1_MUX0_DIV8 (2<<0)
65#define S3C2410_TCFG1_MUX0_DIV16 (3<<0)
66#define S3C2410_TCFG1_MUX0_TCLK0 (4<<0)
67#define S3C2410_TCFG1_MUX0_MASK (15<<0)
68
69#define S3C2410_TCFG1_MUX_DIV2 (0<<0)
70#define S3C2410_TCFG1_MUX_DIV4 (1<<0)
71#define S3C2410_TCFG1_MUX_DIV8 (2<<0)
72#define S3C2410_TCFG1_MUX_DIV16 (3<<0)
73#define S3C2410_TCFG1_MUX_TCLK (4<<0)
74#define S3C2410_TCFG1_MUX_MASK (15<<0)
75
76#define S3C64XX_TCFG1_MUX_DIV1 (0<<0)
77#define S3C64XX_TCFG1_MUX_DIV2 (1<<0)
78#define S3C64XX_TCFG1_MUX_DIV4 (2<<0)
79#define S3C64XX_TCFG1_MUX_DIV8 (3<<0)
80#define S3C64XX_TCFG1_MUX_DIV16 (4<<0)
81#define S3C64XX_TCFG1_MUX_TCLK (5<<0) /* 3 sets of TCLK */
82#define S3C64XX_TCFG1_MUX_MASK (15<<0)
83
84#define S3C2410_TCFG1_SHIFT(x) ((x) * 4)
85
86/* for each timer, we have an count buffer, an compare buffer and
87 * an observation buffer
88*/
89
90/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
91
92#define S3C2410_TCNTB(tmr) S3C_TIMERREG2(tmr, 0x00)
93#define S3C2410_TCMPB(tmr) S3C_TIMERREG2(tmr, 0x04)
94#define S3C2410_TCNTO(tmr) S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
95
96#define S3C2410_TCON_T4RELOAD (1<<22)
97#define S3C2410_TCON_T4MANUALUPD (1<<21)
98#define S3C2410_TCON_T4START (1<<20)
99
100#define S3C2410_TCON_T3RELOAD (1<<19)
101#define S3C2410_TCON_T3INVERT (1<<18)
102#define S3C2410_TCON_T3MANUALUPD (1<<17)
103#define S3C2410_TCON_T3START (1<<16)
104
105#define S3C2410_TCON_T2RELOAD (1<<15)
106#define S3C2410_TCON_T2INVERT (1<<14)
107#define S3C2410_TCON_T2MANUALUPD (1<<13)
108#define S3C2410_TCON_T2START (1<<12)
109
110#define S3C2410_TCON_T1RELOAD (1<<11)
111#define S3C2410_TCON_T1INVERT (1<<10)
112#define S3C2410_TCON_T1MANUALUPD (1<<9)
113#define S3C2410_TCON_T1START (1<<8)
114
115#define S3C2410_TCON_T0DEADZONE (1<<4)
116#define S3C2410_TCON_T0RELOAD (1<<3)
117#define S3C2410_TCON_T0INVERT (1<<2)
118#define S3C2410_TCON_T0MANUALUPD (1<<1)
119#define S3C2410_TCON_T0START (1<<0)
120
121#endif /* __ASM_ARCH_REGS_TIMER_H */
122
123
124
diff --git a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h
new file mode 100644
index 000000000000..36a85f5000c8
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h
@@ -0,0 +1,50 @@
1/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C - USB2.0 Highspeed/OtG device PHY registers
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* Note, this is a seperate header file as some of the clock framework
16 * needs to touch this if the clk_48m is used as the USB OHCI or other
17 * peripheral source.
18*/
19
20#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H
21#define __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H __FILE__
22
23/* S3C64XX_PA_USB_HSPHY */
24
25#define S3C_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY)
26
27#define S3C_PHYPWR S3C_HSOTG_PHYREG(0x00)
28#define SRC_PHYPWR_OTG_DISABLE (1 << 4)
29#define SRC_PHYPWR_ANALOG_POWERDOWN (1 << 3)
30#define SRC_PHYPWR_FORCE_SUSPEND (1 << 1)
31
32#define S3C_PHYCLK S3C_HSOTG_PHYREG(0x04)
33#define S3C_PHYCLK_MODE_USB11 (1 << 6)
34#define S3C_PHYCLK_EXT_OSC (1 << 5)
35#define S3C_PHYCLK_CLK_FORCE (1 << 4)
36#define S3C_PHYCLK_ID_PULL (1 << 2)
37#define S3C_PHYCLK_CLKSEL_MASK (0x3 << 0)
38#define S3C_PHYCLK_CLKSEL_SHIFT (0)
39#define S3C_PHYCLK_CLKSEL_48M (0x0 << 0)
40#define S3C_PHYCLK_CLKSEL_12M (0x2 << 0)
41#define S3C_PHYCLK_CLKSEL_24M (0x3 << 0)
42
43#define S3C_RSTCON S3C_HSOTG_PHYREG(0x08)
44#define S3C_RSTCON_PHYCLK (1 << 2)
45#define S3C_RSTCON_HCLK (1 << 2)
46#define S3C_RSTCON_PHY (1 << 0)
47
48#define S3C_PHYTUNE S3C_HSOTG_PHYREG(0x20)
49
50#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h
new file mode 100644
index 000000000000..8d18d9d4d148
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h
@@ -0,0 +1,377 @@
1/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C - USB2.0 Highspeed/OtG device block registers
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_H
16#define __PLAT_S3C64XX_REGS_USB_HSOTG_H __FILE__
17
18#define S3C_HSOTG_REG(x) (x)
19
20#define S3C_GOTGCTL S3C_HSOTG_REG(0x000)
21#define S3C_GOTGCTL_BSESVLD (1 << 19)
22#define S3C_GOTGCTL_ASESVLD (1 << 18)
23#define S3C_GOTGCTL_DBNC_SHORT (1 << 17)
24#define S3C_GOTGCTL_CONID_B (1 << 16)
25#define S3C_GOTGCTL_DEVHNPEN (1 << 11)
26#define S3C_GOTGCTL_HSSETHNPEN (1 << 10)
27#define S3C_GOTGCTL_HNPREQ (1 << 9)
28#define S3C_GOTGCTL_HSTNEGSCS (1 << 8)
29#define S3C_GOTGCTL_SESREQ (1 << 1)
30#define S3C_GOTGCTL_SESREQSCS (1 << 0)
31
32#define S3C_GOTGINT S3C_HSOTG_REG(0x004)
33#define S3C_GOTGINT_DbnceDone (1 << 19)
34#define S3C_GOTGINT_ADevTOUTChg (1 << 18)
35#define S3C_GOTGINT_HstNegDet (1 << 17)
36#define S3C_GOTGINT_HstnegSucStsChng (1 << 9)
37#define S3C_GOTGINT_SesReqSucStsChng (1 << 8)
38#define S3C_GOTGINT_SesEndDet (1 << 2)
39
40#define S3C_GAHBCFG S3C_HSOTG_REG(0x008)
41#define S3C_GAHBCFG_PTxFEmpLvl (1 << 8)
42#define S3C_GAHBCFG_NPTxFEmpLvl (1 << 7)
43#define S3C_GAHBCFG_DMAEn (1 << 5)
44#define S3C_GAHBCFG_HBstLen_MASK (0xf << 1)
45#define S3C_GAHBCFG_HBstLen_SHIFT (1)
46#define S3C_GAHBCFG_HBstLen_Single (0x0 << 1)
47#define S3C_GAHBCFG_HBstLen_Incr (0x1 << 1)
48#define S3C_GAHBCFG_HBstLen_Incr4 (0x3 << 1)
49#define S3C_GAHBCFG_HBstLen_Incr8 (0x5 << 1)
50#define S3C_GAHBCFG_HBstLen_Incr16 (0x7 << 1)
51#define S3C_GAHBCFG_GlblIntrEn (1 << 0)
52
53#define S3C_GUSBCFG S3C_HSOTG_REG(0x00C)
54#define S3C_GUSBCFG_PHYLPClkSel (1 << 15)
55#define S3C_GUSBCFG_HNPCap (1 << 9)
56#define S3C_GUSBCFG_SRPCap (1 << 8)
57#define S3C_GUSBCFG_PHYIf16 (1 << 3)
58#define S3C_GUSBCFG_TOutCal_MASK (0x7 << 0)
59#define S3C_GUSBCFG_TOutCal_SHIFT (0)
60#define S3C_GUSBCFG_TOutCal_LIMIT (0x7)
61#define S3C_GUSBCFG_TOutCal(_x) ((_x) << 0)
62
63#define S3C_GRSTCTL S3C_HSOTG_REG(0x010)
64
65#define S3C_GRSTCTL_AHBIdle (1 << 31)
66#define S3C_GRSTCTL_DMAReq (1 << 30)
67#define S3C_GRSTCTL_TxFNum_MASK (0x1f << 6)
68#define S3C_GRSTCTL_TxFNum_SHIFT (6)
69#define S3C_GRSTCTL_TxFNum_LIMIT (0x1f)
70#define S3C_GRSTCTL_TxFNum(_x) ((_x) << 6)
71#define S3C_GRSTCTL_TxFFlsh (1 << 5)
72#define S3C_GRSTCTL_RxFFlsh (1 << 4)
73#define S3C_GRSTCTL_INTknQFlsh (1 << 3)
74#define S3C_GRSTCTL_FrmCntrRst (1 << 2)
75#define S3C_GRSTCTL_HSftRst (1 << 1)
76#define S3C_GRSTCTL_CSftRst (1 << 0)
77
78#define S3C_GINTSTS S3C_HSOTG_REG(0x014)
79#define S3C_GINTMSK S3C_HSOTG_REG(0x018)
80
81#define S3C_GINTSTS_WkUpInt (1 << 31)
82#define S3C_GINTSTS_SessReqInt (1 << 30)
83#define S3C_GINTSTS_DisconnInt (1 << 29)
84#define S3C_GINTSTS_ConIDStsChng (1 << 28)
85#define S3C_GINTSTS_PTxFEmp (1 << 26)
86#define S3C_GINTSTS_HChInt (1 << 25)
87#define S3C_GINTSTS_PrtInt (1 << 24)
88#define S3C_GINTSTS_FetSusp (1 << 22)
89#define S3C_GINTSTS_incompIP (1 << 21)
90#define S3C_GINTSTS_IncomplSOIN (1 << 20)
91#define S3C_GINTSTS_OEPInt (1 << 19)
92#define S3C_GINTSTS_IEPInt (1 << 18)
93#define S3C_GINTSTS_EPMis (1 << 17)
94#define S3C_GINTSTS_EOPF (1 << 15)
95#define S3C_GINTSTS_ISOutDrop (1 << 14)
96#define S3C_GINTSTS_EnumDone (1 << 13)
97#define S3C_GINTSTS_USBRst (1 << 12)
98#define S3C_GINTSTS_USBSusp (1 << 11)
99#define S3C_GINTSTS_ErlySusp (1 << 10)
100#define S3C_GINTSTS_GOUTNakEff (1 << 7)
101#define S3C_GINTSTS_GINNakEff (1 << 6)
102#define S3C_GINTSTS_NPTxFEmp (1 << 5)
103#define S3C_GINTSTS_RxFLvl (1 << 4)
104#define S3C_GINTSTS_SOF (1 << 3)
105#define S3C_GINTSTS_OTGInt (1 << 2)
106#define S3C_GINTSTS_ModeMis (1 << 1)
107#define S3C_GINTSTS_CurMod_Host (1 << 0)
108
109#define S3C_GRXSTSR S3C_HSOTG_REG(0x01C)
110#define S3C_GRXSTSP S3C_HSOTG_REG(0x020)
111
112#define S3C_GRXSTS_FN_MASK (0x7f << 25)
113#define S3C_GRXSTS_FN_SHIFT (25)
114
115#define S3C_GRXSTS_PktSts_MASK (0xf << 17)
116#define S3C_GRXSTS_PktSts_SHIFT (17)
117#define S3C_GRXSTS_PktSts_GlobalOutNAK (0x1 << 17)
118#define S3C_GRXSTS_PktSts_OutRX (0x2 << 17)
119#define S3C_GRXSTS_PktSts_OutDone (0x3 << 17)
120#define S3C_GRXSTS_PktSts_SetupDone (0x4 << 17)
121#define S3C_GRXSTS_PktSts_SetupRX (0x6 << 17)
122
123#define S3C_GRXSTS_DPID_MASK (0x3 << 15)
124#define S3C_GRXSTS_DPID_SHIFT (15)
125#define S3C_GRXSTS_ByteCnt_MASK (0x7ff << 4)
126#define S3C_GRXSTS_ByteCnt_SHIFT (4)
127#define S3C_GRXSTS_EPNum_MASK (0xf << 0)
128#define S3C_GRXSTS_EPNum_SHIFT (0)
129
130#define S3C_GRXFSIZ S3C_HSOTG_REG(0x024)
131
132#define S3C_GNPTXFSIZ S3C_HSOTG_REG(0x028)
133
134#define S3C_GNPTXFSIZ_NPTxFDep_MASK (0xffff << 16)
135#define S3C_GNPTXFSIZ_NPTxFDep_SHIFT (16)
136#define S3C_GNPTXFSIZ_NPTxFDep_LIMIT (0xffff)
137#define S3C_GNPTXFSIZ_NPTxFDep(_x) ((_x) << 16)
138#define S3C_GNPTXFSIZ_NPTxFStAddr_MASK (0xffff << 0)
139#define S3C_GNPTXFSIZ_NPTxFStAddr_SHIFT (0)
140#define S3C_GNPTXFSIZ_NPTxFStAddr_LIMIT (0xffff)
141#define S3C_GNPTXFSIZ_NPTxFStAddr(_x) ((_x) << 0)
142
143#define S3C_GNPTXSTS S3C_HSOTG_REG(0x02C)
144
145#define S3C_GNPTXSTS_NPtxQTop_MASK (0x7f << 24)
146#define S3C_GNPTXSTS_NPtxQTop_SHIFT (24)
147
148#define S3C_GNPTXSTS_NPTxQSpcAvail_MASK (0xff << 16)
149#define S3C_GNPTXSTS_NPTxQSpcAvail_SHIFT (16)
150#define S3C_GNPTXSTS_NPTxQSpcAvail_GET(_v) (((_v) >> 16) & 0xff)
151
152#define S3C_GNPTXSTS_NPTxFSpcAvail_MASK (0xffff << 0)
153#define S3C_GNPTXSTS_NPTxFSpcAvail_SHIFT (0)
154#define S3C_GNPTXSTS_NPTxFSpcAvail_GET(_v) (((_v) >> 0) & 0xffff)
155
156
157#define S3C_HPTXFSIZ S3C_HSOTG_REG(0x100)
158
159#define S3C_DPTXFSIZn(_a) S3C_HSOTG_REG(0x104 + (((_a) - 1) * 4))
160
161#define S3C_DPTXFSIZn_DPTxFSize_MASK (0xffff << 16)
162#define S3C_DPTXFSIZn_DPTxFSize_SHIFT (16)
163#define S3C_DPTXFSIZn_DPTxFSize_GET(_v) (((_v) >> 16) & 0xffff)
164#define S3C_DPTXFSIZn_DPTxFSize_LIMIT (0xffff)
165#define S3C_DPTXFSIZn_DPTxFSize(_x) ((_x) << 16)
166
167#define S3C_DPTXFSIZn_DPTxFStAddr_MASK (0xffff << 0)
168#define S3C_DPTXFSIZn_DPTxFStAddr_SHIFT (0)
169
170/* Device mode registers */
171#define S3C_DCFG S3C_HSOTG_REG(0x800)
172
173#define S3C_DCFG_EPMisCnt_MASK (0x1f << 18)
174#define S3C_DCFG_EPMisCnt_SHIFT (18)
175#define S3C_DCFG_EPMisCnt_LIMIT (0x1f)
176#define S3C_DCFG_EPMisCnt(_x) ((_x) << 18)
177
178#define S3C_DCFG_PerFrInt_MASK (0x3 << 11)
179#define S3C_DCFG_PerFrInt_SHIFT (11)
180#define S3C_DCFG_PerFrInt_LIMIT (0x3)
181#define S3C_DCFG_PerFrInt(_x) ((_x) << 11)
182
183#define S3C_DCFG_DevAddr_MASK (0x7f << 4)
184#define S3C_DCFG_DevAddr_SHIFT (4)
185#define S3C_DCFG_DevAddr_LIMIT (0x7f)
186#define S3C_DCFG_DevAddr(_x) ((_x) << 4)
187
188#define S3C_DCFG_NZStsOUTHShk (1 << 2)
189
190#define S3C_DCFG_DevSpd_MASK (0x3 << 0)
191#define S3C_DCFG_DevSpd_SHIFT (0)
192#define S3C_DCFG_DevSpd_HS (0x0 << 0)
193#define S3C_DCFG_DevSpd_FS (0x1 << 0)
194#define S3C_DCFG_DevSpd_LS (0x2 << 0)
195#define S3C_DCFG_DevSpd_FS48 (0x3 << 0)
196
197#define S3C_DCTL S3C_HSOTG_REG(0x804)
198
199#define S3C_DCTL_PWROnPrgDone (1 << 11)
200#define S3C_DCTL_CGOUTNak (1 << 10)
201#define S3C_DCTL_SGOUTNak (1 << 9)
202#define S3C_DCTL_CGNPInNAK (1 << 8)
203#define S3C_DCTL_SGNPInNAK (1 << 7)
204#define S3C_DCTL_TstCtl_MASK (0x7 << 4)
205#define S3C_DCTL_TstCtl_SHIFT (4)
206#define S3C_DCTL_GOUTNakSts (1 << 3)
207#define S3C_DCTL_GNPINNakSts (1 << 2)
208#define S3C_DCTL_SftDiscon (1 << 1)
209#define S3C_DCTL_RmtWkUpSig (1 << 0)
210
211#define S3C_DSTS S3C_HSOTG_REG(0x808)
212
213#define S3C_DSTS_SOFFN_MASK (0x3fff << 8)
214#define S3C_DSTS_SOFFN_SHIFT (8)
215#define S3C_DSTS_SOFFN_LIMIT (0x3fff)
216#define S3C_DSTS_SOFFN(_x) ((_x) << 8)
217#define S3C_DSTS_ErraticErr (1 << 3)
218#define S3C_DSTS_EnumSpd_MASK (0x3 << 1)
219#define S3C_DSTS_EnumSpd_SHIFT (1)
220#define S3C_DSTS_EnumSpd_HS (0x0 << 1)
221#define S3C_DSTS_EnumSpd_FS (0x1 << 1)
222#define S3C_DSTS_EnumSpd_LS (0x2 << 1)
223#define S3C_DSTS_EnumSpd_FS48 (0x3 << 1)
224
225#define S3C_DSTS_SuspSts (1 << 0)
226
227#define S3C_DIEPMSK S3C_HSOTG_REG(0x810)
228
229#define S3C_DIEPMSK_INEPNakEffMsk (1 << 6)
230#define S3C_DIEPMSK_INTknEPMisMsk (1 << 5)
231#define S3C_DIEPMSK_INTknTXFEmpMsk (1 << 4)
232#define S3C_DIEPMSK_TimeOUTMsk (1 << 3)
233#define S3C_DIEPMSK_AHBErrMsk (1 << 2)
234#define S3C_DIEPMSK_EPDisbldMsk (1 << 1)
235#define S3C_DIEPMSK_XferComplMsk (1 << 0)
236
237#define S3C_DOEPMSK S3C_HSOTG_REG(0x814)
238
239#define S3C_DOEPMSK_Back2BackSetup (1 << 6)
240#define S3C_DOEPMSK_OUTTknEPdisMsk (1 << 4)
241#define S3C_DOEPMSK_SetupMsk (1 << 3)
242#define S3C_DOEPMSK_AHBErrMsk (1 << 2)
243#define S3C_DOEPMSK_EPDisbldMsk (1 << 1)
244#define S3C_DOEPMSK_XferComplMsk (1 << 0)
245
246#define S3C_DAINT S3C_HSOTG_REG(0x818)
247#define S3C_DAINTMSK S3C_HSOTG_REG(0x81C)
248
249#define S3C_DAINT_OutEP_SHIFT (16)
250#define S3C_DAINT_OutEP(x) (1 << ((x) + 16))
251#define S3C_DAINT_InEP(x) (1 << (x))
252
253#define S3C_DTKNQR1 S3C_HSOTG_REG(0x820)
254#define S3C_DTKNQR2 S3C_HSOTG_REG(0x824)
255#define S3C_DTKNQR3 S3C_HSOTG_REG(0x830)
256#define S3C_DTKNQR4 S3C_HSOTG_REG(0x834)
257
258#define S3C_DVBUSDIS S3C_HSOTG_REG(0x828)
259#define S3C_DVBUSPULSE S3C_HSOTG_REG(0x82C)
260
261#define S3C_DIEPCTL0 S3C_HSOTG_REG(0x900)
262#define S3C_DOEPCTL0 S3C_HSOTG_REG(0xB00)
263#define S3C_DIEPCTL(_a) S3C_HSOTG_REG(0x900 + ((_a) * 0x20))
264#define S3C_DOEPCTL(_a) S3C_HSOTG_REG(0xB00 + ((_a) * 0x20))
265
266/* EP0 specialness:
267 * bits[29..28] - reserved (no SetD0PID, SetD1PID)
268 * bits[25..22] - should always be zero, this isn't a periodic endpoint
269 * bits[10..0] - MPS setting differenct for EP0
270*/
271#define S3C_D0EPCTL_MPS_MASK (0x3 << 0)
272#define S3C_D0EPCTL_MPS_SHIFT (0)
273#define S3C_D0EPCTL_MPS_64 (0x0 << 0)
274#define S3C_D0EPCTL_MPS_32 (0x1 << 0)
275#define S3C_D0EPCTL_MPS_16 (0x2 << 0)
276#define S3C_D0EPCTL_MPS_8 (0x3 << 0)
277
278#define S3C_DxEPCTL_EPEna (1 << 31)
279#define S3C_DxEPCTL_EPDis (1 << 30)
280#define S3C_DxEPCTL_SetD1PID (1 << 29)
281#define S3C_DxEPCTL_SetOddFr (1 << 29)
282#define S3C_DxEPCTL_SetD0PID (1 << 28)
283#define S3C_DxEPCTL_SetEvenFr (1 << 28)
284#define S3C_DxEPCTL_SNAK (1 << 27)
285#define S3C_DxEPCTL_CNAK (1 << 26)
286#define S3C_DxEPCTL_TxFNum_MASK (0xf << 22)
287#define S3C_DxEPCTL_TxFNum_SHIFT (22)
288#define S3C_DxEPCTL_TxFNum_LIMIT (0xf)
289#define S3C_DxEPCTL_TxFNum(_x) ((_x) << 22)
290
291#define S3C_DxEPCTL_Stall (1 << 21)
292#define S3C_DxEPCTL_Snp (1 << 20)
293#define S3C_DxEPCTL_EPType_MASK (0x3 << 18)
294#define S3C_DxEPCTL_EPType_SHIFT (18)
295#define S3C_DxEPCTL_EPType_Control (0x0 << 18)
296#define S3C_DxEPCTL_EPType_Iso (0x1 << 18)
297#define S3C_DxEPCTL_EPType_Bulk (0x2 << 18)
298#define S3C_DxEPCTL_EPType_Intterupt (0x3 << 18)
299
300#define S3C_DxEPCTL_NAKsts (1 << 17)
301#define S3C_DxEPCTL_DPID (1 << 16)
302#define S3C_DxEPCTL_EOFrNum (1 << 16)
303#define S3C_DxEPCTL_USBActEp (1 << 15)
304#define S3C_DxEPCTL_NextEp_MASK (0xf << 11)
305#define S3C_DxEPCTL_NextEp_SHIFT (11)
306#define S3C_DxEPCTL_NextEp_LIMIT (0xf)
307#define S3C_DxEPCTL_NextEp(_x) ((_x) << 11)
308
309#define S3C_DxEPCTL_MPS_MASK (0x7ff << 0)
310#define S3C_DxEPCTL_MPS_SHIFT (0)
311#define S3C_DxEPCTL_MPS_LIMIT (0x7ff)
312#define S3C_DxEPCTL_MPS(_x) ((_x) << 0)
313
314#define S3C_DIEPINT(_a) S3C_HSOTG_REG(0x908 + ((_a) * 0x20))
315#define S3C_DOEPINT(_a) S3C_HSOTG_REG(0xB08 + ((_a) * 0x20))
316
317#define S3C_DxEPINT_INEPNakEff (1 << 6)
318#define S3C_DxEPINT_Back2BackSetup (1 << 6)
319#define S3C_DxEPINT_INTknEPMis (1 << 5)
320#define S3C_DxEPINT_INTknTXFEmp (1 << 4)
321#define S3C_DxEPINT_OUTTknEPdis (1 << 4)
322#define S3C_DxEPINT_Timeout (1 << 3)
323#define S3C_DxEPINT_Setup (1 << 3)
324#define S3C_DxEPINT_AHBErr (1 << 2)
325#define S3C_DxEPINT_EPDisbld (1 << 1)
326#define S3C_DxEPINT_XferCompl (1 << 0)
327
328#define S3C_DIEPTSIZ0 S3C_HSOTG_REG(0x910)
329
330#define S3C_DIEPTSIZ0_PktCnt_MASK (0x3 << 19)
331#define S3C_DIEPTSIZ0_PktCnt_SHIFT (19)
332#define S3C_DIEPTSIZ0_PktCnt_LIMIT (0x3)
333#define S3C_DIEPTSIZ0_PktCnt(_x) ((_x) << 19)
334
335#define S3C_DIEPTSIZ0_XferSize_MASK (0x7f << 0)
336#define S3C_DIEPTSIZ0_XferSize_SHIFT (0)
337#define S3C_DIEPTSIZ0_XferSize_LIMIT (0x7f)
338#define S3C_DIEPTSIZ0_XferSize(_x) ((_x) << 0)
339
340
341#define DOEPTSIZ0 S3C_HSOTG_REG(0xB10)
342#define S3C_DOEPTSIZ0_SUPCnt_MASK (0x3 << 29)
343#define S3C_DOEPTSIZ0_SUPCnt_SHIFT (29)
344#define S3C_DOEPTSIZ0_SUPCnt_LIMIT (0x3)
345#define S3C_DOEPTSIZ0_SUPCnt(_x) ((_x) << 29)
346
347#define S3C_DOEPTSIZ0_PktCnt (1 << 19)
348#define S3C_DOEPTSIZ0_XferSize_MASK (0x7f << 0)
349#define S3C_DOEPTSIZ0_XferSize_SHIFT (0)
350
351#define S3C_DIEPTSIZ(_a) S3C_HSOTG_REG(0x910 + ((_a) * 0x20))
352#define S3C_DOEPTSIZ(_a) S3C_HSOTG_REG(0xB10 + ((_a) * 0x20))
353
354#define S3C_DxEPTSIZ_MC_MASK (0x3 << 29)
355#define S3C_DxEPTSIZ_MC_SHIFT (29)
356#define S3C_DxEPTSIZ_MC_LIMIT (0x3)
357#define S3C_DxEPTSIZ_MC(_x) ((_x) << 29)
358
359#define S3C_DxEPTSIZ_PktCnt_MASK (0x3ff << 19)
360#define S3C_DxEPTSIZ_PktCnt_SHIFT (19)
361#define S3C_DxEPTSIZ_PktCnt_GET(_v) (((_v) >> 19) & 0x3ff)
362#define S3C_DxEPTSIZ_PktCnt_LIMIT (0x3ff)
363#define S3C_DxEPTSIZ_PktCnt(_x) ((_x) << 19)
364
365#define S3C_DxEPTSIZ_XferSize_MASK (0x7ffff << 0)
366#define S3C_DxEPTSIZ_XferSize_SHIFT (0)
367#define S3C_DxEPTSIZ_XferSize_GET(_v) (((_v) >> 0) & 0x7ffff)
368#define S3C_DxEPTSIZ_XferSize_LIMIT (0x7ffff)
369#define S3C_DxEPTSIZ_XferSize(_x) ((_x) << 0)
370
371
372#define S3C_DIEPDMA(_a) S3C_HSOTG_REG(0x914 + ((_a) * 0x20))
373#define S3C_DOEPDMA(_a) S3C_HSOTG_REG(0xB14 + ((_a) * 0x20))
374
375#define S3C_EPFIFO(_a) S3C_HSOTG_REG(0x1000 + ((_a) * 0x1000))
376
377#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-watchdog.h b/arch/arm/plat-samsung/include/plat/regs-watchdog.h
new file mode 100644
index 000000000000..4938492470f7
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-watchdog.h
@@ -0,0 +1,41 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Watchdog timer control
11*/
12
13
14#ifndef __ASM_ARCH_REGS_WATCHDOG_H
15#define __ASM_ARCH_REGS_WATCHDOG_H
16
17#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
18
19#define S3C2410_WTCON S3C_WDOGREG(0x00)
20#define S3C2410_WTDAT S3C_WDOGREG(0x04)
21#define S3C2410_WTCNT S3C_WDOGREG(0x08)
22
23/* the watchdog can either generate a reset pulse, or an
24 * interrupt.
25 */
26
27#define S3C2410_WTCON_RSTEN (0x01)
28#define S3C2410_WTCON_INTEN (1<<2)
29#define S3C2410_WTCON_ENABLE (1<<5)
30
31#define S3C2410_WTCON_DIV16 (0<<3)
32#define S3C2410_WTCON_DIV32 (1<<3)
33#define S3C2410_WTCON_DIV64 (2<<3)
34#define S3C2410_WTCON_DIV128 (3<<3)
35
36#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
37#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
38
39#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
40
41
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
new file mode 100644
index 000000000000..53198673b6bd
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -0,0 +1,226 @@
1/* linux/arch/arm/plat-s3c/include/plat/sdhci.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C Platform - SDHCI (HSMMC) platform data definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C_SDHCI_H
16#define __PLAT_S3C_SDHCI_H __FILE__
17
18struct platform_device;
19struct mmc_host;
20struct mmc_card;
21struct mmc_ios;
22
23/**
24 * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
25 * @max_width: The maximum number of data bits supported.
26 * @host_caps: Standard MMC host capabilities bit field.
27 * @cfg_gpio: Configure the GPIO for a specific card bit-width
28 * @cfg_card: Configure the interface for a specific card and speed. This
29 * is necessary the controllers and/or GPIO blocks require the
30 * changing of driver-strength and other controls dependant on
31 * the card and speed of operation.
32 *
33 * Initialisation data specific to either the machine or the platform
34 * for the device driver to use or call-back when configuring gpio or
35 * card speed information.
36*/
37struct s3c_sdhci_platdata {
38 unsigned int max_width;
39 unsigned int host_caps;
40
41 char **clocks; /* set of clock sources */
42
43 void (*cfg_gpio)(struct platform_device *dev, int width);
44 void (*cfg_card)(struct platform_device *dev,
45 void __iomem *regbase,
46 struct mmc_ios *ios,
47 struct mmc_card *card);
48};
49
50/**
51 * s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device.
52 * @pd: Platform data to register to device.
53 *
54 * Register the given platform data for use withe S3C SDHCI device.
55 * The call will copy the platform data, so the board definitions can
56 * make the structure itself __initdata.
57 */
58extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd);
59extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd);
60extern void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd);
61
62/* Default platform data, exported so that per-cpu initialisation can
63 * set the correct one when there are more than one cpu type selected.
64*/
65
66extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata;
67extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
68extern struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata;
69
70/* Helper function availablity */
71
72extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
73extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
74extern void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
75extern void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
76extern void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
77extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
78
79/* S3C6400 SDHCI setup */
80
81#ifdef CONFIG_S3C6400_SETUP_SDHCI
82extern char *s3c6400_hsmmc_clksrcs[4];
83
84#ifdef CONFIG_S3C_DEV_HSMMC
85extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
86 void __iomem *r,
87 struct mmc_ios *ios,
88 struct mmc_card *card);
89
90static inline void s3c6400_default_sdhci0(void)
91{
92 s3c_hsmmc0_def_platdata.clocks = s3c6400_hsmmc_clksrcs;
93 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
94 s3c_hsmmc0_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
95}
96
97#else
98static inline void s3c6400_default_sdhci0(void) { }
99#endif /* CONFIG_S3C_DEV_HSMMC */
100
101#ifdef CONFIG_S3C_DEV_HSMMC1
102static inline void s3c6400_default_sdhci1(void)
103{
104 s3c_hsmmc1_def_platdata.clocks = s3c6400_hsmmc_clksrcs;
105 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
106 s3c_hsmmc1_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
107}
108#else
109static inline void s3c6400_default_sdhci1(void) { }
110#endif /* CONFIG_S3C_DEV_HSMMC1 */
111
112#ifdef CONFIG_S3C_DEV_HSMMC2
113static inline void s3c6400_default_sdhci2(void)
114{
115 s3c_hsmmc2_def_platdata.clocks = s3c6400_hsmmc_clksrcs;
116 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
117 s3c_hsmmc2_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
118}
119#else
120static inline void s3c6400_default_sdhci2(void) { }
121#endif /* CONFIG_S3C_DEV_HSMMC2 */
122
123#else
124static inline void s3c6400_default_sdhci0(void) { }
125static inline void s3c6400_default_sdhci1(void) { }
126#endif /* CONFIG_S3C6400_SETUP_SDHCI */
127
128/* S3C6410 SDHCI setup */
129
130#ifdef CONFIG_S3C6410_SETUP_SDHCI
131extern char *s3c6410_hsmmc_clksrcs[4];
132
133extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
134 void __iomem *r,
135 struct mmc_ios *ios,
136 struct mmc_card *card);
137
138#ifdef CONFIG_S3C_DEV_HSMMC
139static inline void s3c6410_default_sdhci0(void)
140{
141 s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
142 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
143 s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
144}
145#else
146static inline void s3c6410_default_sdhci0(void) { }
147#endif /* CONFIG_S3C_DEV_HSMMC */
148
149#ifdef CONFIG_S3C_DEV_HSMMC1
150static inline void s3c6410_default_sdhci1(void)
151{
152 s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
153 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
154 s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
155}
156#else
157static inline void s3c6410_default_sdhci1(void) { }
158#endif /* CONFIG_S3C_DEV_HSMMC1 */
159
160#ifdef CONFIG_S3C_DEV_HSMMC2
161static inline void s3c6410_default_sdhci2(void)
162{
163 s3c_hsmmc2_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
164 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
165 s3c_hsmmc2_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
166}
167#else
168static inline void s3c6410_default_sdhci2(void) { }
169#endif /* CONFIG_S3C_DEV_HSMMC2 */
170
171#else
172static inline void s3c6410_default_sdhci0(void) { }
173static inline void s3c6410_default_sdhci1(void) { }
174#endif /* CONFIG_S3C6410_SETUP_SDHCI */
175
176/* S5PC100 SDHCI setup */
177
178#ifdef CONFIG_S5PC100_SETUP_SDHCI
179extern char *s5pc100_hsmmc_clksrcs[4];
180
181extern void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev,
182 void __iomem *r,
183 struct mmc_ios *ios,
184 struct mmc_card *card);
185
186#ifdef CONFIG_S3C_DEV_HSMMC
187static inline void s5pc100_default_sdhci0(void)
188{
189 s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
190 s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio;
191 s3c_hsmmc0_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
192}
193#else
194static inline void s5pc100_default_sdhci0(void) { }
195#endif /* CONFIG_S3C_DEV_HSMMC */
196
197#ifdef CONFIG_S3C_DEV_HSMMC1
198static inline void s5pc100_default_sdhci1(void)
199{
200 s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
201 s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio;
202 s3c_hsmmc1_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
203}
204#else
205static inline void s5pc100_default_sdhci1(void) { }
206#endif /* CONFIG_S3C_DEV_HSMMC1 */
207
208#ifdef CONFIG_S3C_DEV_HSMMC2
209static inline void s5pc100_default_sdhci2(void)
210{
211 s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
212 s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio;
213 s3c_hsmmc2_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
214}
215#else
216static inline void s5pc100_default_sdhci2(void) { }
217#endif /* CONFIG_S3C_DEV_HSMMC1 */
218
219
220#else
221static inline void s5pc100_default_sdhci0(void) { }
222static inline void s5pc100_default_sdhci1(void) { }
223static inline void s5pc100_default_sdhci2(void) { }
224#endif /* CONFIG_S5PC100_SETUP_SDHCI */
225
226#endif /* __PLAT_S3C_SDHCI_H */
diff --git a/arch/arm/plat-samsung/include/plat/udc-hs.h b/arch/arm/plat-samsung/include/plat/udc-hs.h
new file mode 100644
index 000000000000..dd04db043109
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/udc-hs.h
@@ -0,0 +1,29 @@
1/* arch/arm/plat-s3c/include/plat/udc-hs.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C USB2.0 High-speed / OtG platform information
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15enum s3c_hostg_dmamode {
16 S3C_HSOTG_DMA_NONE, /* do not use DMA at-all */
17 S3C_HSOTG_DMA_ONLY, /* always use DMA */
18 S3C_HSOTG_DMA_DRV, /* DMA is chosen by driver */
19};
20
21/**
22 * struct s3c_hsotg_plat - platform data for high-speed otg/udc
23 * @dma: Whether to use DMA or not.
24 * @is_osc: The clock source is an oscillator, not a crystal
25 */
26struct s3c_hsotg_plat {
27 enum s3c_hostg_dmamode dma;
28 unsigned int is_osc : 1;
29};
diff --git a/arch/arm/plat-samsung/include/plat/watchdog-reset.h b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
new file mode 100644
index 000000000000..54b762acb5a0
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
@@ -0,0 +1,49 @@
1/* arch/arm/plat-s3c/include/plat/watchdog-reset.h
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - System define for arch_reset() function
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <plat/regs-watchdog.h>
14#include <mach/map.h>
15
16#include <linux/clk.h>
17#include <linux/err.h>
18#include <linux/io.h>
19
20static inline void arch_wdt_reset(void)
21{
22 struct clk *wdtclk;
23
24 printk("arch_reset: attempting watchdog reset\n");
25
26 __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */
27
28 wdtclk = clk_get(NULL, "watchdog");
29 if (!IS_ERR(wdtclk)) {
30 clk_enable(wdtclk);
31 } else
32 printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
33
34 /* put initial values into count and data */
35 __raw_writel(0x80, S3C2410_WTCNT);
36 __raw_writel(0x80, S3C2410_WTDAT);
37
38 /* set the watchdog to go and reset... */
39 __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
40 S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
41
42 /* wait for reset to assert... */
43 mdelay(500);
44
45 printk(KERN_ERR "Watchdog reset failed to assert reset\n");
46
47 /* delay to allow the serial port to show the message */
48 mdelay(50);
49}
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