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authorLinus Torvalds <torvalds@linux-foundation.org>2012-10-11 21:21:02 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-10-11 21:21:02 -0400
commit5f76945a9c978b8b8bf8eb7fe3b17b9981240a97 (patch)
treedf61aca168df657bc71ce8b578bcb0c81b0622ee /arch/arm/plat-samsung
parent940e3a8dd6683a3787faf769b3df7a06f1c2fa31 (diff)
parentcd9d6f10d07f26dd8a70e519c22b6b4f8a9e3e7a (diff)
Merge tag 'fbdev-updates-for-3.7' of git://github.com/schandinat/linux-2.6
Pull fbdev updates from Florian Tobias Schandinat: "This includes: - large updates for OMAP - basic OMAP5 DSS support for DPI and DSI outputs - large cleanups and restructuring - some update to Exynos and da8xx-fb - removal of the pnx4008 driver (arch removed) - various other small patches" Fix up some trivial conflicts (mostly just include line changes, but also some due to the renaming of the deferred work functions by Tejun). * tag 'fbdev-updates-for-3.7' of git://github.com/schandinat/linux-2.6: (193 commits) gbefb: fix compile error video: mark nuc900fb_map_video_memory as __devinit video/mx3fb: set .owner to prevent module unloading while being used video: exynos_dp: use clk_prepare_enable and clk_disable_unprepare drivers/video/exynos/exynos_mipi_dsi.c: fix error return code drivers/video/savage/savagefb_driver.c: fix error return code video: s3c-fb: use clk_prepare_enable and clk_disable_unprepare da8xx-fb: save and restore LCDC context across suspend/resume cycle da8xx-fb: add pm_runtime support video/udlfb: fix line counting in fb_write OMAPDSS: add missing include for string.h OMAPDSS: DISPC: Configure color conversion coefficients for writeback OMAPDSS: DISPC: Add manager like functions for writeback OMAPDSS: DISPC: Configure writeback FIFOs OMAPDSS: DISPC: Configure writeback specific parameters in dispc_wb_setup() OMAPDSS: DISPC: Configure overlay-like parameters in dispc_wb_setup OMAPDSS: DISPC: Add function to set channel in for writeback OMAPDSS: DISPC: Don't set chroma resampling bit for writeback OMAPDSS: DISPC: Downscale chroma if plane is writeback OMAPDSS: DISPC: Configure input and output sizes for writeback ...
Diffstat (limited to 'arch/arm/plat-samsung')
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-fb-v4.h159
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-fb.h403
2 files changed, 0 insertions, 562 deletions
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
deleted file mode 100644
index 4c3647f80057..000000000000
--- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
+++ /dev/null
@@ -1,159 +0,0 @@
1/* arch/arm/plat-samsung/include/plat/regs-fb-v4.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - new-style framebuffer register definitions
9 *
10 * This is the register set for the new style framebuffer interface
11 * found from the S3C2443 onwards and specifically the S3C64XX series
12 * S3C6400 and S3C6410.
13 *
14 * The file contains the cpu specific items which change between whichever
15 * architecture is selected. See <plat/regs-fb.h> for the core definitions
16 * that are the same.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21*/
22
23/* include the core definitions here, in case we really do need to
24 * override them at a later date.
25*/
26
27#include <plat/regs-fb.h>
28
29#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
30#define VIDCON1_FSTATUS_EVEN (1 << 15)
31
32/* Video timing controls */
33#define VIDTCON0 (0x10)
34#define VIDTCON1 (0x14)
35#define VIDTCON2 (0x18)
36
37/* Window position controls */
38
39#define WINCON(_win) (0x20 + ((_win) * 4))
40
41/* OSD1 and OSD4 do not have register D */
42
43#define VIDOSD_BASE (0x40)
44
45#define VIDINTCON0 (0x130)
46
47/* WINCONx */
48
49#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
50#define WINCONx_CSCWIDTH_SHIFT (26)
51#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
52#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
53
54#define WINCONx_ENLOCAL (1 << 22)
55#define WINCONx_BUFSTATUS (1 << 21)
56#define WINCONx_BUFSEL (1 << 20)
57#define WINCONx_BUFAUTOEN (1 << 19)
58#define WINCONx_YCbCr (1 << 13)
59
60#define WINCON1_LOCALSEL_CAMIF (1 << 23)
61
62#define WINCON2_LOCALSEL_CAMIF (1 << 23)
63#define WINCON2_BLD_PIX (1 << 6)
64
65#define WINCON2_ALPHA_SEL (1 << 1)
66#define WINCON2_BPPMODE_MASK (0xf << 2)
67#define WINCON2_BPPMODE_SHIFT (2)
68#define WINCON2_BPPMODE_1BPP (0x0 << 2)
69#define WINCON2_BPPMODE_2BPP (0x1 << 2)
70#define WINCON2_BPPMODE_4BPP (0x2 << 2)
71#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
72#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
73#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
74#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
75#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
76#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
77#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
78#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
79#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
80#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
81#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
82
83#define WINCON3_BLD_PIX (1 << 6)
84
85#define WINCON3_ALPHA_SEL (1 << 1)
86#define WINCON3_BPPMODE_MASK (0xf << 2)
87#define WINCON3_BPPMODE_SHIFT (2)
88#define WINCON3_BPPMODE_1BPP (0x0 << 2)
89#define WINCON3_BPPMODE_2BPP (0x1 << 2)
90#define WINCON3_BPPMODE_4BPP (0x2 << 2)
91#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
92#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
93#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
94#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
95#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
96#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
97#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
98#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
99#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
100#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
101
102#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
103#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
104#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
105
106#define DITHMODE (0x170)
107#define WINxMAP(_win) (0x180 + ((_win) * 4))
108
109
110#define DITHMODE_R_POS_MASK (0x3 << 5)
111#define DITHMODE_R_POS_SHIFT (5)
112#define DITHMODE_R_POS_8BIT (0x0 << 5)
113#define DITHMODE_R_POS_6BIT (0x1 << 5)
114#define DITHMODE_R_POS_5BIT (0x2 << 5)
115
116#define DITHMODE_G_POS_MASK (0x3 << 3)
117#define DITHMODE_G_POS_SHIFT (3)
118#define DITHMODE_G_POS_8BIT (0x0 << 3)
119#define DITHMODE_G_POS_6BIT (0x1 << 3)
120#define DITHMODE_G_POS_5BIT (0x2 << 3)
121
122#define DITHMODE_B_POS_MASK (0x3 << 1)
123#define DITHMODE_B_POS_SHIFT (1)
124#define DITHMODE_B_POS_8BIT (0x0 << 1)
125#define DITHMODE_B_POS_6BIT (0x1 << 1)
126#define DITHMODE_B_POS_5BIT (0x2 << 1)
127
128#define DITHMODE_DITH_EN (1 << 0)
129
130#define WPALCON (0x1A0)
131
132/* Palette control */
133/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
134 * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
135#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
136#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
137#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
138
139
140/* Notes on per-window bpp settings
141 *
142 * Value Win0 Win1 Win2 Win3 Win 4
143 * 0000 1(P) 1(P) 1(P) 1(P) 1(P)
144 * 0001 2(P) 2(P) 2(P) 2(P) 2(P)
145 * 0010 4(P) 4(P) 4(P) 4(P) -none-
146 * 0011 8(P) 8(P) -none- -none- -none-
147 * 0100 -none- 8(A232) 8(A232) -none- -none-
148 * 0101 16(565) 16(565) 16(565) 16(565) 16(565)
149 * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
150 * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
151 * 1000 18(666) 18(666) 18(666) 18(666) 18(666)
152 * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
153 * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
154 * 1011 24(888) 24(888) 24(888) 24(888) 24(888)
155 * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
156 * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
157 * 1110 -none- -none- -none- -none- -none-
158 * 1111 -none- -none- -none- -none- -none-
159*/
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
deleted file mode 100644
index 9a78012d6f43..000000000000
--- a/arch/arm/plat-samsung/include/plat/regs-fb.h
+++ /dev/null
@@ -1,403 +0,0 @@
1/* arch/arm/plat-samsung/include/plat/regs-fb.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C Platform - new-style framebuffer register definitions
9 *
10 * This is the register set for the new style framebuffer interface
11 * found from the S3C2443 onwards into the S3C2416, S3C2450 and the
12 * S3C64XX series such as the S3C6400 and S3C6410.
13 *
14 * The file does not contain the cpu specific items which are based on
15 * whichever architecture is selected, it only contains the core of the
16 * register set. See <mach/regs-fb.h> to get the specifics.
17 *
18 * Note, we changed to using regs-fb.h as it avoids any clashes with
19 * the original regs-lcd.h so out of the way of regs-lcd.h as well as
20 * indicating the newer block is much more than just an LCD interface.
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
25*/
26
27/* Please do not include this file directly, use <mach/regs-fb.h> to
28 * ensure all the localised SoC support is included as necessary.
29*/
30
31/* VIDCON0 */
32
33#define VIDCON0 (0x00)
34#define VIDCON0_INTERLACE (1 << 29)
35#define VIDCON0_VIDOUT_MASK (0x3 << 26)
36#define VIDCON0_VIDOUT_SHIFT (26)
37#define VIDCON0_VIDOUT_RGB (0x0 << 26)
38#define VIDCON0_VIDOUT_TV (0x1 << 26)
39#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
40#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
41
42#define VIDCON0_L1_DATA_MASK (0x7 << 23)
43#define VIDCON0_L1_DATA_SHIFT (23)
44#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
45#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
46#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
47#define VIDCON0_L1_DATA_24BPP (0x3 << 23)
48#define VIDCON0_L1_DATA_18BPP (0x4 << 23)
49#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
50
51#define VIDCON0_L0_DATA_MASK (0x7 << 20)
52#define VIDCON0_L0_DATA_SHIFT (20)
53#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
54#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
55#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
56#define VIDCON0_L0_DATA_24BPP (0x3 << 20)
57#define VIDCON0_L0_DATA_18BPP (0x4 << 20)
58#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
59
60#define VIDCON0_PNRMODE_MASK (0x3 << 17)
61#define VIDCON0_PNRMODE_SHIFT (17)
62#define VIDCON0_PNRMODE_RGB (0x0 << 17)
63#define VIDCON0_PNRMODE_BGR (0x1 << 17)
64#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
65#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
66
67#define VIDCON0_CLKVALUP (1 << 16)
68#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
69#define VIDCON0_CLKVAL_F_SHIFT (6)
70#define VIDCON0_CLKVAL_F_LIMIT (0xff)
71#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
72#define VIDCON0_VLCKFREE (1 << 5)
73#define VIDCON0_CLKDIR (1 << 4)
74
75#define VIDCON0_CLKSEL_MASK (0x3 << 2)
76#define VIDCON0_CLKSEL_SHIFT (2)
77#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
78#define VIDCON0_CLKSEL_LCD (0x1 << 2)
79#define VIDCON0_CLKSEL_27M (0x3 << 2)
80
81#define VIDCON0_ENVID (1 << 1)
82#define VIDCON0_ENVID_F (1 << 0)
83
84#define VIDCON1 (0x04)
85#define VIDCON1_LINECNT_MASK (0x7ff << 16)
86#define VIDCON1_LINECNT_SHIFT (16)
87#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
88#define VIDCON1_VSTATUS_MASK (0x3 << 13)
89#define VIDCON1_VSTATUS_SHIFT (13)
90#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
91#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
92#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
93#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
94#define VIDCON1_VCLK_MASK (0x3 << 9)
95#define VIDCON1_VCLK_HOLD (0x0 << 9)
96#define VIDCON1_VCLK_RUN (0x1 << 9)
97
98#define VIDCON1_INV_VCLK (1 << 7)
99#define VIDCON1_INV_HSYNC (1 << 6)
100#define VIDCON1_INV_VSYNC (1 << 5)
101#define VIDCON1_INV_VDEN (1 << 4)
102
103/* VIDCON2 */
104
105#define VIDCON2 (0x08)
106#define VIDCON2_EN601 (1 << 23)
107#define VIDCON2_TVFMTSEL_SW (1 << 14)
108
109#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
110#define VIDCON2_TVFMTSEL1_SHIFT (12)
111#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
112#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
113#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
114
115#define VIDCON2_ORGYCbCr (1 << 8)
116#define VIDCON2_YUVORDCrCb (1 << 7)
117
118/* PRTCON (S3C6410, S5PC100)
119 * Might not be present in the S3C6410 documentation,
120 * but tests prove it's there almost for sure; shouldn't hurt in any case.
121 */
122#define PRTCON (0x0c)
123#define PRTCON_PROTECT (1 << 11)
124
125/* VIDTCON0 */
126
127#define VIDTCON0_VBPDE_MASK (0xff << 24)
128#define VIDTCON0_VBPDE_SHIFT (24)
129#define VIDTCON0_VBPDE_LIMIT (0xff)
130#define VIDTCON0_VBPDE(_x) ((_x) << 24)
131
132#define VIDTCON0_VBPD_MASK (0xff << 16)
133#define VIDTCON0_VBPD_SHIFT (16)
134#define VIDTCON0_VBPD_LIMIT (0xff)
135#define VIDTCON0_VBPD(_x) ((_x) << 16)
136
137#define VIDTCON0_VFPD_MASK (0xff << 8)
138#define VIDTCON0_VFPD_SHIFT (8)
139#define VIDTCON0_VFPD_LIMIT (0xff)
140#define VIDTCON0_VFPD(_x) ((_x) << 8)
141
142#define VIDTCON0_VSPW_MASK (0xff << 0)
143#define VIDTCON0_VSPW_SHIFT (0)
144#define VIDTCON0_VSPW_LIMIT (0xff)
145#define VIDTCON0_VSPW(_x) ((_x) << 0)
146
147/* VIDTCON1 */
148
149#define VIDTCON1_VFPDE_MASK (0xff << 24)
150#define VIDTCON1_VFPDE_SHIFT (24)
151#define VIDTCON1_VFPDE_LIMIT (0xff)
152#define VIDTCON1_VFPDE(_x) ((_x) << 24)
153
154#define VIDTCON1_HBPD_MASK (0xff << 16)
155#define VIDTCON1_HBPD_SHIFT (16)
156#define VIDTCON1_HBPD_LIMIT (0xff)
157#define VIDTCON1_HBPD(_x) ((_x) << 16)
158
159#define VIDTCON1_HFPD_MASK (0xff << 8)
160#define VIDTCON1_HFPD_SHIFT (8)
161#define VIDTCON1_HFPD_LIMIT (0xff)
162#define VIDTCON1_HFPD(_x) ((_x) << 8)
163
164#define VIDTCON1_HSPW_MASK (0xff << 0)
165#define VIDTCON1_HSPW_SHIFT (0)
166#define VIDTCON1_HSPW_LIMIT (0xff)
167#define VIDTCON1_HSPW(_x) ((_x) << 0)
168
169#define VIDTCON2 (0x18)
170#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
171#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
172#define VIDTCON2_LINEVAL_SHIFT (11)
173#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
174#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11)
175
176#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22)
177#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
178#define VIDTCON2_HOZVAL_SHIFT (0)
179#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
180#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0)
181
182/* WINCONx */
183
184
185#define WINCONx_BITSWP (1 << 18)
186#define WINCONx_BYTSWP (1 << 17)
187#define WINCONx_HAWSWP (1 << 16)
188#define WINCONx_WSWP (1 << 15)
189#define WINCONx_BURSTLEN_MASK (0x3 << 9)
190#define WINCONx_BURSTLEN_SHIFT (9)
191#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
192#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
193#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
194
195#define WINCONx_ENWIN (1 << 0)
196#define WINCON0_BPPMODE_MASK (0xf << 2)
197#define WINCON0_BPPMODE_SHIFT (2)
198#define WINCON0_BPPMODE_1BPP (0x0 << 2)
199#define WINCON0_BPPMODE_2BPP (0x1 << 2)
200#define WINCON0_BPPMODE_4BPP (0x2 << 2)
201#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
202#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
203#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
204#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
205#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
206
207#define WINCON1_BLD_PIX (1 << 6)
208
209#define WINCON1_ALPHA_SEL (1 << 1)
210#define WINCON1_BPPMODE_MASK (0xf << 2)
211#define WINCON1_BPPMODE_SHIFT (2)
212#define WINCON1_BPPMODE_1BPP (0x0 << 2)
213#define WINCON1_BPPMODE_2BPP (0x1 << 2)
214#define WINCON1_BPPMODE_4BPP (0x2 << 2)
215#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
216#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
217#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
218#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
219#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
220#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
221#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
222#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
223#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
224#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
225#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
226#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
227
228/* S5PV210 */
229#define SHADOWCON (0x34)
230#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))
231/* DMA channels (all windows) */
232#define SHADOWCON_CHx_ENABLE(_win) (1 << (_win))
233/* Local input channels (windows 0-2) */
234#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))
235
236#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
237#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
238#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
239#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
240#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11)
241
242#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
243#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
244#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
245#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
246#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0)
247
248#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
249#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
250#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
251#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
252#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11)
253
254#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
255#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
256#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
257#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
258#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0)
259
260/* For VIDOSD[1..4]C */
261#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
262#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
263#define VIDISD14C_ALPHA0_G_SHIFT (16)
264#define VIDISD14C_ALPHA0_G_LIMIT (0xf)
265#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
266#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
267#define VIDISD14C_ALPHA0_B_SHIFT (12)
268#define VIDISD14C_ALPHA0_B_LIMIT (0xf)
269#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
270#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
271#define VIDISD14C_ALPHA1_R_SHIFT (8)
272#define VIDISD14C_ALPHA1_R_LIMIT (0xf)
273#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
274#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
275#define VIDISD14C_ALPHA1_G_SHIFT (4)
276#define VIDISD14C_ALPHA1_G_LIMIT (0xf)
277#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
278#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
279#define VIDISD14C_ALPHA1_B_SHIFT (0)
280#define VIDISD14C_ALPHA1_B_LIMIT (0xf)
281#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
282
283/* Video buffer addresses */
284#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
285#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
286#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
287#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
288#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
289
290#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27)
291#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
292#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
293#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
294#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13)
295
296#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26)
297#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
298#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
299#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
300#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0)
301
302/* Interrupt controls and status */
303
304#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
305#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)
306#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)
307#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
308
309#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
310#define VIDINTCON0_INT_SYSSUBCON (1 << 18)
311#define VIDINTCON0_INT_I80IFDONE (1 << 17)
312
313#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
314#define VIDINTCON0_FRAMESEL0_SHIFT (15)
315#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
316#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
317#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
318#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
319
320#define VIDINTCON0_FRAMESEL1 (1 << 13)
321#define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13)
322#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13)
323#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13)
324#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13)
325#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13)
326
327#define VIDINTCON0_INT_FRAME (1 << 12)
328#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
329#define VIDINTCON0_FIFIOSEL_SHIFT (5)
330#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
331#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
332
333#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
334#define VIDINTCON0_FIFOLEVEL_SHIFT (2)
335#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
336#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
337#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
338#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
339#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
340
341#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
342#define VIDINTCON0_INT_FIFO_SHIFT (0)
343#define VIDINTCON0_INT_ENABLE (1 << 0)
344
345#define VIDINTCON1 (0x134)
346#define VIDINTCON1_INT_I180 (1 << 2)
347#define VIDINTCON1_INT_FRAME (1 << 1)
348#define VIDINTCON1_INT_FIFO (1 << 0)
349
350/* Window colour-key control registers */
351#define WKEYCON (0x140) /* 6410,V210 */
352
353#define WKEYCON0 (0x00)
354#define WKEYCON1 (0x04)
355
356#define WxKEYCON0_KEYBL_EN (1 << 26)
357#define WxKEYCON0_KEYEN_F (1 << 25)
358#define WxKEYCON0_DIRCON (1 << 24)
359#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
360#define WxKEYCON0_COMPKEY_SHIFT (0)
361#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)
362#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
363#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
364#define WxKEYCON1_COLVAL_SHIFT (0)
365#define WxKEYCON1_COLVAL_LIMIT (0xffffff)
366#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
367
368
369/* Window blanking (MAP) */
370
371#define WINxMAP_MAP (1 << 24)
372#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
373#define WINxMAP_MAP_COLOUR_SHIFT (0)
374#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)
375#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
376
377#define WPALCON_PAL_UPDATE (1 << 9)
378#define WPALCON_W1PAL_MASK (0x7 << 3)
379#define WPALCON_W1PAL_SHIFT (3)
380#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
381#define WPALCON_W1PAL_24BPP (0x1 << 3)
382#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
383#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
384#define WPALCON_W1PAL_18BPP (0x4 << 3)
385#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
386#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
387
388#define WPALCON_W0PAL_MASK (0x7 << 0)
389#define WPALCON_W0PAL_SHIFT (0)
390#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
391#define WPALCON_W0PAL_24BPP (0x1 << 0)
392#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
393#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
394#define WPALCON_W0PAL_18BPP (0x4 << 0)
395#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
396#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
397
398/* Blending equation control */
399#define BLENDCON (0x260)
400#define BLENDCON_NEW_MASK (1 << 0)
401#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
402#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
403
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 03:32:38 -0500