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authorThomas Abraham <thomas.abraham@linaro.org>2011-08-10 06:21:20 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2011-08-23 13:48:31 -0400
commit2a8d7bddf273477d6aa81405c9b4bae223e11ed9 (patch)
treec344956ef3499870b14158f438494ca5f27d0140 /arch/arm/plat-s5p
parent88bb4ea14c72f89c5265029c1891e5eb6521cc0f (diff)
ARM: SAMSUNG: Remove uart irq handling from plaform code
With uart tx/rx/err interrupt handling moved into the driver for s3c64xx and later SoC's, the uart interrupt handling in plaform code can be removed. The uart device irq resources is reduced to one and the related unused macros are removed. Suggested-by: Grant Likely <grant.likely@secretlab.ca> CC: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'arch/arm/plat-s5p')
-rw-r--r--arch/arm/plat-s5p/Kconfig1
-rw-r--r--arch/arm/plat-s5p/dev-uart.c84
-rw-r--r--arch/arm/plat-s5p/include/plat/irqs.h35
-rw-r--r--arch/arm/plat-s5p/irq.c34
4 files changed, 12 insertions, 142 deletions
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 9843c954c042..9a197e55f669 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -22,7 +22,6 @@ config PLAT_S5P
22 select PLAT_SAMSUNG 22 select PLAT_SAMSUNG
23 select SAMSUNG_CLKSRC 23 select SAMSUNG_CLKSRC
24 select SAMSUNG_IRQ_VIC_TIMER 24 select SAMSUNG_IRQ_VIC_TIMER
25 select SAMSUNG_IRQ_UART
26 help 25 help
27 Base platform code for Samsung's S5P series SoC. 26 Base platform code for Samsung's S5P series SoC.
28 27
diff --git a/arch/arm/plat-s5p/dev-uart.c b/arch/arm/plat-s5p/dev-uart.c
index afaf87fdb93e..c9308db36183 100644
--- a/arch/arm/plat-s5p/dev-uart.c
+++ b/arch/arm/plat-s5p/dev-uart.c
@@ -32,20 +32,10 @@ static struct resource s5p_uart0_resource[] = {
32 .flags = IORESOURCE_MEM, 32 .flags = IORESOURCE_MEM,
33 }, 33 },
34 [1] = { 34 [1] = {
35 .start = IRQ_S5P_UART_RX0, 35 .start = IRQ_UART0,
36 .end = IRQ_S5P_UART_RX0, 36 .end = IRQ_UART0,
37 .flags = IORESOURCE_IRQ, 37 .flags = IORESOURCE_IRQ,
38 }, 38 },
39 [2] = {
40 .start = IRQ_S5P_UART_TX0,
41 .end = IRQ_S5P_UART_TX0,
42 .flags = IORESOURCE_IRQ,
43 },
44 [3] = {
45 .start = IRQ_S5P_UART_ERR0,
46 .end = IRQ_S5P_UART_ERR0,
47 .flags = IORESOURCE_IRQ,
48 }
49}; 39};
50 40
51static struct resource s5p_uart1_resource[] = { 41static struct resource s5p_uart1_resource[] = {
@@ -55,18 +45,8 @@ static struct resource s5p_uart1_resource[] = {
55 .flags = IORESOURCE_MEM, 45 .flags = IORESOURCE_MEM,
56 }, 46 },
57 [1] = { 47 [1] = {
58 .start = IRQ_S5P_UART_RX1, 48 .start = IRQ_UART1,
59 .end = IRQ_S5P_UART_RX1, 49 .end = IRQ_UART1,
60 .flags = IORESOURCE_IRQ,
61 },
62 [2] = {
63 .start = IRQ_S5P_UART_TX1,
64 .end = IRQ_S5P_UART_TX1,
65 .flags = IORESOURCE_IRQ,
66 },
67 [3] = {
68 .start = IRQ_S5P_UART_ERR1,
69 .end = IRQ_S5P_UART_ERR1,
70 .flags = IORESOURCE_IRQ, 50 .flags = IORESOURCE_IRQ,
71 }, 51 },
72}; 52};
@@ -78,18 +58,8 @@ static struct resource s5p_uart2_resource[] = {
78 .flags = IORESOURCE_MEM, 58 .flags = IORESOURCE_MEM,
79 }, 59 },
80 [1] = { 60 [1] = {
81 .start = IRQ_S5P_UART_RX2, 61 .start = IRQ_UART2,
82 .end = IRQ_S5P_UART_RX2, 62 .end = IRQ_UART2,
83 .flags = IORESOURCE_IRQ,
84 },
85 [2] = {
86 .start = IRQ_S5P_UART_TX2,
87 .end = IRQ_S5P_UART_TX2,
88 .flags = IORESOURCE_IRQ,
89 },
90 [3] = {
91 .start = IRQ_S5P_UART_ERR2,
92 .end = IRQ_S5P_UART_ERR2,
93 .flags = IORESOURCE_IRQ, 63 .flags = IORESOURCE_IRQ,
94 }, 64 },
95}; 65};
@@ -102,18 +72,8 @@ static struct resource s5p_uart3_resource[] = {
102 .flags = IORESOURCE_MEM, 72 .flags = IORESOURCE_MEM,
103 }, 73 },
104 [1] = { 74 [1] = {
105 .start = IRQ_S5P_UART_RX3, 75 .start = IRQ_UART3,
106 .end = IRQ_S5P_UART_RX3, 76 .end = IRQ_UART3,
107 .flags = IORESOURCE_IRQ,
108 },
109 [2] = {
110 .start = IRQ_S5P_UART_TX3,
111 .end = IRQ_S5P_UART_TX3,
112 .flags = IORESOURCE_IRQ,
113 },
114 [3] = {
115 .start = IRQ_S5P_UART_ERR3,
116 .end = IRQ_S5P_UART_ERR3,
117 .flags = IORESOURCE_IRQ, 77 .flags = IORESOURCE_IRQ,
118 }, 78 },
119#endif 79#endif
@@ -127,18 +87,8 @@ static struct resource s5p_uart4_resource[] = {
127 .flags = IORESOURCE_MEM, 87 .flags = IORESOURCE_MEM,
128 }, 88 },
129 [1] = { 89 [1] = {
130 .start = IRQ_S5P_UART_RX4, 90 .start = IRQ_UART4,
131 .end = IRQ_S5P_UART_RX4, 91 .end = IRQ_UART4,
132 .flags = IORESOURCE_IRQ,
133 },
134 [2] = {
135 .start = IRQ_S5P_UART_TX4,
136 .end = IRQ_S5P_UART_TX4,
137 .flags = IORESOURCE_IRQ,
138 },
139 [3] = {
140 .start = IRQ_S5P_UART_ERR4,
141 .end = IRQ_S5P_UART_ERR4,
142 .flags = IORESOURCE_IRQ, 92 .flags = IORESOURCE_IRQ,
143 }, 93 },
144#endif 94#endif
@@ -152,18 +102,8 @@ static struct resource s5p_uart5_resource[] = {
152 .flags = IORESOURCE_MEM, 102 .flags = IORESOURCE_MEM,
153 }, 103 },
154 [1] = { 104 [1] = {
155 .start = IRQ_S5P_UART_RX5, 105 .start = IRQ_UART5,
156 .end = IRQ_S5P_UART_RX5, 106 .end = IRQ_UART5,
157 .flags = IORESOURCE_IRQ,
158 },
159 [2] = {
160 .start = IRQ_S5P_UART_TX5,
161 .end = IRQ_S5P_UART_TX5,
162 .flags = IORESOURCE_IRQ,
163 },
164 [3] = {
165 .start = IRQ_S5P_UART_ERR5,
166 .end = IRQ_S5P_UART_ERR5,
167 .flags = IORESOURCE_IRQ, 107 .flags = IORESOURCE_IRQ,
168 }, 108 },
169#endif 109#endif
diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h
index ba9121c60a2a..144dbfc6506d 100644
--- a/arch/arm/plat-s5p/include/plat/irqs.h
+++ b/arch/arm/plat-s5p/include/plat/irqs.h
@@ -37,41 +37,6 @@
37#define IRQ_VIC1_BASE S5P_VIC1_BASE 37#define IRQ_VIC1_BASE S5P_VIC1_BASE
38#define IRQ_VIC2_BASE S5P_VIC2_BASE 38#define IRQ_VIC2_BASE S5P_VIC2_BASE
39 39
40/* UART interrupts, each UART has 4 intterupts per channel so
41 * use the space between the ISA and S3C main interrupts. Note, these
42 * are not in the same order as the S3C24XX series! */
43
44#define IRQ_S5P_UART_BASE0 (16)
45#define IRQ_S5P_UART_BASE1 (20)
46#define IRQ_S5P_UART_BASE2 (24)
47#define IRQ_S5P_UART_BASE3 (28)
48
49#define UART_IRQ_RXD (0)
50#define UART_IRQ_ERR (1)
51#define UART_IRQ_TXD (2)
52
53#define IRQ_S5P_UART_RX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_RXD)
54#define IRQ_S5P_UART_TX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_TXD)
55#define IRQ_S5P_UART_ERR0 (IRQ_S5P_UART_BASE0 + UART_IRQ_ERR)
56
57#define IRQ_S5P_UART_RX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_RXD)
58#define IRQ_S5P_UART_TX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_TXD)
59#define IRQ_S5P_UART_ERR1 (IRQ_S5P_UART_BASE1 + UART_IRQ_ERR)
60
61#define IRQ_S5P_UART_RX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_RXD)
62#define IRQ_S5P_UART_TX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_TXD)
63#define IRQ_S5P_UART_ERR2 (IRQ_S5P_UART_BASE2 + UART_IRQ_ERR)
64
65#define IRQ_S5P_UART_RX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_RXD)
66#define IRQ_S5P_UART_TX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_TXD)
67#define IRQ_S5P_UART_ERR3 (IRQ_S5P_UART_BASE3 + UART_IRQ_ERR)
68
69/* S3C compatibilty defines */
70#define IRQ_S3CUART_RX0 IRQ_S5P_UART_RX0
71#define IRQ_S3CUART_RX1 IRQ_S5P_UART_RX1
72#define IRQ_S3CUART_RX2 IRQ_S5P_UART_RX2
73#define IRQ_S3CUART_RX3 IRQ_S5P_UART_RX3
74
75/* VIC based IRQs */ 40/* VIC based IRQs */
76 41
77#define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x)) 42#define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x))
diff --git a/arch/arm/plat-s5p/irq.c b/arch/arm/plat-s5p/irq.c
index a97c08957f49..afdaa1082b9f 100644
--- a/arch/arm/plat-s5p/irq.c
+++ b/arch/arm/plat-s5p/irq.c
@@ -17,42 +17,10 @@
17 17
18#include <asm/hardware/vic.h> 18#include <asm/hardware/vic.h>
19 19
20#include <linux/serial_core.h>
21#include <mach/map.h> 20#include <mach/map.h>
22#include <plat/regs-timer.h> 21#include <plat/regs-timer.h>
23#include <plat/regs-serial.h>
24#include <plat/cpu.h> 22#include <plat/cpu.h>
25#include <plat/irq-vic-timer.h> 23#include <plat/irq-vic-timer.h>
26#include <plat/irq-uart.h>
27
28/*
29 * Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
30 * are consecutive when looking up the interrupt in the demux routines.
31 */
32static struct s3c_uart_irq uart_irqs[] = {
33 [0] = {
34 .regs = S5P_VA_UART0,
35 .base_irq = IRQ_S5P_UART_BASE0,
36 .parent_irq = IRQ_UART0,
37 },
38 [1] = {
39 .regs = S5P_VA_UART1,
40 .base_irq = IRQ_S5P_UART_BASE1,
41 .parent_irq = IRQ_UART1,
42 },
43 [2] = {
44 .regs = S5P_VA_UART2,
45 .base_irq = IRQ_S5P_UART_BASE2,
46 .parent_irq = IRQ_UART2,
47 },
48#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
49 [3] = {
50 .regs = S5P_VA_UART3,
51 .base_irq = IRQ_S5P_UART_BASE3,
52 .parent_irq = IRQ_UART3,
53 },
54#endif
55};
56 24
57void __init s5p_init_irq(u32 *vic, u32 num_vic) 25void __init s5p_init_irq(u32 *vic, u32 num_vic)
58{ 26{
@@ -65,6 +33,4 @@ void __init s5p_init_irq(u32 *vic, u32 num_vic)
65#endif 33#endif
66 34
67 s3c_init_vic_timer_irq(5, IRQ_TIMER0); 35 s3c_init_vic_timer_irq(5, IRQ_TIMER0);
68
69 s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
70} 36}
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