diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-12-18 17:15:30 -0500 |
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committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-12-18 17:15:30 -0500 |
commit | fdb0a1a67e131f07a308730c80d07e330211d2e0 (patch) | |
tree | 4fbf35055fc965737c1ffdbcfe98d7ea8335f940 /arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h | |
parent | fc0b7a20368193e1f7cf1376624eed419b9c33e6 (diff) | |
parent | 7bb56d01f111890414fbe35412698485b68ed468 (diff) |
Merge branch 'next-merged' of git://aeryn.fluff.org.uk/bjdooks/linux into devel
Diffstat (limited to 'arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h')
-rw-r--r-- | arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h new file mode 100644 index 000000000000..21a906299d30 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h | |||
@@ -0,0 +1,36 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * GPIO Bank J register and configuration definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define S3C64XX_GPJCON (S3C64XX_GPJ_BASE + 0x00) | ||
16 | #define S3C64XX_GPJDAT (S3C64XX_GPJ_BASE + 0x04) | ||
17 | #define S3C64XX_GPJPUD (S3C64XX_GPJ_BASE + 0x08) | ||
18 | #define S3C64XX_GPJCONSLP (S3C64XX_GPJ_BASE + 0x0c) | ||
19 | #define S3C64XX_GPJPUDSLP (S3C64XX_GPJ_BASE + 0x10) | ||
20 | |||
21 | #define S3C64XX_GPJ_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) | ||
22 | #define S3C64XX_GPJ_INPUT(__gpio) (0x0 << ((__gpio) * 2)) | ||
23 | #define S3C64XX_GPJ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) | ||
24 | |||
25 | #define S3C64XX_GPJ0_VD16 (0x02 << 0) | ||
26 | #define S3C64XX_GPJ1_VD17 (0x02 << 2) | ||
27 | #define S3C64XX_GPJ2_VD18 (0x02 << 4) | ||
28 | #define S3C64XX_GPJ3_VD19 (0x02 << 6) | ||
29 | #define S3C64XX_GPJ4_VD20 (0x02 << 8) | ||
30 | #define S3C64XX_GPJ5_VD21 (0x02 << 10) | ||
31 | #define S3C64XX_GPJ6_VD22 (0x02 << 12) | ||
32 | #define S3C64XX_GPJ7_VD23 (0x02 << 14) | ||
33 | #define S3C64XX_GPJ8_LCD_HSYNC (0x02 << 16) | ||
34 | #define S3C64XX_GPJ9_LCD_VSYNC (0x02 << 18) | ||
35 | #define S3C64XX_GPJ10_LCD_VDEN (0x02 << 20) | ||
36 | #define S3C64XX_GPJ11_LCD_VCLK (0x02 << 22) | ||