diff options
author | Ben Dooks <ben-linux@fluff.org> | 2008-10-21 09:06:38 -0400 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2008-12-15 16:46:08 -0500 |
commit | e425382ed90d221ef9031a1b2d97d9bfedcf90c3 (patch) | |
tree | ca36882dba4caf8a9726ed67216251360c80ef59 /arch/arm/plat-s3c24xx | |
parent | c3391e36d697c997b6afeb045071e0be95219a3e (diff) |
[ARM] S3C24XX: Update clock data on resume
Update the clock settings on resume for suspend/resume
support so that if the boot loader changes anything or
the system's PLL is reset then we return with the correct
settings.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c24xx')
-rw-r--r-- | arch/arm/plat-s3c24xx/clock.c | 25 | ||||
-rw-r--r-- | arch/arm/plat-s3c24xx/include/plat/clock.h | 15 | ||||
-rw-r--r-- | arch/arm/plat-s3c24xx/pm.c | 4 | ||||
-rw-r--r-- | arch/arm/plat-s3c24xx/s3c244x.c | 21 |
4 files changed, 44 insertions, 21 deletions
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c index 334e696200be..a4a0a67a3074 100644 --- a/arch/arm/plat-s3c24xx/clock.c +++ b/arch/arm/plat-s3c24xx/clock.c | |||
@@ -47,6 +47,8 @@ | |||
47 | #include <mach/regs-clock.h> | 47 | #include <mach/regs-clock.h> |
48 | #include <mach/regs-gpio.h> | 48 | #include <mach/regs-gpio.h> |
49 | 49 | ||
50 | #include <plat/cpu-freq.h> | ||
51 | |||
50 | #include <plat/clock.h> | 52 | #include <plat/clock.h> |
51 | #include <plat/cpu.h> | 53 | #include <plat/cpu.h> |
52 | #include <plat/pll.h> | 54 | #include <plat/pll.h> |
@@ -327,24 +329,24 @@ int s3c24xx_register_clocks(struct clk **clks, int nr_clks) | |||
327 | 329 | ||
328 | /* initalise all the clocks */ | 330 | /* initalise all the clocks */ |
329 | 331 | ||
330 | int __init s3c24xx_setup_clocks(unsigned long xtal, | 332 | void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk, |
331 | unsigned long fclk, | 333 | unsigned long hclk, |
332 | unsigned long hclk, | 334 | unsigned long pclk) |
333 | unsigned long pclk) | ||
334 | { | 335 | { |
335 | printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n"); | 336 | clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON), |
336 | 337 | clk_xtal.rate); | |
337 | /* initialise the main system clocks */ | ||
338 | |||
339 | clk_xtal.rate = xtal; | ||
340 | clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON), xtal); | ||
341 | 338 | ||
342 | clk_mpll.rate = fclk; | 339 | clk_mpll.rate = fclk; |
343 | clk_h.rate = hclk; | 340 | clk_h.rate = hclk; |
344 | clk_p.rate = pclk; | 341 | clk_p.rate = pclk; |
345 | clk_f.rate = fclk; | 342 | clk_f.rate = fclk; |
343 | } | ||
346 | 344 | ||
347 | /* assume uart clocks are correctly setup */ | 345 | int __init s3c24xx_register_baseclocks(unsigned long xtal) |
346 | { | ||
347 | printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n"); | ||
348 | |||
349 | clk_xtal.rate = xtal; | ||
348 | 350 | ||
349 | /* register our clocks */ | 351 | /* register our clocks */ |
350 | 352 | ||
@@ -368,3 +370,4 @@ int __init s3c24xx_setup_clocks(unsigned long xtal, | |||
368 | 370 | ||
369 | return 0; | 371 | return 0; |
370 | } | 372 | } |
373 | |||
diff --git a/arch/arm/plat-s3c24xx/include/plat/clock.h b/arch/arm/plat-s3c24xx/include/plat/clock.h index 88a00c35b685..ba174aab76f2 100644 --- a/arch/arm/plat-s3c24xx/include/plat/clock.h +++ b/arch/arm/plat-s3c24xx/include/plat/clock.h | |||
@@ -60,7 +60,14 @@ extern int s3c2410_clkcon_enable(struct clk *clk, int enable); | |||
60 | extern int s3c24xx_register_clock(struct clk *clk); | 60 | extern int s3c24xx_register_clock(struct clk *clk); |
61 | extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks); | 61 | extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks); |
62 | 62 | ||
63 | extern int s3c24xx_setup_clocks(unsigned long xtal, | 63 | extern int s3c24xx_register_baseclocks(unsigned long xtal); |
64 | unsigned long fclk, | 64 | |
65 | unsigned long hclk, | 65 | extern void s3c24xx_setup_clocks(unsigned long fclk, |
66 | unsigned long pclk); | 66 | unsigned long hclk, |
67 | unsigned long pclk); | ||
68 | |||
69 | extern void s3c2410_setup_clocks(void); | ||
70 | extern void s3c2412_setup_clocks(void); | ||
71 | extern void s3c244x_setup_clocks(void); | ||
72 | extern void s3c2443_setup_clocks(void); | ||
73 | |||
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c index 8efb57ad5019..bc37cf49f973 100644 --- a/arch/arm/plat-s3c24xx/pm.c +++ b/arch/arm/plat-s3c24xx/pm.c | |||
@@ -76,11 +76,13 @@ static struct sleep_save core_save[] = { | |||
76 | SAVE_ITEM(S3C2410_BANKCON4), | 76 | SAVE_ITEM(S3C2410_BANKCON4), |
77 | SAVE_ITEM(S3C2410_BANKCON5), | 77 | SAVE_ITEM(S3C2410_BANKCON5), |
78 | 78 | ||
79 | #ifndef CONFIG_CPU_FREQ | ||
79 | SAVE_ITEM(S3C2410_CLKDIVN), | 80 | SAVE_ITEM(S3C2410_CLKDIVN), |
80 | SAVE_ITEM(S3C2410_MPLLCON), | 81 | SAVE_ITEM(S3C2410_MPLLCON), |
82 | SAVE_ITEM(S3C2410_REFRESH), | ||
83 | #endif | ||
81 | SAVE_ITEM(S3C2410_UPLLCON), | 84 | SAVE_ITEM(S3C2410_UPLLCON), |
82 | SAVE_ITEM(S3C2410_CLKSLOW), | 85 | SAVE_ITEM(S3C2410_CLKSLOW), |
83 | SAVE_ITEM(S3C2410_REFRESH), | ||
84 | }; | 86 | }; |
85 | 87 | ||
86 | static struct gpio_sleep { | 88 | static struct gpio_sleep { |
diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c index 7f33cef20bac..494368403055 100644 --- a/arch/arm/plat-s3c24xx/s3c244x.c +++ b/arch/arm/plat-s3c24xx/s3c244x.c | |||
@@ -29,6 +29,8 @@ | |||
29 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
30 | #include <asm/irq.h> | 30 | #include <asm/irq.h> |
31 | 31 | ||
32 | #include <plat/cpu-freq.h> | ||
33 | |||
32 | #include <mach/regs-clock.h> | 34 | #include <mach/regs-clock.h> |
33 | #include <plat/regs-serial.h> | 35 | #include <plat/regs-serial.h> |
34 | #include <mach/regs-gpio.h> | 36 | #include <mach/regs-gpio.h> |
@@ -71,15 +73,18 @@ void __init s3c244x_map_io(void) | |||
71 | s3c_device_usbgadget.name = "s3c2440-usbgadget"; | 73 | s3c_device_usbgadget.name = "s3c2440-usbgadget"; |
72 | } | 74 | } |
73 | 75 | ||
74 | void __init s3c244x_init_clocks(int xtal) | 76 | void __init_or_cpufreq s3c244x_setup_clocks(void) |
75 | { | 77 | { |
78 | struct clk *xtal_clk; | ||
76 | unsigned long clkdiv; | 79 | unsigned long clkdiv; |
77 | unsigned long camdiv; | 80 | unsigned long camdiv; |
81 | unsigned long xtal; | ||
78 | unsigned long hclk, fclk, pclk; | 82 | unsigned long hclk, fclk, pclk; |
79 | int hdiv = 1; | 83 | int hdiv = 1; |
80 | 84 | ||
81 | /* now we've got our machine bits initialised, work out what | 85 | xtal_clk = clk_get(NULL, "xtal"); |
82 | * clocks we've got */ | 86 | xtal = clk_get_rate(xtal_clk); |
87 | clk_put(xtal_clk); | ||
83 | 88 | ||
84 | fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2; | 89 | fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2; |
85 | 90 | ||
@@ -107,18 +112,24 @@ void __init s3c244x_init_clocks(int xtal) | |||
107 | } | 112 | } |
108 | 113 | ||
109 | hclk = fclk / hdiv; | 114 | hclk = fclk / hdiv; |
110 | pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1); | 115 | pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1); |
111 | 116 | ||
112 | /* print brief summary of clocks, etc */ | 117 | /* print brief summary of clocks, etc */ |
113 | 118 | ||
114 | printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", | 119 | printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", |
115 | print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); | 120 | print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); |
116 | 121 | ||
122 | s3c24xx_setup_clocks(fclk, hclk, pclk); | ||
123 | } | ||
124 | |||
125 | void __init s3c244x_init_clocks(int xtal) | ||
126 | { | ||
117 | /* initialise the clocks here, to allow other things like the | 127 | /* initialise the clocks here, to allow other things like the |
118 | * console to use them, and to add new ones after the initialisation | 128 | * console to use them, and to add new ones after the initialisation |
119 | */ | 129 | */ |
120 | 130 | ||
121 | s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); | 131 | s3c24xx_register_baseclocks(xtal); |
132 | s3c244x_setup_clocks(); | ||
122 | s3c2410_baseclk_add(); | 133 | s3c2410_baseclk_add(); |
123 | } | 134 | } |
124 | 135 | ||