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authorHeiko Stuebner <heiko@sntech.de>2012-05-12 03:22:18 -0400
committerKukjin Kim <kgene.kim@samsung.com>2012-05-12 03:22:18 -0400
commitde7bfff1b251395be9a229ee14191105d8d1385d (patch)
tree38fb42e1a376754d8584fd72daf04c110d29d1b3 /arch/arm/plat-s3c24xx
parent618ae08a8804cc545e692f12293e3dd165c4dd77 (diff)
ARM: S3C24XX: move common power-management code to mach-s3c24xx
This is the basic power-management code used by all s3c24xx machines. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/plat-s3c24xx')
-rw-r--r--arch/arm/plat-s3c24xx/Makefile3
-rw-r--r--arch/arm/plat-s3c24xx/irq-pm.c95
-rw-r--r--arch/arm/plat-s3c24xx/pm.c149
-rw-r--r--arch/arm/plat-s3c24xx/sleep.S84
4 files changed, 0 insertions, 331 deletions
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index 1e3126a2902e..a07bbc933b4e 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -21,9 +21,6 @@ obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpu-freq-debugfs.o
21 21
22# Architecture dependent builds 22# Architecture dependent builds
23 23
24obj-$(CONFIG_PM) += pm.o
25obj-$(CONFIG_PM) += irq-pm.o
26obj-$(CONFIG_PM) += sleep.o
27obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o 24obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o
28obj-$(CONFIG_S3C24XX_DMA) += dma.o 25obj-$(CONFIG_S3C24XX_DMA) += dma.o
29obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o 26obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o
diff --git a/arch/arm/plat-s3c24xx/irq-pm.c b/arch/arm/plat-s3c24xx/irq-pm.c
deleted file mode 100644
index 0efb2e2848c8..000000000000
--- a/arch/arm/plat-s3c24xx/irq-pm.c
+++ /dev/null
@@ -1,95 +0,0 @@
1/* linux/arch/arm/plat-s3c24xx/irq-om.c
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C24XX - IRQ PM code
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18
19#include <plat/cpu.h>
20#include <plat/pm.h>
21#include <plat/irq.h>
22
23#include <asm/irq.h>
24
25/* state for IRQs over sleep */
26
27/* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
28 *
29 * set bit to 1 in allow bitfield to enable the wakeup settings on it
30*/
31
32unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
33unsigned long s3c_irqwake_eintallow = 0x0000fff0L;
34
35int s3c_irq_wake(struct irq_data *data, unsigned int state)
36{
37 unsigned long irqbit = 1 << (data->irq - IRQ_EINT0);
38
39 if (!(s3c_irqwake_intallow & irqbit))
40 return -ENOENT;
41
42 printk(KERN_INFO "wake %s for irq %d\n",
43 state ? "enabled" : "disabled", data->irq);
44
45 if (!state)
46 s3c_irqwake_intmask |= irqbit;
47 else
48 s3c_irqwake_intmask &= ~irqbit;
49
50 return 0;
51}
52
53static struct sleep_save irq_save[] = {
54 SAVE_ITEM(S3C2410_INTMSK),
55 SAVE_ITEM(S3C2410_INTSUBMSK),
56};
57
58/* the extint values move between the s3c2410/s3c2440 and the s3c2412
59 * so we use an array to hold them, and to calculate the address of
60 * the register at run-time
61*/
62
63static unsigned long save_extint[3];
64static unsigned long save_eintflt[4];
65static unsigned long save_eintmask;
66
67int s3c24xx_irq_suspend(void)
68{
69 unsigned int i;
70
71 for (i = 0; i < ARRAY_SIZE(save_extint); i++)
72 save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4));
73
74 for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
75 save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4));
76
77 s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
78 save_eintmask = __raw_readl(S3C24XX_EINTMASK);
79
80 return 0;
81}
82
83void s3c24xx_irq_resume(void)
84{
85 unsigned int i;
86
87 for (i = 0; i < ARRAY_SIZE(save_extint); i++)
88 __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4));
89
90 for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
91 __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4));
92
93 s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
94 __raw_writel(save_eintmask, S3C24XX_EINTMASK);
95}
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
deleted file mode 100644
index 60627e63a254..000000000000
--- a/arch/arm/plat-s3c24xx/pm.c
+++ /dev/null
@@ -1,149 +0,0 @@
1/* linux/arch/arm/plat-s3c24xx/pm.c
2 *
3 * Copyright (c) 2004-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C24XX Power Manager (Suspend-To-RAM) support
7 *
8 * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * Parts based on arch/arm/mach-pxa/pm.c
25 *
26 * Thanks to Dimitry Andric for debugging
27*/
28
29#include <linux/init.h>
30#include <linux/suspend.h>
31#include <linux/errno.h>
32#include <linux/time.h>
33#include <linux/gpio.h>
34#include <linux/interrupt.h>
35#include <linux/serial_core.h>
36#include <linux/io.h>
37
38#include <plat/regs-serial.h>
39#include <mach/regs-clock.h>
40#include <mach/regs-gpio.h>
41#include <mach/regs-mem.h>
42#include <mach/regs-irq.h>
43
44#include <asm/mach/time.h>
45
46#include <plat/gpio-cfg.h>
47#include <plat/pm.h>
48
49#define PFX "s3c24xx-pm: "
50
51static struct sleep_save core_save[] = {
52 SAVE_ITEM(S3C2410_LOCKTIME),
53 SAVE_ITEM(S3C2410_CLKCON),
54
55 /* we restore the timings here, with the proviso that the board
56 * brings the system up in an slower, or equal frequency setting
57 * to the original system.
58 *
59 * if we cannot guarantee this, then things are going to go very
60 * wrong here, as we modify the refresh and both pll settings.
61 */
62
63 SAVE_ITEM(S3C2410_BWSCON),
64 SAVE_ITEM(S3C2410_BANKCON0),
65 SAVE_ITEM(S3C2410_BANKCON1),
66 SAVE_ITEM(S3C2410_BANKCON2),
67 SAVE_ITEM(S3C2410_BANKCON3),
68 SAVE_ITEM(S3C2410_BANKCON4),
69 SAVE_ITEM(S3C2410_BANKCON5),
70
71#ifndef CONFIG_CPU_FREQ
72 SAVE_ITEM(S3C2410_CLKDIVN),
73 SAVE_ITEM(S3C2410_MPLLCON),
74 SAVE_ITEM(S3C2410_REFRESH),
75#endif
76 SAVE_ITEM(S3C2410_UPLLCON),
77 SAVE_ITEM(S3C2410_CLKSLOW),
78};
79
80static struct sleep_save misc_save[] = {
81 SAVE_ITEM(S3C2410_DCLKCON),
82};
83
84/* s3c_pm_check_resume_pin
85 *
86 * check to see if the pin is configured correctly for sleep mode, and
87 * make any necessary adjustments if it is not
88*/
89
90static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
91{
92 unsigned long irqstate;
93 unsigned long pinstate;
94 int irq = gpio_to_irq(pin);
95
96 if (irqoffs < 4)
97 irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
98 else
99 irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
100
101 pinstate = s3c_gpio_getcfg(pin);
102
103 if (!irqstate) {
104 if (pinstate == S3C2410_GPIO_IRQ)
105 S3C_PMDBG("Leaving IRQ %d (pin %d) as is\n", irq, pin);
106 } else {
107 if (pinstate == S3C2410_GPIO_IRQ) {
108 S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin);
109 s3c_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
110 }
111 }
112}
113
114/* s3c_pm_configure_extint
115 *
116 * configure all external interrupt pins
117*/
118
119void s3c_pm_configure_extint(void)
120{
121 int pin;
122
123 /* for each of the external interrupts (EINT0..EINT15) we
124 * need to check wether it is an external interrupt source,
125 * and then configure it as an input if it is not
126 */
127
128 for (pin = S3C2410_GPF(0); pin <= S3C2410_GPF(7); pin++) {
129 s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF(0));
130 }
131
132 for (pin = S3C2410_GPG(0); pin <= S3C2410_GPG(7); pin++) {
133 s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG(0))+8);
134 }
135}
136
137
138void s3c_pm_restore_core(void)
139{
140 s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
141 s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
142}
143
144void s3c_pm_save_core(void)
145{
146 s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
147 s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
148}
149
diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S
deleted file mode 100644
index c56612569b40..000000000000
--- a/arch/arm/plat-s3c24xx/sleep.S
+++ /dev/null
@@ -1,84 +0,0 @@
1/* linux/arch/arm/plat-s3c24xx/sleep.S
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 Power Manager (Suspend-To-RAM) support
7 *
8 * Based on PXA/SA1100 sleep code by:
9 * Nicolas Pitre, (c) 2002 Monta Vista Software Inc
10 * Cliff Brake, (c) 2001
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25*/
26
27#include <linux/linkage.h>
28#include <asm/assembler.h>
29#include <mach/hardware.h>
30#include <mach/map.h>
31
32#include <mach/regs-gpio.h>
33#include <mach/regs-clock.h>
34#include <mach/regs-mem.h>
35#include <plat/regs-serial.h>
36
37/* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
38 * reset the UART configuration, only enable if you really need this!
39*/
40//#define CONFIG_DEBUG_RESUME
41
42 .text
43
44 /* sleep magic, to allow the bootloader to check for an valid
45 * image to resume to. Must be the first word before the
46 * s3c_cpu_resume entry.
47 */
48
49 .word 0x2bedf00d
50
51 /* s3c_cpu_resume
52 *
53 * resume code entry for bootloader to call
54 */
55
56ENTRY(s3c_cpu_resume)
57 mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
58 msr cpsr_c, r0
59
60 @@ load UART to allow us to print the two characters for
61 @@ resume debug
62
63 mov r2, #S3C24XX_PA_UART & 0xff000000
64 orr r2, r2, #S3C24XX_PA_UART & 0xff000
65
66#if 0
67 /* SMDK2440 LED set */
68 mov r14, #S3C24XX_PA_GPIO
69 ldr r12, [ r14, #0x54 ]
70 bic r12, r12, #3<<4
71 orr r12, r12, #1<<7
72 str r12, [ r14, #0x54 ]
73#endif
74
75#ifdef CONFIG_DEBUG_RESUME
76 mov r3, #'L'
77 strb r3, [ r2, #S3C2410_UTXH ]
781001:
79 ldrb r14, [ r3, #S3C2410_UTRSTAT ]
80 tst r14, #S3C2410_UTRSTAT_TXE
81 beq 1001b
82#endif /* CONFIG_DEBUG_RESUME */
83
84 b cpu_resume
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