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authorBen Dooks <ben-linux@fluff.org>2010-01-26 02:47:41 -0500
committerBen Dooks <ben-linux@fluff.org>2010-02-01 12:56:04 -0500
commit58bac7b8ded70c39bcd5f7037091051c277618aa (patch)
tree68fab2208ee756748a116ec39de1655923532d95 /arch/arm/plat-s3c24xx
parent70556b143ae4cf404a73c2461a6bf7fef3fefbf7 (diff)
ARM: S3C24XX: Move S3C2440/S3C2442 plat-s3c24xx support to mach-s3c2440
Remove the old common S3C2440 and S3C2442 SoC support from plat-s3c24xx into mach-s3c2440 now this directory is serving both SoCs. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c24xx')
-rw-r--r--arch/arm/plat-s3c24xx/Kconfig41
-rw-r--r--arch/arm/plat-s3c24xx/Makefile7
-rw-r--r--arch/arm/plat-s3c24xx/cpu.c2
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/s3c244x.h (renamed from arch/arm/plat-s3c24xx/s3c244x.h)2
-rw-r--r--arch/arm/plat-s3c24xx/s3c244x-clock.c138
-rw-r--r--arch/arm/plat-s3c24xx/s3c244x-irq.c142
-rw-r--r--arch/arm/plat-s3c24xx/s3c244x.c196
7 files changed, 2 insertions, 526 deletions
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index a806f359ceb6..0cc5760b668a 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -27,46 +27,6 @@ config S3C24XX_DCLK
27 help 27 help
28 Clock code for supporting DCLK/CLKOUT on S3C24XX architectures 28 Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
29 29
30config CPU_S3C244X
31 bool
32 depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442)
33 help
34 Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems.
35
36config S3C2440_CPUFREQ
37 bool "S3C2440/S3C2442 CPU Frequency scaling support"
38 depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442)
39 select S3C2410_CPUFREQ_UTILS
40 default y
41 help
42 CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs.
43
44config S3C2440_XTAL_12000000
45 bool
46 help
47 Indicate that the build needs to support 12MHz system
48 crystal.
49
50config S3C2440_XTAL_16934400
51 bool
52 help
53 Indicate that the build needs to support 16.9344MHz system
54 crystal.
55
56config S3C2440_PLL_12000000
57 bool
58 depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000
59 default y if CPU_FREQ_S3C24XX_PLL
60 help
61 PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals.
62
63config S3C2440_PLL_16934400
64 bool
65 depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400
66 default y if CPU_FREQ_S3C24XX_PLL
67 help
68 PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals.
69
70config S3C24XX_PWM 30config S3C24XX_PWM
71 bool "PWM device support" 31 bool "PWM device support"
72 select HAVE_PWM 32 select HAVE_PWM
@@ -74,7 +34,6 @@ config S3C24XX_PWM
74 Support for exporting the PWM timer blocks via the pwm device 34 Support for exporting the PWM timer blocks via the pwm device
75 system. 35 system.
76 36
77
78# gpio configurations 37# gpio configurations
79 38
80config S3C24XX_GPIO_EXTRA 39config S3C24XX_GPIO_EXTRA
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index e0100266d039..c2237c41141f 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -25,13 +25,6 @@ obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpu-freq-debugfs.o
25 25
26# Architecture dependant builds 26# Architecture dependant builds
27 27
28obj-$(CONFIG_CPU_S3C244X) += s3c244x.o
29obj-$(CONFIG_CPU_S3C244X) += s3c244x-irq.o
30obj-$(CONFIG_CPU_S3C244X) += s3c244x-clock.o
31obj-$(CONFIG_S3C2440_CPUFREQ) += s3c2440-cpufreq.o
32obj-$(CONFIG_S3C2440_PLL_12000000) += s3c2440-pll-12000000.o
33obj-$(CONFIG_S3C2440_PLL_16934400) += s3c2440-pll-16934400.o
34
35obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o 28obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
36obj-$(CONFIG_PM) += pm.o 29obj-$(CONFIG_PM) += pm.o
37obj-$(CONFIG_PM) += irq-pm.o 30obj-$(CONFIG_PM) += irq-pm.o
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 4af9dd948793..6ecf87af9602 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -49,7 +49,7 @@
49#include <plat/s3c2400.h> 49#include <plat/s3c2400.h>
50#include <plat/s3c2410.h> 50#include <plat/s3c2410.h>
51#include <plat/s3c2412.h> 51#include <plat/s3c2412.h>
52#include "s3c244x.h" 52#include <plat/s3c244x.h>
53#include <plat/s3c2440.h> 53#include <plat/s3c2440.h>
54#include <plat/s3c2442.h> 54#include <plat/s3c2442.h>
55#include <plat/s3c2443.h> 55#include <plat/s3c2443.h>
diff --git a/arch/arm/plat-s3c24xx/s3c244x.h b/arch/arm/plat-s3c24xx/include/plat/s3c244x.h
index 6aab5eaae2b4..8da0904c41ab 100644
--- a/arch/arm/plat-s3c24xx/s3c244x.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c244x.h
@@ -1,4 +1,4 @@
1/* linux/arch/arm/plat-s3c24xx/s3c244x.h 1/* linux/arch/arm/plat-s3c24xx/include/plat/s3c244x.h
2 * 2 *
3 * Copyright (c) 2004-2005 Simtec Electronics 3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
diff --git a/arch/arm/plat-s3c24xx/s3c244x-clock.c b/arch/arm/plat-s3c24xx/s3c244x-clock.c
deleted file mode 100644
index f8d96130d1d1..000000000000
--- a/arch/arm/plat-s3c24xx/s3c244x-clock.c
+++ /dev/null
@@ -1,138 +0,0 @@
1/* linux/arch/arm/plat-s3c24xx/s3c24xx-clock.c
2 *
3 * Copyright (c) 2004-2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2440/S3C2442 Common clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/errno.h>
29#include <linux/err.h>
30#include <linux/device.h>
31#include <linux/sysdev.h>
32#include <linux/interrupt.h>
33#include <linux/ioport.h>
34#include <linux/clk.h>
35#include <linux/io.h>
36
37#include <mach/hardware.h>
38#include <asm/atomic.h>
39#include <asm/irq.h>
40
41#include <mach/regs-clock.h>
42
43#include <plat/clock.h>
44#include <plat/cpu.h>
45
46static int s3c2440_setparent_armclk(struct clk *clk, struct clk *parent)
47{
48 unsigned long camdivn;
49 unsigned long dvs;
50
51 if (parent == &clk_f)
52 dvs = 0;
53 else if (parent == &clk_h)
54 dvs = S3C2440_CAMDIVN_DVSEN;
55 else
56 return -EINVAL;
57
58 clk->parent = parent;
59
60 camdivn = __raw_readl(S3C2440_CAMDIVN);
61 camdivn &= ~S3C2440_CAMDIVN_DVSEN;
62 camdivn |= dvs;
63 __raw_writel(camdivn, S3C2440_CAMDIVN);
64
65 return 0;
66}
67
68static struct clk clk_arm = {
69 .name = "armclk",
70 .id = -1,
71 .ops = &(struct clk_ops) {
72 .set_parent = s3c2440_setparent_armclk,
73 },
74};
75
76static int s3c244x_clk_add(struct sys_device *sysdev)
77{
78 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
79 unsigned long clkdivn;
80 struct clk *clock_upll;
81 int ret;
82
83 printk("S3C244X: Clock Support, DVS %s\n",
84 (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
85
86 clk_arm.parent = (camdivn & S3C2440_CAMDIVN_DVSEN) ? &clk_h : &clk_f;
87
88 ret = s3c24xx_register_clock(&clk_arm);
89 if (ret < 0) {
90 printk(KERN_ERR "S3C24XX: Failed to add armclk (%d)\n", ret);
91 return ret;
92 }
93
94 clock_upll = clk_get(NULL, "upll");
95 if (IS_ERR(clock_upll)) {
96 printk(KERN_ERR "S3C244X: Failed to get upll clock\n");
97 return -ENOENT;
98 }
99
100 /* check rate of UPLL, and if it is near 96MHz, then change
101 * to using half the UPLL rate for the system */
102
103 if (clk_get_rate(clock_upll) > (94 * MHZ)) {
104 clk_usb_bus.rate = clk_get_rate(clock_upll) / 2;
105
106 spin_lock(&clocks_lock);
107
108 clkdivn = __raw_readl(S3C2410_CLKDIVN);
109 clkdivn |= S3C2440_CLKDIVN_UCLK;
110 __raw_writel(clkdivn, S3C2410_CLKDIVN);
111
112 spin_unlock(&clocks_lock);
113 }
114
115 return 0;
116}
117
118static struct sysdev_driver s3c2440_clk_driver = {
119 .add = s3c244x_clk_add,
120};
121
122static int s3c2440_clk_init(void)
123{
124 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver);
125}
126
127arch_initcall(s3c2440_clk_init);
128
129static struct sysdev_driver s3c2442_clk_driver = {
130 .add = s3c244x_clk_add,
131};
132
133static int s3c2442_clk_init(void)
134{
135 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver);
136}
137
138arch_initcall(s3c2442_clk_init);
diff --git a/arch/arm/plat-s3c24xx/s3c244x-irq.c b/arch/arm/plat-s3c24xx/s3c244x-irq.c
deleted file mode 100644
index a75c0c2431ea..000000000000
--- a/arch/arm/plat-s3c24xx/s3c244x-irq.c
+++ /dev/null
@@ -1,142 +0,0 @@
1/* linux/arch/arm/plat-s3c24xx/s3c244x-irq.c
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20*/
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/sysdev.h>
27#include <linux/io.h>
28
29#include <mach/hardware.h>
30#include <asm/irq.h>
31
32#include <asm/mach/irq.h>
33
34#include <mach/regs-irq.h>
35#include <mach/regs-gpio.h>
36
37#include <plat/cpu.h>
38#include <plat/pm.h>
39#include <plat/irq.h>
40
41/* camera irq */
42
43static void s3c_irq_demux_cam(unsigned int irq,
44 struct irq_desc *desc)
45{
46 unsigned int subsrc, submsk;
47
48 /* read the current pending interrupts, and the mask
49 * for what it is available */
50
51 subsrc = __raw_readl(S3C2410_SUBSRCPND);
52 submsk = __raw_readl(S3C2410_INTSUBMSK);
53
54 subsrc &= ~submsk;
55 subsrc >>= 11;
56 subsrc &= 3;
57
58 if (subsrc != 0) {
59 if (subsrc & 1) {
60 generic_handle_irq(IRQ_S3C2440_CAM_C);
61 }
62 if (subsrc & 2) {
63 generic_handle_irq(IRQ_S3C2440_CAM_P);
64 }
65 }
66}
67
68#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
69
70static void
71s3c_irq_cam_mask(unsigned int irqno)
72{
73 s3c_irqsub_mask(irqno, INTMSK_CAM, 3<<11);
74}
75
76static void
77s3c_irq_cam_unmask(unsigned int irqno)
78{
79 s3c_irqsub_unmask(irqno, INTMSK_CAM);
80}
81
82static void
83s3c_irq_cam_ack(unsigned int irqno)
84{
85 s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11);
86}
87
88static struct irq_chip s3c_irq_cam = {
89 .mask = s3c_irq_cam_mask,
90 .unmask = s3c_irq_cam_unmask,
91 .ack = s3c_irq_cam_ack,
92};
93
94static int s3c244x_irq_add(struct sys_device *sysdev)
95{
96 unsigned int irqno;
97
98 set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip);
99 set_irq_handler(IRQ_NFCON, handle_level_irq);
100 set_irq_flags(IRQ_NFCON, IRQF_VALID);
101
102 /* add chained handler for camera */
103
104 set_irq_chip(IRQ_CAM, &s3c_irq_level_chip);
105 set_irq_handler(IRQ_CAM, handle_level_irq);
106 set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
107
108 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
109 set_irq_chip(irqno, &s3c_irq_cam);
110 set_irq_handler(irqno, handle_level_irq);
111 set_irq_flags(irqno, IRQF_VALID);
112 }
113
114 return 0;
115}
116
117static struct sysdev_driver s3c2440_irq_driver = {
118 .add = s3c244x_irq_add,
119 .suspend = s3c24xx_irq_suspend,
120 .resume = s3c24xx_irq_resume,
121};
122
123static int s3c2440_irq_init(void)
124{
125 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver);
126}
127
128arch_initcall(s3c2440_irq_init);
129
130static struct sysdev_driver s3c2442_irq_driver = {
131 .add = s3c244x_irq_add,
132 .suspend = s3c24xx_irq_suspend,
133 .resume = s3c24xx_irq_resume,
134};
135
136
137static int s3c2442_irq_init(void)
138{
139 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_irq_driver);
140}
141
142arch_initcall(s3c2442_irq_init);
diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c
deleted file mode 100644
index 12623a474b54..000000000000
--- a/arch/arm/plat-s3c24xx/s3c244x.c
+++ /dev/null
@@ -1,196 +0,0 @@
1/* linux/arch/arm/plat-s3c24xx/s3c244x.c
2 *
3 * Copyright (c) 2004-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C2440 and S3C2442 Mobile CPU support (not S3C2443)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/serial_core.h>
20#include <linux/platform_device.h>
21#include <linux/sysdev.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27#include <asm/mach/irq.h>
28
29#include <mach/hardware.h>
30#include <asm/irq.h>
31
32#include <plat/cpu-freq.h>
33
34#include <mach/regs-clock.h>
35#include <plat/regs-serial.h>
36#include <mach/regs-gpio.h>
37#include <mach/regs-gpioj.h>
38#include <mach/regs-dsc.h>
39
40#include <plat/s3c2410.h>
41#include <plat/s3c2440.h>
42#include "s3c244x.h"
43#include <plat/clock.h>
44#include <plat/devs.h>
45#include <plat/cpu.h>
46#include <plat/pm.h>
47#include <plat/pll.h>
48
49static struct map_desc s3c244x_iodesc[] __initdata = {
50 IODESC_ENT(CLKPWR),
51 IODESC_ENT(TIMER),
52 IODESC_ENT(WATCHDOG),
53};
54
55/* uart initialisation */
56
57void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no)
58{
59 s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
60}
61
62void __init s3c244x_map_io(void)
63{
64 /* register our io-tables */
65
66 iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc));
67
68 /* rename any peripherals used differing from the s3c2410 */
69
70 s3c_device_sdi.name = "s3c2440-sdi";
71 s3c_device_i2c0.name = "s3c2440-i2c";
72 s3c_device_nand.name = "s3c2440-nand";
73 s3c_device_ts.name = "s3c2440-ts";
74 s3c_device_usbgadget.name = "s3c2440-usbgadget";
75}
76
77void __init_or_cpufreq s3c244x_setup_clocks(void)
78{
79 struct clk *xtal_clk;
80 unsigned long clkdiv;
81 unsigned long camdiv;
82 unsigned long xtal;
83 unsigned long hclk, fclk, pclk;
84 int hdiv = 1;
85
86 xtal_clk = clk_get(NULL, "xtal");
87 xtal = clk_get_rate(xtal_clk);
88 clk_put(xtal_clk);
89
90 fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
91
92 clkdiv = __raw_readl(S3C2410_CLKDIVN);
93 camdiv = __raw_readl(S3C2440_CAMDIVN);
94
95 /* work out clock scalings */
96
97 switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
98 case S3C2440_CLKDIVN_HDIVN_1:
99 hdiv = 1;
100 break;
101
102 case S3C2440_CLKDIVN_HDIVN_2:
103 hdiv = 2;
104 break;
105
106 case S3C2440_CLKDIVN_HDIVN_4_8:
107 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
108 break;
109
110 case S3C2440_CLKDIVN_HDIVN_3_6:
111 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
112 break;
113 }
114
115 hclk = fclk / hdiv;
116 pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
117
118 /* print brief summary of clocks, etc */
119
120 printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
121 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
122
123 s3c24xx_setup_clocks(fclk, hclk, pclk);
124}
125
126void __init s3c244x_init_clocks(int xtal)
127{
128 /* initialise the clocks here, to allow other things like the
129 * console to use them, and to add new ones after the initialisation
130 */
131
132 s3c24xx_register_baseclocks(xtal);
133 s3c244x_setup_clocks();
134 s3c2410_baseclk_add();
135}
136
137#ifdef CONFIG_PM
138
139static struct sleep_save s3c244x_sleep[] = {
140 SAVE_ITEM(S3C2440_DSC0),
141 SAVE_ITEM(S3C2440_DSC1),
142 SAVE_ITEM(S3C2440_GPJDAT),
143 SAVE_ITEM(S3C2440_GPJCON),
144 SAVE_ITEM(S3C2440_GPJUP)
145};
146
147static int s3c244x_suspend(struct sys_device *dev, pm_message_t state)
148{
149 s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
150 return 0;
151}
152
153static int s3c244x_resume(struct sys_device *dev)
154{
155 s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
156 return 0;
157}
158
159#else
160#define s3c244x_suspend NULL
161#define s3c244x_resume NULL
162#endif
163
164/* Since the S3C2442 and S3C2440 share items, put both sysclasses here */
165
166struct sysdev_class s3c2440_sysclass = {
167 .name = "s3c2440-core",
168 .suspend = s3c244x_suspend,
169 .resume = s3c244x_resume
170};
171
172struct sysdev_class s3c2442_sysclass = {
173 .name = "s3c2442-core",
174 .suspend = s3c244x_suspend,
175 .resume = s3c244x_resume
176};
177
178/* need to register class before we actually register the device, and
179 * we also need to ensure that it has been initialised before any of the
180 * drivers even try to use it (even if not on an s3c2440 based system)
181 * as a driver which may support both 2410 and 2440 may try and use it.
182*/
183
184static int __init s3c2440_core_init(void)
185{
186 return sysdev_class_register(&s3c2440_sysclass);
187}
188
189core_initcall(s3c2440_core_init);
190
191static int __init s3c2442_core_init(void)
192{
193 return sysdev_class_register(&s3c2442_sysclass);
194}
195
196core_initcall(s3c2442_core_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 07:00:18 -0500