diff options
author | Heiko Stuebner <heiko@sntech.de> | 2011-10-14 02:08:57 -0400 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-10-14 02:15:53 -0400 |
commit | 33ccedfd1b79a7cf649b2991e95bae415c013240 (patch) | |
tree | a5210ff54f370adb3dd852cb1a99abaa0a7e2e27 /arch/arm/plat-s3c24xx | |
parent | 866a1c8c354e613c2bf378a1cd562756d4a32e75 (diff) |
ARM: S3C24XX: use clk_get_rate to init fclk in common_setup_clocks
Previously the fclk rate was calculated by dividing the pll through
the divider value of the armdiv. With a real armdiv clk in place it's
possible to simply read its value, which does essentially the same.
This change makes the whole fdiv_fn function pointers supplied to
s3c2443_common_init_clocks and s3c2443_common_setup_clocks
obsolete, so remove it too.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/plat-s3c24xx')
-rw-r--r-- | arch/arm/plat-s3c24xx/s3c2443-clock.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c index 40a87206400f..d3ebbeedf6d9 100644 --- a/arch/arm/plat-s3c24xx/s3c2443-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c | |||
@@ -520,8 +520,7 @@ static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0) | |||
520 | 520 | ||
521 | /* EPLLCON compatible enough to get on/off information */ | 521 | /* EPLLCON compatible enough to get on/off information */ |
522 | 522 | ||
523 | void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll, | 523 | void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll) |
524 | fdiv_fn get_fdiv) | ||
525 | { | 524 | { |
526 | unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); | 525 | unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); |
527 | unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); | 526 | unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); |
@@ -541,7 +540,7 @@ void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll, | |||
541 | pll = get_mpll(mpllcon, xtal); | 540 | pll = get_mpll(mpllcon, xtal); |
542 | clk_msysclk.clk.rate = pll; | 541 | clk_msysclk.clk.rate = pll; |
543 | 542 | ||
544 | fclk = pll / get_fdiv(clkdiv0); | 543 | fclk = clk_get_rate(&clk_armdiv); |
545 | hclk = s3c2443_prediv_getrate(&clk_prediv); | 544 | hclk = s3c2443_prediv_getrate(&clk_prediv); |
546 | hclk /= s3c2443_get_hdiv(clkdiv0); | 545 | hclk /= s3c2443_get_hdiv(clkdiv0); |
547 | pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1); | 546 | pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1); |
@@ -590,7 +589,6 @@ static struct clksrc_clk *clksrcs[] __initdata = { | |||
590 | }; | 589 | }; |
591 | 590 | ||
592 | void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, | 591 | void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, |
593 | fdiv_fn get_fdiv, | ||
594 | unsigned int *divs, int nr_divs, | 592 | unsigned int *divs, int nr_divs, |
595 | int divmask) | 593 | int divmask) |
596 | { | 594 | { |
@@ -620,5 +618,5 @@ void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, | |||
620 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | 618 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
621 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | 619 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
622 | 620 | ||
623 | s3c2443_common_setup_clocks(get_mpll, get_fdiv); | 621 | s3c2443_common_setup_clocks(get_mpll); |
624 | } | 622 | } |