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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2009-06-10 17:40:55 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-06-10 17:41:06 -0400
commit547c32aeb5a24178ef20488ae0508efcc32ae8e4 (patch)
treefdc33154820cfddc845cef2f67380dace655b28f /arch/arm/plat-s3c24xx
parentb0efb42478c81ed0ed9aa0dc444db200c32624f0 (diff)
parent99ae99533a059750c4b0f76295625b8ac5ea751a (diff)
Merge branch for-rmk-devel of git://aeryn.fluff.org.uk/bjdooks/linux into devel
Diffstat (limited to 'arch/arm/plat-s3c24xx')
-rw-r--r--arch/arm/plat-s3c24xx/Kconfig1
-rw-r--r--arch/arm/plat-s3c24xx/adc.c11
-rw-r--r--arch/arm/plat-s3c24xx/common-smdk.c25
-rw-r--r--arch/arm/plat-s3c24xx/devs.c30
-rw-r--r--arch/arm/plat-s3c24xx/dma.c151
-rw-r--r--arch/arm/plat-s3c24xx/gpio.c34
-rw-r--r--arch/arm/plat-s3c24xx/gpiolib.c50
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/dma-plat.h (renamed from arch/arm/plat-s3c24xx/include/plat/dma.h)12
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/map.h1
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/pm-core.h5
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/regs-dma.h145
-rw-r--r--arch/arm/plat-s3c24xx/pm.c222
-rw-r--r--arch/arm/plat-s3c24xx/setup-i2c.c5
-rw-r--r--arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c20
-rw-r--r--arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c20
15 files changed, 305 insertions, 427 deletions
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 2c8a2f5d75ff..5b0bc914f58e 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -71,6 +71,7 @@ config PM_SIMTEC
71config S3C2410_DMA 71config S3C2410_DMA
72 bool "S3C2410 DMA support" 72 bool "S3C2410 DMA support"
73 depends on ARCH_S3C2410 73 depends on ARCH_S3C2410
74 select S3C_DMA
74 help 75 help
75 S3C2410 DMA support. This is needed for drivers like sound which 76 S3C2410 DMA support. This is needed for drivers like sound which
76 use the S3C2410's DMA system to move data to and from the 77 use the S3C2410's DMA system to move data to and from the
diff --git a/arch/arm/plat-s3c24xx/adc.c b/arch/arm/plat-s3c24xx/adc.c
index 91adfa71c172..ee1baf11ad9e 100644
--- a/arch/arm/plat-s3c24xx/adc.c
+++ b/arch/arm/plat-s3c24xx/adc.c
@@ -45,7 +45,8 @@ struct s3c_adc_client {
45 unsigned char channel; 45 unsigned char channel;
46 46
47 void (*select_cb)(unsigned selected); 47 void (*select_cb)(unsigned selected);
48 void (*convert_cb)(unsigned val1, unsigned val2); 48 void (*convert_cb)(unsigned val1, unsigned val2,
49 unsigned *samples_left);
49}; 50};
50 51
51struct adc_device { 52struct adc_device {
@@ -158,7 +159,8 @@ static void s3c_adc_default_select(unsigned select)
158 159
159struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev, 160struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
160 void (*select)(unsigned int selected), 161 void (*select)(unsigned int selected),
161 void (*conv)(unsigned d0, unsigned d1), 162 void (*conv)(unsigned d0, unsigned d1,
163 unsigned *samples_left),
162 unsigned int is_ts) 164 unsigned int is_ts)
163{ 165{
164 struct s3c_adc_client *client; 166 struct s3c_adc_client *client;
@@ -227,9 +229,10 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
227 data1 = readl(adc->regs + S3C2410_ADCDAT1); 229 data1 = readl(adc->regs + S3C2410_ADCDAT1);
228 adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1); 230 adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1);
229 231
230 (client->convert_cb)(data0 & 0x3ff, data1 & 0x3ff); 232 client->nr_samples--;
233 (client->convert_cb)(data0 & 0x3ff, data1 & 0x3ff, &client->nr_samples);
231 234
232 if (--client->nr_samples > 0) { 235 if (client->nr_samples > 0) {
233 /* fire another conversion for this */ 236 /* fire another conversion for this */
234 237
235 client->select_cb(1); 238 client->select_cb(1);
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index 1a8347cec20a..aa119863c5ce 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -18,6 +18,7 @@
18#include <linux/list.h> 18#include <linux/list.h>
19#include <linux/timer.h> 19#include <linux/timer.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/gpio.h>
21#include <linux/sysdev.h> 22#include <linux/sysdev.h>
22#include <linux/platform_device.h> 23#include <linux/platform_device.h>
23 24
@@ -47,27 +48,27 @@
47/* LED devices */ 48/* LED devices */
48 49
49static struct s3c24xx_led_platdata smdk_pdata_led4 = { 50static struct s3c24xx_led_platdata smdk_pdata_led4 = {
50 .gpio = S3C2410_GPF4, 51 .gpio = S3C2410_GPF(4),
51 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, 52 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
52 .name = "led4", 53 .name = "led4",
53 .def_trigger = "timer", 54 .def_trigger = "timer",
54}; 55};
55 56
56static struct s3c24xx_led_platdata smdk_pdata_led5 = { 57static struct s3c24xx_led_platdata smdk_pdata_led5 = {
57 .gpio = S3C2410_GPF5, 58 .gpio = S3C2410_GPF(5),
58 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, 59 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
59 .name = "led5", 60 .name = "led5",
60 .def_trigger = "nand-disk", 61 .def_trigger = "nand-disk",
61}; 62};
62 63
63static struct s3c24xx_led_platdata smdk_pdata_led6 = { 64static struct s3c24xx_led_platdata smdk_pdata_led6 = {
64 .gpio = S3C2410_GPF6, 65 .gpio = S3C2410_GPF(6),
65 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, 66 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
66 .name = "led6", 67 .name = "led6",
67}; 68};
68 69
69static struct s3c24xx_led_platdata smdk_pdata_led7 = { 70static struct s3c24xx_led_platdata smdk_pdata_led7 = {
70 .gpio = S3C2410_GPF7, 71 .gpio = S3C2410_GPF(7),
71 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, 72 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
72 .name = "led7", 73 .name = "led7",
73}; 74};
@@ -184,15 +185,15 @@ void __init smdk_machine_init(void)
184{ 185{
185 /* Configure the LEDs (even if we have no LED support)*/ 186 /* Configure the LEDs (even if we have no LED support)*/
186 187
187 s3c2410_gpio_cfgpin(S3C2410_GPF4, S3C2410_GPF4_OUTP); 188 s3c2410_gpio_cfgpin(S3C2410_GPF(4), S3C2410_GPIO_OUTPUT);
188 s3c2410_gpio_cfgpin(S3C2410_GPF5, S3C2410_GPF5_OUTP); 189 s3c2410_gpio_cfgpin(S3C2410_GPF(5), S3C2410_GPIO_OUTPUT);
189 s3c2410_gpio_cfgpin(S3C2410_GPF6, S3C2410_GPF6_OUTP); 190 s3c2410_gpio_cfgpin(S3C2410_GPF(6), S3C2410_GPIO_OUTPUT);
190 s3c2410_gpio_cfgpin(S3C2410_GPF7, S3C2410_GPF7_OUTP); 191 s3c2410_gpio_cfgpin(S3C2410_GPF(7), S3C2410_GPIO_OUTPUT);
191 192
192 s3c2410_gpio_setpin(S3C2410_GPF4, 1); 193 s3c2410_gpio_setpin(S3C2410_GPF(4), 1);
193 s3c2410_gpio_setpin(S3C2410_GPF5, 1); 194 s3c2410_gpio_setpin(S3C2410_GPF(5), 1);
194 s3c2410_gpio_setpin(S3C2410_GPF6, 1); 195 s3c2410_gpio_setpin(S3C2410_GPF(6), 1);
195 s3c2410_gpio_setpin(S3C2410_GPF7, 1); 196 s3c2410_gpio_setpin(S3C2410_GPF(7), 1);
196 197
197 if (machine_is_smdk2443()) 198 if (machine_is_smdk2443())
198 smdk_nand_info.twrph0 = 50; 199 smdk_nand_info.twrph0 = 50;
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index 16ac01d9b8ab..4eb378c89a39 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -136,36 +136,6 @@ struct platform_device *s3c24xx_uart_src[4] = {
136struct platform_device *s3c24xx_uart_devs[4] = { 136struct platform_device *s3c24xx_uart_devs[4] = {
137}; 137};
138 138
139/* USB Host Controller */
140
141static struct resource s3c_usb_resource[] = {
142 [0] = {
143 .start = S3C24XX_PA_USBHOST,
144 .end = S3C24XX_PA_USBHOST + S3C24XX_SZ_USBHOST - 1,
145 .flags = IORESOURCE_MEM,
146 },
147 [1] = {
148 .start = IRQ_USBH,
149 .end = IRQ_USBH,
150 .flags = IORESOURCE_IRQ,
151 }
152};
153
154static u64 s3c_device_usb_dmamask = 0xffffffffUL;
155
156struct platform_device s3c_device_usb = {
157 .name = "s3c2410-ohci",
158 .id = -1,
159 .num_resources = ARRAY_SIZE(s3c_usb_resource),
160 .resource = s3c_usb_resource,
161 .dev = {
162 .dma_mask = &s3c_device_usb_dmamask,
163 .coherent_dma_mask = 0xffffffffUL
164 }
165};
166
167EXPORT_SYMBOL(s3c_device_usb);
168
169/* LCD Controller */ 139/* LCD Controller */
170 140
171static struct resource s3c_lcd_resource[] = { 141static struct resource s3c_lcd_resource[] = {
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 07326f632361..196b19123653 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -31,10 +31,10 @@
31#include <asm/irq.h> 31#include <asm/irq.h>
32#include <mach/hardware.h> 32#include <mach/hardware.h>
33#include <mach/dma.h> 33#include <mach/dma.h>
34
35#include <mach/map.h> 34#include <mach/map.h>
36 35
37#include <plat/dma.h> 36#include <plat/dma-plat.h>
37#include <plat/regs-dma.h>
38 38
39/* io map for dma */ 39/* io map for dma */
40static void __iomem *dma_base; 40static void __iomem *dma_base;
@@ -44,8 +44,6 @@ static int dma_channels;
44 44
45static struct s3c24xx_dma_selection dma_sel; 45static struct s3c24xx_dma_selection dma_sel;
46 46
47/* dma channel state information */
48struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
49 47
50/* debugging functions */ 48/* debugging functions */
51 49
@@ -135,21 +133,6 @@ dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan)
135#define dbg_showchan(chan) do { } while(0) 133#define dbg_showchan(chan) do { } while(0)
136#endif /* CONFIG_S3C2410_DMA_DEBUG */ 134#endif /* CONFIG_S3C2410_DMA_DEBUG */
137 135
138static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX];
139
140/* lookup_dma_channel
141 *
142 * change the dma channel number given into a real dma channel id
143*/
144
145static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel)
146{
147 if (channel & DMACH_LOW_LEVEL)
148 return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
149 else
150 return dma_chan_map[channel];
151}
152
153/* s3c2410_dma_stats_timeout 136/* s3c2410_dma_stats_timeout
154 * 137 *
155 * Update DMA stats from timeout info 138 * Update DMA stats from timeout info
@@ -214,8 +197,6 @@ s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
214 return 0; 197 return 0;
215} 198}
216 199
217
218
219/* s3c2410_dma_loadbuffer 200/* s3c2410_dma_loadbuffer
220 * 201 *
221 * load a buffer, and update the channel state 202 * load a buffer, and update the channel state
@@ -453,7 +434,7 @@ s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
453int s3c2410_dma_enqueue(unsigned int channel, void *id, 434int s3c2410_dma_enqueue(unsigned int channel, void *id,
454 dma_addr_t data, int size) 435 dma_addr_t data, int size)
455{ 436{
456 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 437 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
457 struct s3c2410_dma_buf *buf; 438 struct s3c2410_dma_buf *buf;
458 unsigned long flags; 439 unsigned long flags;
459 440
@@ -804,7 +785,7 @@ EXPORT_SYMBOL(s3c2410_dma_request);
804 785
805int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client) 786int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
806{ 787{
807 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 788 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
808 unsigned long flags; 789 unsigned long flags;
809 790
810 if (chan == NULL) 791 if (chan == NULL)
@@ -836,7 +817,7 @@ int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
836 chan->irq_claimed = 0; 817 chan->irq_claimed = 0;
837 818
838 if (!(channel & DMACH_LOW_LEVEL)) 819 if (!(channel & DMACH_LOW_LEVEL))
839 dma_chan_map[channel] = NULL; 820 s3c_dma_chan_map[channel] = NULL;
840 821
841 local_irq_restore(flags); 822 local_irq_restore(flags);
842 823
@@ -995,7 +976,7 @@ static int s3c2410_dma_started(struct s3c2410_dma_chan *chan)
995int 976int
996s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op) 977s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
997{ 978{
998 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 979 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
999 980
1000 if (chan == NULL) 981 if (chan == NULL)
1001 return -EINVAL; 982 return -EINVAL;
@@ -1038,14 +1019,13 @@ EXPORT_SYMBOL(s3c2410_dma_ctrl);
1038/* s3c2410_dma_config 1019/* s3c2410_dma_config
1039 * 1020 *
1040 * xfersize: size of unit in bytes (1,2,4) 1021 * xfersize: size of unit in bytes (1,2,4)
1041 * dcon: base value of the DCONx register
1042*/ 1022*/
1043 1023
1044int s3c2410_dma_config(unsigned int channel, 1024int s3c2410_dma_config(unsigned int channel,
1045 int xferunit, 1025 int xferunit)
1046 int dcon)
1047{ 1026{
1048 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 1027 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
1028 unsigned int dcon;
1049 1029
1050 pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n", 1030 pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
1051 __func__, channel, xferunit, dcon); 1031 __func__, channel, xferunit, dcon);
@@ -1055,10 +1035,33 @@ int s3c2410_dma_config(unsigned int channel,
1055 1035
1056 pr_debug("%s: Initial dcon is %08x\n", __func__, dcon); 1036 pr_debug("%s: Initial dcon is %08x\n", __func__, dcon);
1057 1037
1058 dcon |= chan->dcon & dma_sel.dcon_mask; 1038 dcon = chan->dcon & dma_sel.dcon_mask;
1059 1039
1060 pr_debug("%s: New dcon is %08x\n", __func__, dcon); 1040 pr_debug("%s: New dcon is %08x\n", __func__, dcon);
1061 1041
1042 switch (chan->req_ch) {
1043 case DMACH_I2S_IN:
1044 case DMACH_I2S_OUT:
1045 case DMACH_PCM_IN:
1046 case DMACH_PCM_OUT:
1047 case DMACH_MIC_IN:
1048 default:
1049 dcon |= S3C2410_DCON_HANDSHAKE;
1050 dcon |= S3C2410_DCON_SYNC_PCLK;
1051 break;
1052
1053 case DMACH_SDI:
1054 /* note, ensure if need HANDSHAKE or not */
1055 dcon |= S3C2410_DCON_SYNC_PCLK;
1056 break;
1057
1058 case DMACH_XD0:
1059 case DMACH_XD1:
1060 dcon |= S3C2410_DCON_HANDSHAKE;
1061 dcon |= S3C2410_DCON_SYNC_HCLK;
1062 break;
1063 }
1064
1062 switch (xferunit) { 1065 switch (xferunit) {
1063 case 1: 1066 case 1:
1064 dcon |= S3C2410_DCON_BYTE; 1067 dcon |= S3C2410_DCON_BYTE;
@@ -1090,58 +1093,6 @@ int s3c2410_dma_config(unsigned int channel,
1090 1093
1091EXPORT_SYMBOL(s3c2410_dma_config); 1094EXPORT_SYMBOL(s3c2410_dma_config);
1092 1095
1093int s3c2410_dma_setflags(unsigned int channel, unsigned int flags)
1094{
1095 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1096
1097 if (chan == NULL)
1098 return -EINVAL;
1099
1100 pr_debug("%s: chan=%p, flags=%08x\n", __func__, chan, flags);
1101
1102 chan->flags = flags;
1103
1104 return 0;
1105}
1106
1107EXPORT_SYMBOL(s3c2410_dma_setflags);
1108
1109
1110/* do we need to protect the settings of the fields from
1111 * irq?
1112*/
1113
1114int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn)
1115{
1116 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1117
1118 if (chan == NULL)
1119 return -EINVAL;
1120
1121 pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
1122
1123 chan->op_fn = rtn;
1124
1125 return 0;
1126}
1127
1128EXPORT_SYMBOL(s3c2410_dma_set_opfn);
1129
1130int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn)
1131{
1132 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1133
1134 if (chan == NULL)
1135 return -EINVAL;
1136
1137 pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
1138
1139 chan->callback_fn = rtn;
1140
1141 return 0;
1142}
1143
1144EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
1145 1096
1146/* s3c2410_dma_devconfig 1097/* s3c2410_dma_devconfig
1147 * 1098 *
@@ -1150,29 +1101,38 @@ EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
1150 * source: S3C2410_DMASRC_HW: source is hardware 1101 * source: S3C2410_DMASRC_HW: source is hardware
1151 * S3C2410_DMASRC_MEM: source is memory 1102 * S3C2410_DMASRC_MEM: source is memory
1152 * 1103 *
1153 * hwcfg: the value for xxxSTCn register,
1154 * bit 0: 0=increment pointer, 1=leave pointer
1155 * bit 1: 0=source is AHB, 1=source is APB
1156 *
1157 * devaddr: physical address of the source 1104 * devaddr: physical address of the source
1158*/ 1105*/
1159 1106
1160int s3c2410_dma_devconfig(int channel, 1107int s3c2410_dma_devconfig(int channel,
1161 enum s3c2410_dmasrc source, 1108 enum s3c2410_dmasrc source,
1162 int hwcfg,
1163 unsigned long devaddr) 1109 unsigned long devaddr)
1164{ 1110{
1165 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 1111 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
1112 unsigned int hwcfg;
1166 1113
1167 if (chan == NULL) 1114 if (chan == NULL)
1168 return -EINVAL; 1115 return -EINVAL;
1169 1116
1170 pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n", 1117 pr_debug("%s: source=%d, devaddr=%08lx\n",
1171 __func__, (int)source, hwcfg, devaddr); 1118 __func__, (int)source, devaddr);
1172 1119
1173 chan->source = source; 1120 chan->source = source;
1174 chan->dev_addr = devaddr; 1121 chan->dev_addr = devaddr;
1175 chan->hw_cfg = hwcfg; 1122
1123 switch (chan->req_ch) {
1124 case DMACH_XD0:
1125 case DMACH_XD1:
1126 hwcfg = 0; /* AHB */
1127 break;
1128
1129 default:
1130 hwcfg = S3C2410_DISRCC_APB;
1131 }
1132
1133 /* always assume our peripheral desintation is a fixed
1134 * address in memory. */
1135 hwcfg |= S3C2410_DISRCC_INC;
1176 1136
1177 switch (source) { 1137 switch (source) {
1178 case S3C2410_DMASRC_HW: 1138 case S3C2410_DMASRC_HW:
@@ -1219,7 +1179,7 @@ EXPORT_SYMBOL(s3c2410_dma_devconfig);
1219 1179
1220int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *dst) 1180int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *dst)
1221{ 1181{
1222 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 1182 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
1223 1183
1224 if (chan == NULL) 1184 if (chan == NULL)
1225 return -EINVAL; 1185 return -EINVAL;
@@ -1278,8 +1238,8 @@ static int s3c2410_dma_resume(struct sys_device *dev)
1278 1238
1279 printk(KERN_INFO "dma%d: restoring configuration\n", cp->number); 1239 printk(KERN_INFO "dma%d: restoring configuration\n", cp->number);
1280 1240
1281 s3c2410_dma_config(no, cp->xfer_unit, cp->dcon); 1241 s3c2410_dma_config(no, cp->xfer_unit);
1282 s3c2410_dma_devconfig(no, cp->source, cp->hw_cfg, cp->dev_addr); 1242 s3c2410_dma_devconfig(no, cp->source, cp->dev_addr);
1283 1243
1284 /* re-select the dma source for this channel */ 1244 /* re-select the dma source for this channel */
1285 1245
@@ -1476,7 +1436,8 @@ static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel)
1476 found: 1436 found:
1477 dmach = &s3c2410_chans[ch]; 1437 dmach = &s3c2410_chans[ch];
1478 dmach->map = ch_map; 1438 dmach->map = ch_map;
1479 dma_chan_map[channel] = dmach; 1439 dmach->req_ch = channel;
1440 s3c_dma_chan_map[channel] = dmach;
1480 1441
1481 /* select the channel */ 1442 /* select the channel */
1482 1443
diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c
index 4a899c279eb5..95df059b5a1d 100644
--- a/arch/arm/plat-s3c24xx/gpio.c
+++ b/arch/arm/plat-s3c24xx/gpio.c
@@ -183,35 +183,19 @@ EXPORT_SYMBOL(s3c2410_modify_misccr);
183 183
184int s3c2410_gpio_getirq(unsigned int pin) 184int s3c2410_gpio_getirq(unsigned int pin)
185{ 185{
186 if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15) 186 if (pin < S3C2410_GPF(0) || pin > S3C2410_GPG(15))
187 return -1; /* not valid interrupts */ 187 return -EINVAL; /* not valid interrupts */
188 188
189 if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7) 189 if (pin < S3C2410_GPG(0) && pin > S3C2410_GPF(7))
190 return -1; /* not valid pin */ 190 return -EINVAL; /* not valid pin */
191 191
192 if (pin < S3C2410_GPF4) 192 if (pin < S3C2410_GPF(4))
193 return (pin - S3C2410_GPF0) + IRQ_EINT0; 193 return (pin - S3C2410_GPF(0)) + IRQ_EINT0;
194 194
195 if (pin < S3C2410_GPG0) 195 if (pin < S3C2410_GPG(0))
196 return (pin - S3C2410_GPF4) + IRQ_EINT4; 196 return (pin - S3C2410_GPF(4)) + IRQ_EINT4;
197 197
198 return (pin - S3C2410_GPG0) + IRQ_EINT8; 198 return (pin - S3C2410_GPG(0)) + IRQ_EINT8;
199} 199}
200 200
201EXPORT_SYMBOL(s3c2410_gpio_getirq); 201EXPORT_SYMBOL(s3c2410_gpio_getirq);
202
203int s3c2410_gpio_irq2pin(unsigned int irq)
204{
205 if (irq >= IRQ_EINT0 && irq <= IRQ_EINT3)
206 return S3C2410_GPF0 + (irq - IRQ_EINT0);
207
208 if (irq >= IRQ_EINT4 && irq <= IRQ_EINT7)
209 return S3C2410_GPF4 + (irq - IRQ_EINT4);
210
211 if (irq >= IRQ_EINT8 && irq <= IRQ_EINT23)
212 return S3C2410_GPG0 + (irq - IRQ_EINT8);
213
214 return -EINVAL;
215}
216
217EXPORT_SYMBOL(s3c2410_gpio_irq2pin);
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
index 5c0491bf738b..6d7a961d3269 100644
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -15,6 +15,7 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/interrupt.h> 17#include <linux/interrupt.h>
18#include <linux/sysdev.h>
18#include <linux/ioport.h> 19#include <linux/ioport.h>
19#include <linux/io.h> 20#include <linux/io.h>
20#include <linux/gpio.h> 21#include <linux/gpio.h>
@@ -22,6 +23,7 @@
22#include <mach/gpio-core.h> 23#include <mach/gpio-core.h>
23#include <mach/hardware.h> 24#include <mach/hardware.h>
24#include <asm/irq.h> 25#include <asm/irq.h>
26#include <plat/pm.h>
25 27
26#include <mach/regs-gpio.h> 28#include <mach/regs-gpio.h>
27 29
@@ -77,9 +79,10 @@ static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
77 79
78struct s3c_gpio_chip s3c24xx_gpios[] = { 80struct s3c_gpio_chip s3c24xx_gpios[] = {
79 [0] = { 81 [0] = {
80 .base = S3C24XX_GPIO_BASE(S3C2410_GPA0), 82 .base = S3C2410_GPACON,
83 .pm = __gpio_pm(&s3c_gpio_pm_1bit),
81 .chip = { 84 .chip = {
82 .base = S3C2410_GPA0, 85 .base = S3C2410_GPA(0),
83 .owner = THIS_MODULE, 86 .owner = THIS_MODULE,
84 .label = "GPIOA", 87 .label = "GPIOA",
85 .ngpio = 24, 88 .ngpio = 24,
@@ -88,45 +91,50 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
88 }, 91 },
89 }, 92 },
90 [1] = { 93 [1] = {
91 .base = S3C24XX_GPIO_BASE(S3C2410_GPB0), 94 .base = S3C2410_GPBCON,
95 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
92 .chip = { 96 .chip = {
93 .base = S3C2410_GPB0, 97 .base = S3C2410_GPB(0),
94 .owner = THIS_MODULE, 98 .owner = THIS_MODULE,
95 .label = "GPIOB", 99 .label = "GPIOB",
96 .ngpio = 16, 100 .ngpio = 16,
97 }, 101 },
98 }, 102 },
99 [2] = { 103 [2] = {
100 .base = S3C24XX_GPIO_BASE(S3C2410_GPC0), 104 .base = S3C2410_GPCCON,
105 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
101 .chip = { 106 .chip = {
102 .base = S3C2410_GPC0, 107 .base = S3C2410_GPC(0),
103 .owner = THIS_MODULE, 108 .owner = THIS_MODULE,
104 .label = "GPIOC", 109 .label = "GPIOC",
105 .ngpio = 16, 110 .ngpio = 16,
106 }, 111 },
107 }, 112 },
108 [3] = { 113 [3] = {
109 .base = S3C24XX_GPIO_BASE(S3C2410_GPD0), 114 .base = S3C2410_GPDCON,
115 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
110 .chip = { 116 .chip = {
111 .base = S3C2410_GPD0, 117 .base = S3C2410_GPD(0),
112 .owner = THIS_MODULE, 118 .owner = THIS_MODULE,
113 .label = "GPIOD", 119 .label = "GPIOD",
114 .ngpio = 16, 120 .ngpio = 16,
115 }, 121 },
116 }, 122 },
117 [4] = { 123 [4] = {
118 .base = S3C24XX_GPIO_BASE(S3C2410_GPE0), 124 .base = S3C2410_GPECON,
125 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
119 .chip = { 126 .chip = {
120 .base = S3C2410_GPE0, 127 .base = S3C2410_GPE(0),
121 .label = "GPIOE", 128 .label = "GPIOE",
122 .owner = THIS_MODULE, 129 .owner = THIS_MODULE,
123 .ngpio = 16, 130 .ngpio = 16,
124 }, 131 },
125 }, 132 },
126 [5] = { 133 [5] = {
127 .base = S3C24XX_GPIO_BASE(S3C2410_GPF0), 134 .base = S3C2410_GPFCON,
135 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
128 .chip = { 136 .chip = {
129 .base = S3C2410_GPF0, 137 .base = S3C2410_GPF(0),
130 .owner = THIS_MODULE, 138 .owner = THIS_MODULE,
131 .label = "GPIOF", 139 .label = "GPIOF",
132 .ngpio = 8, 140 .ngpio = 8,
@@ -134,14 +142,24 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
134 }, 142 },
135 }, 143 },
136 [6] = { 144 [6] = {
137 .base = S3C24XX_GPIO_BASE(S3C2410_GPG0), 145 .base = S3C2410_GPGCON,
146 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
138 .chip = { 147 .chip = {
139 .base = S3C2410_GPG0, 148 .base = S3C2410_GPG(0),
140 .owner = THIS_MODULE, 149 .owner = THIS_MODULE,
141 .label = "GPIOG", 150 .label = "GPIOG",
142 .ngpio = 10, 151 .ngpio = 16,
143 .to_irq = s3c24xx_gpiolib_bankg_toirq, 152 .to_irq = s3c24xx_gpiolib_bankg_toirq,
144 }, 153 },
154 }, {
155 .base = S3C2410_GPHCON,
156 .pm = __gpio_pm(&s3c_gpio_pm_2bit),
157 .chip = {
158 .base = S3C2410_GPH(0),
159 .owner = THIS_MODULE,
160 .label = "GPIOH",
161 .ngpio = 11,
162 },
145 }, 163 },
146}; 164};
147 165
@@ -156,4 +174,4 @@ static __init int s3c24xx_gpiolib_init(void)
156 return 0; 174 return 0;
157} 175}
158 176
159arch_initcall(s3c24xx_gpiolib_init); 177core_initcall(s3c24xx_gpiolib_init);
diff --git a/arch/arm/plat-s3c24xx/include/plat/dma.h b/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
index c78efe316fc8..9565ead1bc9b 100644
--- a/arch/arm/plat-s3c24xx/include/plat/dma.h
+++ b/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
@@ -1,4 +1,4 @@
1/* linux/include/asm-arm/plat-s3c24xx/dma.h 1/* linux/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
2 * 2 *
3 * Copyright (C) 2006 Simtec Electronics 3 * Copyright (C) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
@@ -10,8 +10,10 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11*/ 11*/
12 12
13#include <plat/dma-core.h>
14
13extern struct sysdev_class dma_sysclass; 15extern struct sysdev_class dma_sysclass;
14extern struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS]; 16extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
15 17
16#define DMA_CH_VALID (1<<31) 18#define DMA_CH_VALID (1<<31)
17#define DMA_CH_NEVER (1<<30) 19#define DMA_CH_NEVER (1<<30)
@@ -31,8 +33,8 @@ struct s3c24xx_dma_map {
31 const char *name; 33 const char *name;
32 struct s3c24xx_dma_addr hw_addr; 34 struct s3c24xx_dma_addr hw_addr;
33 35
34 unsigned long channels[S3C2410_DMA_CHANNELS]; 36 unsigned long channels[S3C_DMA_CHANNELS];
35 unsigned long channels_rx[S3C2410_DMA_CHANNELS]; 37 unsigned long channels_rx[S3C_DMA_CHANNELS];
36}; 38};
37 39
38struct s3c24xx_dma_selection { 40struct s3c24xx_dma_selection {
@@ -58,7 +60,7 @@ extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
58*/ 60*/
59 61
60struct s3c24xx_dma_order_ch { 62struct s3c24xx_dma_order_ch {
61 unsigned int list[S3C2410_DMA_CHANNELS]; /* list of channels */ 63 unsigned int list[S3C_DMA_CHANNELS]; /* list of channels */
62 unsigned int flags; /* flags */ 64 unsigned int flags; /* flags */
63}; 65};
64 66
diff --git a/arch/arm/plat-s3c24xx/include/plat/map.h b/arch/arm/plat-s3c24xx/include/plat/map.h
index eed8f78e7593..c4d133436fc7 100644
--- a/arch/arm/plat-s3c24xx/include/plat/map.h
+++ b/arch/arm/plat-s3c24xx/include/plat/map.h
@@ -58,7 +58,6 @@
58#define S3C24XX_SZ_SPI SZ_1M 58#define S3C24XX_SZ_SPI SZ_1M
59#define S3C24XX_SZ_SDI SZ_1M 59#define S3C24XX_SZ_SDI SZ_1M
60#define S3C24XX_SZ_NAND SZ_1M 60#define S3C24XX_SZ_NAND SZ_1M
61#define S3C24XX_SZ_USBHOST SZ_1M
62 61
63/* GPIO ports */ 62/* GPIO ports */
64 63
diff --git a/arch/arm/plat-s3c24xx/include/plat/pm-core.h b/arch/arm/plat-s3c24xx/include/plat/pm-core.h
index c75882113e04..fb45dd9adca5 100644
--- a/arch/arm/plat-s3c24xx/include/plat/pm-core.h
+++ b/arch/arm/plat-s3c24xx/include/plat/pm-core.h
@@ -57,3 +57,8 @@ static inline void s3c_pm_arch_show_resume_irqs(void)
57 s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND), 57 s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
58 s3c_irqwake_eintmask); 58 s3c_irqwake_eintmask);
59} 59}
60
61static inline void s3c_pm_arch_update_uart(void __iomem *regs,
62 struct pm_uart_save *save)
63{
64}
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-dma.h b/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
new file mode 100644
index 000000000000..3bc0a216df97
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
@@ -0,0 +1,145 @@
1/* arch/arm/mach-s3c2410/include/mach/dma.h
2 *
3 * Copyright (C) 2003,2004,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C24XX DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* DMA Register definitions */
14
15#define S3C2410_DMA_DISRC (0x00)
16#define S3C2410_DMA_DISRCC (0x04)
17#define S3C2410_DMA_DIDST (0x08)
18#define S3C2410_DMA_DIDSTC (0x0C)
19#define S3C2410_DMA_DCON (0x10)
20#define S3C2410_DMA_DSTAT (0x14)
21#define S3C2410_DMA_DCSRC (0x18)
22#define S3C2410_DMA_DCDST (0x1C)
23#define S3C2410_DMA_DMASKTRIG (0x20)
24#define S3C2412_DMA_DMAREQSEL (0x24)
25#define S3C2443_DMA_DMAREQSEL (0x24)
26
27#define S3C2410_DISRCC_INC (1<<0)
28#define S3C2410_DISRCC_APB (1<<1)
29
30#define S3C2410_DMASKTRIG_STOP (1<<2)
31#define S3C2410_DMASKTRIG_ON (1<<1)
32#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
33
34#define S3C2410_DCON_DEMAND (0<<31)
35#define S3C2410_DCON_HANDSHAKE (1<<31)
36#define S3C2410_DCON_SYNC_PCLK (0<<30)
37#define S3C2410_DCON_SYNC_HCLK (1<<30)
38
39#define S3C2410_DCON_INTREQ (1<<29)
40
41#define S3C2410_DCON_CH0_XDREQ0 (0<<24)
42#define S3C2410_DCON_CH0_UART0 (1<<24)
43#define S3C2410_DCON_CH0_SDI (2<<24)
44#define S3C2410_DCON_CH0_TIMER (3<<24)
45#define S3C2410_DCON_CH0_USBEP1 (4<<24)
46
47#define S3C2410_DCON_CH1_XDREQ1 (0<<24)
48#define S3C2410_DCON_CH1_UART1 (1<<24)
49#define S3C2410_DCON_CH1_I2SSDI (2<<24)
50#define S3C2410_DCON_CH1_SPI (3<<24)
51#define S3C2410_DCON_CH1_USBEP2 (4<<24)
52
53#define S3C2410_DCON_CH2_I2SSDO (0<<24)
54#define S3C2410_DCON_CH2_I2SSDI (1<<24)
55#define S3C2410_DCON_CH2_SDI (2<<24)
56#define S3C2410_DCON_CH2_TIMER (3<<24)
57#define S3C2410_DCON_CH2_USBEP3 (4<<24)
58
59#define S3C2410_DCON_CH3_UART2 (0<<24)
60#define S3C2410_DCON_CH3_SDI (1<<24)
61#define S3C2410_DCON_CH3_SPI (2<<24)
62#define S3C2410_DCON_CH3_TIMER (3<<24)
63#define S3C2410_DCON_CH3_USBEP4 (4<<24)
64
65#define S3C2410_DCON_SRCSHIFT (24)
66#define S3C2410_DCON_SRCMASK (7<<24)
67
68#define S3C2410_DCON_BYTE (0<<20)
69#define S3C2410_DCON_HALFWORD (1<<20)
70#define S3C2410_DCON_WORD (2<<20)
71
72#define S3C2410_DCON_AUTORELOAD (0<<22)
73#define S3C2410_DCON_NORELOAD (1<<22)
74#define S3C2410_DCON_HWTRIG (1<<23)
75
76#ifdef CONFIG_CPU_S3C2440
77#define S3C2440_DIDSTC_CHKINT (1<<2)
78
79#define S3C2440_DCON_CH0_I2SSDO (5<<24)
80#define S3C2440_DCON_CH0_PCMIN (6<<24)
81
82#define S3C2440_DCON_CH1_PCMOUT (5<<24)
83#define S3C2440_DCON_CH1_SDI (6<<24)
84
85#define S3C2440_DCON_CH2_PCMIN (5<<24)
86#define S3C2440_DCON_CH2_MICIN (6<<24)
87
88#define S3C2440_DCON_CH3_MICIN (5<<24)
89#define S3C2440_DCON_CH3_PCMOUT (6<<24)
90#endif
91
92#ifdef CONFIG_CPU_S3C2412
93
94#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1)
95
96#define S3C2412_DMAREQSEL_HW (1)
97
98#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
99#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
100#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
101#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
102#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
103#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
104#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
105#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
106#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
107#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
108#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
109#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
110#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
111#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
112#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
113#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
114#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
115#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
116#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
117#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
118
119#endif
120
121#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1)
122
123#define S3C2443_DMAREQSEL_HW (1)
124
125#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
126#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
127#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
128#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
129#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
130#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
131#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
132#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
133#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
134#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
135#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
136#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
137#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
138#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
139#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
140#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
141#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
142#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
143#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
144#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
145#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index 062a29339a91..56e5253ca02c 100644
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -30,6 +30,7 @@
30#include <linux/suspend.h> 30#include <linux/suspend.h>
31#include <linux/errno.h> 31#include <linux/errno.h>
32#include <linux/time.h> 32#include <linux/time.h>
33#include <linux/gpio.h>
33#include <linux/interrupt.h> 34#include <linux/interrupt.h>
34#include <linux/serial_core.h> 35#include <linux/serial_core.h>
35#include <linux/io.h> 36#include <linux/io.h>
@@ -75,43 +76,10 @@ static struct sleep_save core_save[] = {
75 SAVE_ITEM(S3C2410_CLKSLOW), 76 SAVE_ITEM(S3C2410_CLKSLOW),
76}; 77};
77 78
78static struct gpio_sleep {
79 void __iomem *base;
80 unsigned int gpcon;
81 unsigned int gpdat;
82 unsigned int gpup;
83} gpio_save[] = {
84 [0] = {
85 .base = S3C2410_GPACON,
86 },
87 [1] = {
88 .base = S3C2410_GPBCON,
89 },
90 [2] = {
91 .base = S3C2410_GPCCON,
92 },
93 [3] = {
94 .base = S3C2410_GPDCON,
95 },
96 [4] = {
97 .base = S3C2410_GPECON,
98 },
99 [5] = {
100 .base = S3C2410_GPFCON,
101 },
102 [6] = {
103 .base = S3C2410_GPGCON,
104 },
105 [7] = {
106 .base = S3C2410_GPHCON,
107 },
108};
109
110static struct sleep_save misc_save[] = { 79static struct sleep_save misc_save[] = {
111 SAVE_ITEM(S3C2410_DCLKCON), 80 SAVE_ITEM(S3C2410_DCLKCON),
112}; 81};
113 82
114
115/* s3c_pm_check_resume_pin 83/* s3c_pm_check_resume_pin
116 * 84 *
117 * check to see if the pin is configured correctly for sleep mode, and 85 * check to see if the pin is configured correctly for sleep mode, and
@@ -156,195 +124,15 @@ void s3c_pm_configure_extint(void)
156 * and then configure it as an input if it is not 124 * and then configure it as an input if it is not
157 */ 125 */
158 126
159 for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) { 127 for (pin = S3C2410_GPF(0); pin <= S3C2410_GPF(7); pin++) {
160 s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF0); 128 s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF(0));
161 }
162
163 for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
164 s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
165 } 129 }
166}
167
168/* offsets for CON/DAT/UP registers */
169
170#define OFFS_CON (S3C2410_GPACON - S3C2410_GPACON)
171#define OFFS_DAT (S3C2410_GPADAT - S3C2410_GPACON)
172#define OFFS_UP (S3C2410_GPBUP - S3C2410_GPBCON)
173
174/* s3c_pm_save_gpios()
175 *
176 * Save the state of the GPIOs
177 */
178
179void s3c_pm_save_gpios(void)
180{
181 struct gpio_sleep *gps = gpio_save;
182 unsigned int gpio;
183
184 for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
185 void __iomem *base = gps->base;
186
187 gps->gpcon = __raw_readl(base + OFFS_CON);
188 gps->gpdat = __raw_readl(base + OFFS_DAT);
189
190 if (gpio > 0)
191 gps->gpup = __raw_readl(base + OFFS_UP);
192 130
131 for (pin = S3C2410_GPG(0); pin <= S3C2410_GPG(7); pin++) {
132 s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG(0))+8);
193 } 133 }
194} 134}
195 135
196/* Test whether the given masked+shifted bits of an GPIO configuration
197 * are one of the SFN (special function) modes. */
198
199static inline int is_sfn(unsigned long con)
200{
201 return (con == 2 || con == 3);
202}
203
204/* Test if the given masked+shifted GPIO configuration is an input */
205
206static inline int is_in(unsigned long con)
207{
208 return con == 0;
209}
210
211/* Test if the given masked+shifted GPIO configuration is an output */
212
213static inline int is_out(unsigned long con)
214{
215 return con == 1;
216}
217
218/**
219 * s3c2410_pm_restore_gpio() - restore the given GPIO bank
220 * @index: The number of the GPIO bank being resumed.
221 * @gps: The sleep confgiuration for the bank.
222 *
223 * Restore one of the GPIO banks that was saved during suspend. This is
224 * not as simple as once thought, due to the possibility of glitches
225 * from the order that the CON and DAT registers are set in.
226 *
227 * The three states the pin can be are {IN,OUT,SFN} which gives us 9
228 * combinations of changes to check. Three of these, if the pin stays
229 * in the same configuration can be discounted. This leaves us with
230 * the following:
231 *
232 * { IN => OUT } Change DAT first
233 * { IN => SFN } Change CON first
234 * { OUT => SFN } Change CON first, so new data will not glitch
235 * { OUT => IN } Change CON first, so new data will not glitch
236 * { SFN => IN } Change CON first
237 * { SFN => OUT } Change DAT first, so new data will not glitch [1]
238 *
239 * We do not currently deal with the UP registers as these control
240 * weak resistors, so a small delay in change should not need to bring
241 * these into the calculations.
242 *
243 * [1] this assumes that writing to a pin DAT whilst in SFN will set the
244 * state for when it is next output.
245 */
246
247static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps)
248{
249 void __iomem *base = gps->base;
250 unsigned long gps_gpcon = gps->gpcon;
251 unsigned long gps_gpdat = gps->gpdat;
252 unsigned long old_gpcon;
253 unsigned long old_gpdat;
254 unsigned long old_gpup = 0x0;
255 unsigned long gpcon;
256 int nr;
257
258 old_gpcon = __raw_readl(base + OFFS_CON);
259 old_gpdat = __raw_readl(base + OFFS_DAT);
260
261 if (base == S3C2410_GPACON) {
262 /* GPACON only has one bit per control / data and no PULLUPs.
263 * GPACON[x] = 0 => Output, 1 => SFN */
264
265 /* first set all SFN bits to SFN */
266
267 gpcon = old_gpcon | gps->gpcon;
268 __raw_writel(gpcon, base + OFFS_CON);
269
270 /* now set all the other bits */
271
272 __raw_writel(gps_gpdat, base + OFFS_DAT);
273 __raw_writel(gps_gpcon, base + OFFS_CON);
274 } else {
275 unsigned long old, new, mask;
276 unsigned long change_mask = 0x0;
277
278 old_gpup = __raw_readl(base + OFFS_UP);
279
280 /* Create a change_mask of all the items that need to have
281 * their CON value changed before their DAT value, so that
282 * we minimise the work between the two settings.
283 */
284
285 for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
286 old = (old_gpcon & mask) >> nr;
287 new = (gps_gpcon & mask) >> nr;
288
289 /* If there is no change, then skip */
290
291 if (old == new)
292 continue;
293
294 /* If both are special function, then skip */
295
296 if (is_sfn(old) && is_sfn(new))
297 continue;
298
299 /* Change is IN => OUT, do not change now */
300
301 if (is_in(old) && is_out(new))
302 continue;
303
304 /* Change is SFN => OUT, do not change now */
305
306 if (is_sfn(old) && is_out(new))
307 continue;
308
309 /* We should now be at the case of IN=>SFN,
310 * OUT=>SFN, OUT=>IN, SFN=>IN. */
311
312 change_mask |= mask;
313 }
314
315 /* Write the new CON settings */
316
317 gpcon = old_gpcon & ~change_mask;
318 gpcon |= gps_gpcon & change_mask;
319
320 __raw_writel(gpcon, base + OFFS_CON);
321
322 /* Now change any items that require DAT,CON */
323
324 __raw_writel(gps_gpdat, base + OFFS_DAT);
325 __raw_writel(gps_gpcon, base + OFFS_CON);
326 __raw_writel(gps->gpup, base + OFFS_UP);
327 }
328
329 S3C_PMDBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n",
330 index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
331}
332
333
334/** s3c2410_pm_restore_gpios()
335 *
336 * Restore the state of the GPIOs
337 */
338
339void s3c_pm_restore_gpios(void)
340{
341 struct gpio_sleep *gps = gpio_save;
342 int gpio;
343
344 for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
345 s3c2410_pm_restore_gpio(gpio, gps);
346 }
347}
348 136
349void s3c_pm_restore_core(void) 137void s3c_pm_restore_core(void)
350{ 138{
diff --git a/arch/arm/plat-s3c24xx/setup-i2c.c b/arch/arm/plat-s3c24xx/setup-i2c.c
index d62b7e7fb355..71a6accf114e 100644
--- a/arch/arm/plat-s3c24xx/setup-i2c.c
+++ b/arch/arm/plat-s3c24xx/setup-i2c.c
@@ -11,6 +11,7 @@
11*/ 11*/
12 12
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/gpio.h>
14 15
15struct platform_device; 16struct platform_device;
16 17
@@ -20,6 +21,6 @@ struct platform_device;
20 21
21void s3c_i2c0_cfg_gpio(struct platform_device *dev) 22void s3c_i2c0_cfg_gpio(struct platform_device *dev)
22{ 23{
23 s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA); 24 s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPE15_IICSDA);
24 s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL); 25 s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPE14_IICSCL);
25} 26}
diff --git a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
index 8b403cbb53d2..9edf7894eedd 100644
--- a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
+++ b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
@@ -22,16 +22,16 @@ void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
22 int enable) 22 int enable)
23{ 23{
24 if (enable) { 24 if (enable) {
25 s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPE13_SPICLK0); 25 s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPE13_SPICLK0);
26 s3c2410_gpio_cfgpin(S3C2410_GPE12, S3C2410_GPE12_SPIMOSI0); 26 s3c2410_gpio_cfgpin(S3C2410_GPE(12), S3C2410_GPE12_SPIMOSI0);
27 s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPE11_SPIMISO0); 27 s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPE11_SPIMISO0);
28 s3c2410_gpio_pullup(S3C2410_GPE11, 0); 28 s3c2410_gpio_pullup(S3C2410_GPE(11), 0);
29 s3c2410_gpio_pullup(S3C2410_GPE13, 0); 29 s3c2410_gpio_pullup(S3C2410_GPE(13), 0);
30 } else { 30 } else {
31 s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPIO_INPUT); 31 s3c2410_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPIO_INPUT);
32 s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPIO_INPUT); 32 s3c2410_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPIO_INPUT);
33 s3c2410_gpio_pullup(S3C2410_GPE11, 1); 33 s3c2410_gpio_pullup(S3C2410_GPE(11), 1);
34 s3c2410_gpio_pullup(S3C2410_GPE12, 1); 34 s3c2410_gpio_pullup(S3C2410_GPE(12), 1);
35 s3c2410_gpio_pullup(S3C2410_GPE13, 1); 35 s3c2410_gpio_pullup(S3C2410_GPE(13), 1);
36 } 36 }
37} 37}
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
index 8fccd4e549f0..f34d0fc69ad8 100644
--- a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
+++ b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
@@ -22,16 +22,16 @@ void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
22 int enable) 22 int enable)
23{ 23{
24 if (enable) { 24 if (enable) {
25 s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPG7_SPICLK1); 25 s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPG7_SPICLK1);
26 s3c2410_gpio_cfgpin(S3C2410_GPG6, S3C2410_GPG6_SPIMOSI1); 26 s3c2410_gpio_cfgpin(S3C2410_GPG(6), S3C2410_GPG6_SPIMOSI1);
27 s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPG5_SPIMISO1); 27 s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPG5_SPIMISO1);
28 s3c2410_gpio_pullup(S3C2410_GPG5, 0); 28 s3c2410_gpio_pullup(S3C2410_GPG(5), 0);
29 s3c2410_gpio_pullup(S3C2410_GPG6, 0); 29 s3c2410_gpio_pullup(S3C2410_GPG(6), 0);
30 } else { 30 } else {
31 s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPIO_INPUT); 31 s3c2410_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPIO_INPUT);
32 s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPIO_INPUT); 32 s3c2410_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPIO_INPUT);
33 s3c2410_gpio_pullup(S3C2410_GPG5, 1); 33 s3c2410_gpio_pullup(S3C2410_GPG(5), 1);
34 s3c2410_gpio_pullup(S3C2410_GPG6, 1); 34 s3c2410_gpio_pullup(S3C2410_GPG(6), 1);
35 s3c2410_gpio_pullup(S3C2410_GPG7, 1); 35 s3c2410_gpio_pullup(S3C2410_GPG(7), 1);
36 } 36 }
37} 37}
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-30 15:30:09 -0400