diff options
author | Rusty Russell <rusty@rustcorp.com.au> | 2008-12-31 07:35:57 -0500 |
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committer | Rusty Russell <rusty@rustcorp.com.au> | 2008-12-31 07:35:57 -0500 |
commit | 2ca1a615835d9f4990f42102ab1f2ef434e7e89c (patch) | |
tree | 726cf3d5f29a6c66c44e4bd68e7ebed2fd83d059 /arch/arm/plat-s3c/include/plat/regs-timer.h | |
parent | e12f0102ac81d660c9f801d0a0e10ccf4537a9de (diff) | |
parent | 6a94cb73064c952255336cc57731904174b2c58f (diff) |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts:
arch/x86/kernel/io_apic.c
Diffstat (limited to 'arch/arm/plat-s3c/include/plat/regs-timer.h')
-rw-r--r-- | arch/arm/plat-s3c/include/plat/regs-timer.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/arm/plat-s3c/include/plat/regs-timer.h b/arch/arm/plat-s3c/include/plat/regs-timer.h index cc0eedd53e38..d097d92f8cc7 100644 --- a/arch/arm/plat-s3c/include/plat/regs-timer.h +++ b/arch/arm/plat-s3c/include/plat/regs-timer.h | |||
@@ -10,7 +10,6 @@ | |||
10 | * S3C2410 Timer configuration | 10 | * S3C2410 Timer configuration |
11 | */ | 11 | */ |
12 | 12 | ||
13 | |||
14 | #ifndef __ASM_ARCH_REGS_TIMER_H | 13 | #ifndef __ASM_ARCH_REGS_TIMER_H |
15 | #define __ASM_ARCH_REGS_TIMER_H | 14 | #define __ASM_ARCH_REGS_TIMER_H |
16 | 15 | ||
@@ -21,6 +20,8 @@ | |||
21 | #define S3C2410_TCFG1 S3C_TIMERREG(0x04) | 20 | #define S3C2410_TCFG1 S3C_TIMERREG(0x04) |
22 | #define S3C2410_TCON S3C_TIMERREG(0x08) | 21 | #define S3C2410_TCON S3C_TIMERREG(0x08) |
23 | 22 | ||
23 | #define S3C64XX_TINT_CSTAT S3C_TIMERREG(0x44) | ||
24 | |||
24 | #define S3C2410_TCFG_PRESCALER0_MASK (255<<0) | 25 | #define S3C2410_TCFG_PRESCALER0_MASK (255<<0) |
25 | #define S3C2410_TCFG_PRESCALER1_MASK (255<<8) | 26 | #define S3C2410_TCFG_PRESCALER1_MASK (255<<8) |
26 | #define S3C2410_TCFG_PRESCALER1_SHIFT (8) | 27 | #define S3C2410_TCFG_PRESCALER1_SHIFT (8) |
@@ -72,6 +73,14 @@ | |||
72 | #define S3C2410_TCFG1_MUX_TCLK (4<<0) | 73 | #define S3C2410_TCFG1_MUX_TCLK (4<<0) |
73 | #define S3C2410_TCFG1_MUX_MASK (15<<0) | 74 | #define S3C2410_TCFG1_MUX_MASK (15<<0) |
74 | 75 | ||
76 | #define S3C64XX_TCFG1_MUX_DIV1 (0<<0) | ||
77 | #define S3C64XX_TCFG1_MUX_DIV2 (1<<0) | ||
78 | #define S3C64XX_TCFG1_MUX_DIV4 (2<<0) | ||
79 | #define S3C64XX_TCFG1_MUX_DIV8 (3<<0) | ||
80 | #define S3C64XX_TCFG1_MUX_DIV16 (4<<0) | ||
81 | #define S3C64XX_TCFG1_MUX_TCLK (5<<0) /* 3 sets of TCLK */ | ||
82 | #define S3C64XX_TCFG1_MUX_MASK (15<<0) | ||
83 | |||
75 | #define S3C2410_TCFG1_SHIFT(x) ((x) * 4) | 84 | #define S3C2410_TCFG1_SHIFT(x) ((x) * 4) |
76 | 85 | ||
77 | /* for each timer, we have an count buffer, an compare buffer and | 86 | /* for each timer, we have an count buffer, an compare buffer and |