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authorLennert Buytenhek <buytenh@wantstofly.org>2008-03-27 14:51:40 -0400
committerNicolas Pitre <nico@marvell.com>2008-03-27 14:51:40 -0400
commit2bac1de2031aa4cad88a437d4410ec289da4f7dc (patch)
tree1f9abbf6f3d428bbdcbfc93337e3e2e28e3d81c9 /arch/arm/plat-orion
parentabc0197d7a74e51a1581ce9971d7c2c0f2adadaf (diff)
plat-orion: share time handling code
Split off Orion time handling code into plat-orion/. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Reviewed-by: Tzachi Perelstein <tzachi@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm/plat-orion')
-rw-r--r--arch/arm/plat-orion/Makefile2
-rw-r--r--arch/arm/plat-orion/time.c203
2 files changed, 204 insertions, 1 deletions
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index b33ecb60183d..198f3dde2be3 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := irq.o pcie.o 5obj-y := irq.o pcie.o time.o
6obj-m := 6obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
new file mode 100644
index 000000000000..28b5285446e8
--- /dev/null
+++ b/arch/arm/plat-orion/time.c
@@ -0,0 +1,203 @@
1/*
2 * arch/arm/plat-orion/time.c
3 *
4 * Marvell Orion SoC timer handling.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 *
10 * Timer 0 is used as free-running clocksource, while timer 1 is
11 * used as clock_event_device.
12 */
13
14#include <linux/kernel.h>
15#include <linux/clockchips.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <asm/mach/time.h>
19#include <asm/arch/hardware.h>
20
21/*
22 * Number of timer ticks per jiffy.
23 */
24static u32 ticks_per_jiffy;
25
26
27/*
28 * Timer block registers.
29 */
30#define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000)
31#define TIMER0_EN 0x0001
32#define TIMER0_RELOAD_EN 0x0002
33#define TIMER1_EN 0x0004
34#define TIMER1_RELOAD_EN 0x0008
35#define TIMER0_RELOAD (TIMER_VIRT_BASE + 0x0010)
36#define TIMER0_VAL (TIMER_VIRT_BASE + 0x0014)
37#define TIMER1_RELOAD (TIMER_VIRT_BASE + 0x0018)
38#define TIMER1_VAL (TIMER_VIRT_BASE + 0x001c)
39
40
41/*
42 * Clocksource handling.
43 */
44static cycle_t orion_clksrc_read(void)
45{
46 return 0xffffffff - readl(TIMER0_VAL);
47}
48
49static struct clocksource orion_clksrc = {
50 .name = "orion_clocksource",
51 .shift = 20,
52 .rating = 300,
53 .read = orion_clksrc_read,
54 .mask = CLOCKSOURCE_MASK(32),
55 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
56};
57
58
59
60/*
61 * Clockevent handling.
62 */
63static int
64orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
65{
66 unsigned long flags;
67 u32 u;
68
69 if (delta == 0)
70 return -ETIME;
71
72 local_irq_save(flags);
73
74 /*
75 * Clear and enable clockevent timer interrupt.
76 */
77 writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
78
79 u = readl(BRIDGE_MASK);
80 u |= BRIDGE_INT_TIMER1;
81 writel(u, BRIDGE_MASK);
82
83 /*
84 * Setup new clockevent timer value.
85 */
86 writel(delta, TIMER1_VAL);
87
88 /*
89 * Enable the timer.
90 */
91 u = readl(TIMER_CTRL);
92 u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
93 writel(u, TIMER_CTRL);
94
95 local_irq_restore(flags);
96
97 return 0;
98}
99
100static void
101orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
102{
103 unsigned long flags;
104 u32 u;
105
106 local_irq_save(flags);
107 if (mode == CLOCK_EVT_MODE_PERIODIC) {
108 /*
109 * Setup timer to fire at 1/HZ intervals.
110 */
111 writel(ticks_per_jiffy - 1, TIMER1_RELOAD);
112 writel(ticks_per_jiffy - 1, TIMER1_VAL);
113
114 /*
115 * Enable timer interrupt.
116 */
117 u = readl(BRIDGE_MASK);
118 writel(u | BRIDGE_INT_TIMER1, BRIDGE_MASK);
119
120 /*
121 * Enable timer.
122 */
123 u = readl(TIMER_CTRL);
124 writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL);
125 } else {
126 /*
127 * Disable timer.
128 */
129 u = readl(TIMER_CTRL);
130 writel(u & ~TIMER1_EN, TIMER_CTRL);
131
132 /*
133 * Disable timer interrupt.
134 */
135 u = readl(BRIDGE_MASK);
136 writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK);
137
138 /*
139 * ACK pending timer interrupt.
140 */
141 writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
142
143 }
144 local_irq_restore(flags);
145}
146
147static struct clock_event_device orion_clkevt = {
148 .name = "orion_tick",
149 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
150 .shift = 32,
151 .rating = 300,
152 .cpumask = CPU_MASK_CPU0,
153 .set_next_event = orion_clkevt_next_event,
154 .set_mode = orion_clkevt_mode,
155};
156
157static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
158{
159 /*
160 * ACK timer interrupt and call event handler.
161 */
162 writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
163 orion_clkevt.event_handler(&orion_clkevt);
164
165 return IRQ_HANDLED;
166}
167
168static struct irqaction orion_timer_irq = {
169 .name = "orion_tick",
170 .flags = IRQF_DISABLED | IRQF_TIMER,
171 .handler = orion_timer_interrupt
172};
173
174void __init orion_time_init(unsigned int irq, unsigned int tclk)
175{
176 u32 u;
177
178 ticks_per_jiffy = (tclk + HZ/2) / HZ;
179
180
181 /*
182 * Setup free-running clocksource timer (interrupts
183 * disabled.)
184 */
185 writel(0xffffffff, TIMER0_VAL);
186 writel(0xffffffff, TIMER0_RELOAD);
187 u = readl(BRIDGE_MASK);
188 writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK);
189 u = readl(TIMER_CTRL);
190 writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL);
191 orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift);
192 clocksource_register(&orion_clksrc);
193
194
195 /*
196 * Setup clockevent timer (interrupt-driven.)
197 */
198 setup_irq(irq, &orion_timer_irq);
199 orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
200 orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt);
201 orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt);
202 clockevents_register_device(&orion_clkevt);
203}