aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/plat-omap
diff options
context:
space:
mode:
authorTony Lindgren <tony@atomide.com>2012-11-09 17:54:17 -0500
committerTony Lindgren <tony@atomide.com>2012-11-09 17:54:17 -0500
commitf56f52e02a9c3da4bc2cc6eb9ddcf5602ea44b37 (patch)
treea9ce4f46ea3b2e516698b2c3817e40414a8bbf51 /arch/arm/plat-omap
parent84fbd2b8c8da49b4e53fcb484a1564a9b5da61b3 (diff)
parent6ba54ab4a49bbad736b0254aa6bdf0cb83013815 (diff)
Merge branch 'omap-for-v3.8/cleanup-headers-prepare-multiplatform-v3' into omap-for-v3.8/dt
Conflicts: arch/arm/plat-omap/dmtimer.c Resolved as suggested by Jon Hunter.
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r--arch/arm/plat-omap/Makefile4
-rw-r--r--arch/arm/plat-omap/clock.c544
-rw-r--r--arch/arm/plat-omap/common.c48
-rw-r--r--arch/arm/plat-omap/counter_32k.c3
-rw-r--r--arch/arm/plat-omap/debug-devices.c3
-rw-r--r--arch/arm/plat-omap/debug-leds.c23
-rw-r--r--arch/arm/plat-omap/dma.c132
-rw-r--r--arch/arm/plat-omap/dmtimer.c20
-rw-r--r--arch/arm/plat-omap/fb.c62
-rw-r--r--arch/arm/plat-omap/i2c.c155
-rw-r--r--arch/arm/plat-omap/include/plat-omap/dma-omap.h (renamed from arch/arm/plat-omap/include/plat/dma.h)201
-rw-r--r--arch/arm/plat-omap/include/plat/clkdev_omap.h51
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h309
-rw-r--r--arch/arm/plat-omap/include/plat/common.h42
-rw-r--r--arch/arm/plat-omap/include/plat/counter-32k.h1
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h468
-rw-r--r--arch/arm/plat-omap/include/plat/debug-devices.h2
-rw-r--r--arch/arm/plat-omap/include/plat/dma-44xx.h147
-rw-r--r--arch/arm/plat-omap/include/plat/dmtimer.h2
-rw-r--r--arch/arm/plat-omap/include/plat/fpga.h193
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc.h190
-rw-r--r--arch/arm/plat-omap/include/plat/i2c.h30
-rw-r--r--arch/arm/plat-omap/include/plat/led.h24
-rw-r--r--arch/arm/plat-omap/include/plat/menelaus.h49
-rw-r--r--arch/arm/plat-omap/include/plat/mmc.h188
-rw-r--r--arch/arm/plat-omap/include/plat/multi.h120
-rw-r--r--arch/arm/plat-omap/include/plat/omap-pm.h352
-rw-r--r--arch/arm/plat-omap/include/plat/omap-secure.h14
-rw-r--r--arch/arm/plat-omap/include/plat/omap_device.h176
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h676
-rw-r--r--arch/arm/plat-omap/include/plat/sdrc.h164
-rw-r--r--arch/arm/plat-omap/include/plat/serial.h132
-rw-r--r--arch/arm/plat-omap/include/plat/sram.h97
-rw-r--r--arch/arm/plat-omap/include/plat/tc.h89
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h204
-rw-r--r--arch/arm/plat-omap/include/plat/usb.h179
-rw-r--r--arch/arm/plat-omap/include/plat/vrfb.h66
-rw-r--r--arch/arm/plat-omap/omap-pm-noop.c372
-rw-r--r--arch/arm/plat-omap/omap_device.c1278
-rw-r--r--arch/arm/plat-omap/sram.c366
-rw-r--r--arch/arm/plat-omap/sram.h6
41 files changed, 233 insertions, 6949 deletions
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index dacaee009a4e..8d885848600a 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -3,13 +3,12 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := common.o sram.o clock.o dma.o fb.o counter_32k.o 6obj-y := sram.o dma.o fb.o counter_32k.o
7obj-m := 7obj-m :=
8obj-n := 8obj-n :=
9obj- := 9obj- :=
10 10
11# omap_device support (OMAP2+ only at the moment) 11# omap_device support (OMAP2+ only at the moment)
12obj-$(CONFIG_ARCH_OMAP2PLUS) += omap_device.o
13 12
14obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o 13obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
15obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o 14obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
@@ -20,4 +19,3 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y)
20# OMAP mailbox framework 19# OMAP mailbox framework
21obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o 20obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o
22 21
23obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
deleted file mode 100644
index 9d7ac20ef8f9..000000000000
--- a/arch/arm/plat-omap/clock.c
+++ /dev/null
@@ -1,544 +0,0 @@
1/*
2 * linux/arch/arm/plat-omap/clock.c
3 *
4 * Copyright (C) 2004 - 2008 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 *
7 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/list.h>
16#include <linux/errno.h>
17#include <linux/export.h>
18#include <linux/err.h>
19#include <linux/string.h>
20#include <linux/clk.h>
21#include <linux/mutex.h>
22#include <linux/cpufreq.h>
23#include <linux/io.h>
24
25#include <plat/clock.h>
26
27static LIST_HEAD(clocks);
28static DEFINE_MUTEX(clocks_mutex);
29static DEFINE_SPINLOCK(clockfw_lock);
30
31static struct clk_functions *arch_clock;
32
33/*
34 * Standard clock functions defined in include/linux/clk.h
35 */
36
37int clk_enable(struct clk *clk)
38{
39 unsigned long flags;
40 int ret;
41
42 if (clk == NULL || IS_ERR(clk))
43 return -EINVAL;
44
45 if (!arch_clock || !arch_clock->clk_enable)
46 return -EINVAL;
47
48 spin_lock_irqsave(&clockfw_lock, flags);
49 ret = arch_clock->clk_enable(clk);
50 spin_unlock_irqrestore(&clockfw_lock, flags);
51
52 return ret;
53}
54EXPORT_SYMBOL(clk_enable);
55
56void clk_disable(struct clk *clk)
57{
58 unsigned long flags;
59
60 if (clk == NULL || IS_ERR(clk))
61 return;
62
63 if (!arch_clock || !arch_clock->clk_disable)
64 return;
65
66 spin_lock_irqsave(&clockfw_lock, flags);
67 if (clk->usecount == 0) {
68 pr_err("Trying disable clock %s with 0 usecount\n",
69 clk->name);
70 WARN_ON(1);
71 goto out;
72 }
73
74 arch_clock->clk_disable(clk);
75
76out:
77 spin_unlock_irqrestore(&clockfw_lock, flags);
78}
79EXPORT_SYMBOL(clk_disable);
80
81unsigned long clk_get_rate(struct clk *clk)
82{
83 unsigned long flags;
84 unsigned long ret;
85
86 if (clk == NULL || IS_ERR(clk))
87 return 0;
88
89 spin_lock_irqsave(&clockfw_lock, flags);
90 ret = clk->rate;
91 spin_unlock_irqrestore(&clockfw_lock, flags);
92
93 return ret;
94}
95EXPORT_SYMBOL(clk_get_rate);
96
97/*
98 * Optional clock functions defined in include/linux/clk.h
99 */
100
101long clk_round_rate(struct clk *clk, unsigned long rate)
102{
103 unsigned long flags;
104 long ret;
105
106 if (clk == NULL || IS_ERR(clk))
107 return 0;
108
109 if (!arch_clock || !arch_clock->clk_round_rate)
110 return 0;
111
112 spin_lock_irqsave(&clockfw_lock, flags);
113 ret = arch_clock->clk_round_rate(clk, rate);
114 spin_unlock_irqrestore(&clockfw_lock, flags);
115
116 return ret;
117}
118EXPORT_SYMBOL(clk_round_rate);
119
120int clk_set_rate(struct clk *clk, unsigned long rate)
121{
122 unsigned long flags;
123 int ret = -EINVAL;
124
125 if (clk == NULL || IS_ERR(clk))
126 return ret;
127
128 if (!arch_clock || !arch_clock->clk_set_rate)
129 return ret;
130
131 spin_lock_irqsave(&clockfw_lock, flags);
132 ret = arch_clock->clk_set_rate(clk, rate);
133 if (ret == 0)
134 propagate_rate(clk);
135 spin_unlock_irqrestore(&clockfw_lock, flags);
136
137 return ret;
138}
139EXPORT_SYMBOL(clk_set_rate);
140
141int clk_set_parent(struct clk *clk, struct clk *parent)
142{
143 unsigned long flags;
144 int ret = -EINVAL;
145
146 if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
147 return ret;
148
149 if (!arch_clock || !arch_clock->clk_set_parent)
150 return ret;
151
152 spin_lock_irqsave(&clockfw_lock, flags);
153 if (clk->usecount == 0) {
154 ret = arch_clock->clk_set_parent(clk, parent);
155 if (ret == 0)
156 propagate_rate(clk);
157 } else
158 ret = -EBUSY;
159 spin_unlock_irqrestore(&clockfw_lock, flags);
160
161 return ret;
162}
163EXPORT_SYMBOL(clk_set_parent);
164
165struct clk *clk_get_parent(struct clk *clk)
166{
167 return clk->parent;
168}
169EXPORT_SYMBOL(clk_get_parent);
170
171/*
172 * OMAP specific clock functions shared between omap1 and omap2
173 */
174
175int __initdata mpurate;
176
177/*
178 * By default we use the rate set by the bootloader.
179 * You can override this with mpurate= cmdline option.
180 */
181static int __init omap_clk_setup(char *str)
182{
183 get_option(&str, &mpurate);
184
185 if (!mpurate)
186 return 1;
187
188 if (mpurate < 1000)
189 mpurate *= 1000000;
190
191 return 1;
192}
193__setup("mpurate=", omap_clk_setup);
194
195/* Used for clocks that always have same value as the parent clock */
196unsigned long followparent_recalc(struct clk *clk)
197{
198 return clk->parent->rate;
199}
200
201/*
202 * Used for clocks that have the same value as the parent clock,
203 * divided by some factor
204 */
205unsigned long omap_fixed_divisor_recalc(struct clk *clk)
206{
207 WARN_ON(!clk->fixed_div);
208
209 return clk->parent->rate / clk->fixed_div;
210}
211
212void clk_reparent(struct clk *child, struct clk *parent)
213{
214 list_del_init(&child->sibling);
215 if (parent)
216 list_add(&child->sibling, &parent->children);
217 child->parent = parent;
218
219 /* now do the debugfs renaming to reattach the child
220 to the proper parent */
221}
222
223/* Propagate rate to children */
224void propagate_rate(struct clk *tclk)
225{
226 struct clk *clkp;
227
228 list_for_each_entry(clkp, &tclk->children, sibling) {
229 if (clkp->recalc)
230 clkp->rate = clkp->recalc(clkp);
231 propagate_rate(clkp);
232 }
233}
234
235static LIST_HEAD(root_clks);
236
237/**
238 * recalculate_root_clocks - recalculate and propagate all root clocks
239 *
240 * Recalculates all root clocks (clocks with no parent), which if the
241 * clock's .recalc is set correctly, should also propagate their rates.
242 * Called at init.
243 */
244void recalculate_root_clocks(void)
245{
246 struct clk *clkp;
247
248 list_for_each_entry(clkp, &root_clks, sibling) {
249 if (clkp->recalc)
250 clkp->rate = clkp->recalc(clkp);
251 propagate_rate(clkp);
252 }
253}
254
255/**
256 * clk_preinit - initialize any fields in the struct clk before clk init
257 * @clk: struct clk * to initialize
258 *
259 * Initialize any struct clk fields needed before normal clk initialization
260 * can run. No return value.
261 */
262void clk_preinit(struct clk *clk)
263{
264 INIT_LIST_HEAD(&clk->children);
265}
266
267int clk_register(struct clk *clk)
268{
269 if (clk == NULL || IS_ERR(clk))
270 return -EINVAL;
271
272 /*
273 * trap out already registered clocks
274 */
275 if (clk->node.next || clk->node.prev)
276 return 0;
277
278 mutex_lock(&clocks_mutex);
279 if (clk->parent)
280 list_add(&clk->sibling, &clk->parent->children);
281 else
282 list_add(&clk->sibling, &root_clks);
283
284 list_add(&clk->node, &clocks);
285 if (clk->init)
286 clk->init(clk);
287 mutex_unlock(&clocks_mutex);
288
289 return 0;
290}
291EXPORT_SYMBOL(clk_register);
292
293void clk_unregister(struct clk *clk)
294{
295 if (clk == NULL || IS_ERR(clk))
296 return;
297
298 mutex_lock(&clocks_mutex);
299 list_del(&clk->sibling);
300 list_del(&clk->node);
301 mutex_unlock(&clocks_mutex);
302}
303EXPORT_SYMBOL(clk_unregister);
304
305void clk_enable_init_clocks(void)
306{
307 struct clk *clkp;
308
309 list_for_each_entry(clkp, &clocks, node) {
310 if (clkp->flags & ENABLE_ON_INIT)
311 clk_enable(clkp);
312 }
313}
314
315int omap_clk_enable_autoidle_all(void)
316{
317 struct clk *c;
318 unsigned long flags;
319
320 spin_lock_irqsave(&clockfw_lock, flags);
321
322 list_for_each_entry(c, &clocks, node)
323 if (c->ops->allow_idle)
324 c->ops->allow_idle(c);
325
326 spin_unlock_irqrestore(&clockfw_lock, flags);
327
328 return 0;
329}
330
331int omap_clk_disable_autoidle_all(void)
332{
333 struct clk *c;
334 unsigned long flags;
335
336 spin_lock_irqsave(&clockfw_lock, flags);
337
338 list_for_each_entry(c, &clocks, node)
339 if (c->ops->deny_idle)
340 c->ops->deny_idle(c);
341
342 spin_unlock_irqrestore(&clockfw_lock, flags);
343
344 return 0;
345}
346
347/*
348 * Low level helpers
349 */
350static int clkll_enable_null(struct clk *clk)
351{
352 return 0;
353}
354
355static void clkll_disable_null(struct clk *clk)
356{
357}
358
359const struct clkops clkops_null = {
360 .enable = clkll_enable_null,
361 .disable = clkll_disable_null,
362};
363
364/*
365 * Dummy clock
366 *
367 * Used for clock aliases that are needed on some OMAPs, but not others
368 */
369struct clk dummy_ck = {
370 .name = "dummy",
371 .ops = &clkops_null,
372};
373
374/*
375 *
376 */
377
378#ifdef CONFIG_OMAP_RESET_CLOCKS
379/*
380 * Disable any unused clocks left on by the bootloader
381 */
382static int __init clk_disable_unused(void)
383{
384 struct clk *ck;
385 unsigned long flags;
386
387 if (!arch_clock || !arch_clock->clk_disable_unused)
388 return 0;
389
390 pr_info("clock: disabling unused clocks to save power\n");
391
392 spin_lock_irqsave(&clockfw_lock, flags);
393 list_for_each_entry(ck, &clocks, node) {
394 if (ck->ops == &clkops_null)
395 continue;
396
397 if (ck->usecount > 0 || !ck->enable_reg)
398 continue;
399
400 arch_clock->clk_disable_unused(ck);
401 }
402 spin_unlock_irqrestore(&clockfw_lock, flags);
403
404 return 0;
405}
406late_initcall(clk_disable_unused);
407late_initcall(omap_clk_enable_autoidle_all);
408#endif
409
410int __init clk_init(struct clk_functions * custom_clocks)
411{
412 if (!custom_clocks) {
413 pr_err("No custom clock functions registered\n");
414 BUG();
415 }
416
417 arch_clock = custom_clocks;
418
419 return 0;
420}
421
422#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
423/*
424 * debugfs support to trace clock tree hierarchy and attributes
425 */
426
427#include <linux/debugfs.h>
428#include <linux/seq_file.h>
429
430static struct dentry *clk_debugfs_root;
431
432static int clk_dbg_show_summary(struct seq_file *s, void *unused)
433{
434 struct clk *c;
435 struct clk *pa;
436
437 mutex_lock(&clocks_mutex);
438 seq_printf(s, "%-30s %-30s %-10s %s\n",
439 "clock-name", "parent-name", "rate", "use-count");
440
441 list_for_each_entry(c, &clocks, node) {
442 pa = c->parent;
443 seq_printf(s, "%-30s %-30s %-10lu %d\n",
444 c->name, pa ? pa->name : "none", c->rate, c->usecount);
445 }
446 mutex_unlock(&clocks_mutex);
447
448 return 0;
449}
450
451static int clk_dbg_open(struct inode *inode, struct file *file)
452{
453 return single_open(file, clk_dbg_show_summary, inode->i_private);
454}
455
456static const struct file_operations debug_clock_fops = {
457 .open = clk_dbg_open,
458 .read = seq_read,
459 .llseek = seq_lseek,
460 .release = single_release,
461};
462
463static int clk_debugfs_register_one(struct clk *c)
464{
465 int err;
466 struct dentry *d;
467 struct clk *pa = c->parent;
468
469 d = debugfs_create_dir(c->name, pa ? pa->dent : clk_debugfs_root);
470 if (!d)
471 return -ENOMEM;
472 c->dent = d;
473
474 d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount);
475 if (!d) {
476 err = -ENOMEM;
477 goto err_out;
478 }
479 d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
480 if (!d) {
481 err = -ENOMEM;
482 goto err_out;
483 }
484 d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
485 if (!d) {
486 err = -ENOMEM;
487 goto err_out;
488 }
489 return 0;
490
491err_out:
492 debugfs_remove_recursive(c->dent);
493 return err;
494}
495
496static int clk_debugfs_register(struct clk *c)
497{
498 int err;
499 struct clk *pa = c->parent;
500
501 if (pa && !pa->dent) {
502 err = clk_debugfs_register(pa);
503 if (err)
504 return err;
505 }
506
507 if (!c->dent) {
508 err = clk_debugfs_register_one(c);
509 if (err)
510 return err;
511 }
512 return 0;
513}
514
515static int __init clk_debugfs_init(void)
516{
517 struct clk *c;
518 struct dentry *d;
519 int err;
520
521 d = debugfs_create_dir("clock", NULL);
522 if (!d)
523 return -ENOMEM;
524 clk_debugfs_root = d;
525
526 list_for_each_entry(c, &clocks, node) {
527 err = clk_debugfs_register(c);
528 if (err)
529 goto err_out;
530 }
531
532 d = debugfs_create_file("summary", S_IRUGO,
533 d, NULL, &debug_clock_fops);
534 if (!d)
535 return -ENOMEM;
536
537 return 0;
538err_out:
539 debugfs_remove_recursive(clk_debugfs_root);
540 return err;
541}
542late_initcall(clk_debugfs_init);
543
544#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
deleted file mode 100644
index 111315a69354..000000000000
--- a/arch/arm/plat-omap/common.c
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * linux/arch/arm/plat-omap/common.c
3 *
4 * Code common to all OMAP machines.
5 * The file is created by Tony Lindgren <tony@atomide.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/dma-mapping.h>
18
19#include <plat/common.h>
20#include <plat/vram.h>
21#include <linux/platform_data/dsp-omap.h>
22#include <plat/dma.h>
23
24#include <plat/omap-secure.h>
25
26void __init omap_reserve(void)
27{
28 omap_vram_reserve_sdram_memblock();
29 omap_dsp_reserve_sdram_memblock();
30 omap_secure_ram_reserve_memblock();
31 omap_barrier_reserve_memblock();
32}
33
34void __init omap_init_consistent_dma_size(void)
35{
36#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
37 init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20);
38#endif
39}
40
41/*
42 * Stub function for OMAP2 so that common files
43 * continue to build when custom builds are used
44 */
45int __weak omap_secure_ram_reserve_memblock(void)
46{
47 return 0;
48}
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 87ba8dd0d791..f3771cdb9838 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -22,9 +22,6 @@
22#include <asm/mach/time.h> 22#include <asm/mach/time.h>
23#include <asm/sched_clock.h> 23#include <asm/sched_clock.h>
24 24
25#include <plat/common.h>
26#include <plat/clock.h>
27
28/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */ 25/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
29#define OMAP2_32KSYNCNT_REV_OFF 0x0 26#define OMAP2_32KSYNCNT_REV_OFF 0x0
30#define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30) 27#define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30)
diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c
index 5a4678edd65a..a609e2161817 100644
--- a/arch/arm/plat-omap/debug-devices.c
+++ b/arch/arm/plat-omap/debug-devices.c
@@ -15,8 +15,7 @@
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/smc91x.h> 16#include <linux/smc91x.h>
17 17
18#include <mach/hardware.h> 18#include <plat/debug-devices.h>
19#include "../mach-omap2/debug-devices.h"
20 19
21/* Many OMAP development platforms reuse the same "debug board"; these 20/* Many OMAP development platforms reuse the same "debug board"; these
22 * platforms include H2, H3, H4, and Perseus2. 21 * platforms include H2, H3, H4, and Perseus2.
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index ea29bbe8e5cf..c43ea21f33b4 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -17,16 +17,33 @@
17#include <linux/platform_data/gpio-omap.h> 17#include <linux/platform_data/gpio-omap.h>
18#include <linux/slab.h> 18#include <linux/slab.h>
19 19
20#include <mach/hardware.h>
21#include <asm/mach-types.h> 20#include <asm/mach-types.h>
22 21
23#include <plat/fpga.h>
24
25/* Many OMAP development platforms reuse the same "debug board"; these 22/* Many OMAP development platforms reuse the same "debug board"; these
26 * platforms include H2, H3, H4, and Perseus2. There are 16 LEDs on the 23 * platforms include H2, H3, H4, and Perseus2. There are 16 LEDs on the
27 * debug board (all green), accessed through FPGA registers. 24 * debug board (all green), accessed through FPGA registers.
28 */ 25 */
29 26
27/* NOTE: most boards don't have a static mapping for the FPGA ... */
28struct h2p2_dbg_fpga {
29 /* offset 0x00 */
30 u16 smc91x[8];
31 /* offset 0x10 */
32 u16 fpga_rev;
33 u16 board_rev;
34 u16 gpio_outputs;
35 u16 leds;
36 /* offset 0x18 */
37 u16 misc_inputs;
38 u16 lan_status;
39 u16 lan_reset;
40 u16 reserved0;
41 /* offset 0x20 */
42 u16 ps2_data;
43 u16 ps2_ctrl;
44 /* plus also 4 rs232 ports ... */
45};
46
30static struct h2p2_dbg_fpga __iomem *fpga; 47static struct h2p2_dbg_fpga __iomem *fpga;
31 48
32static u16 fpga_led_state; 49static u16 fpga_led_state;
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index c76ed8bff838..c288b76f8e6c 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -36,9 +36,7 @@
36#include <linux/slab.h> 36#include <linux/slab.h>
37#include <linux/delay.h> 37#include <linux/delay.h>
38 38
39#include <plat/cpu.h> 39#include <plat-omap/dma-omap.h>
40#include <plat/dma.h>
41#include <plat/tc.h>
42 40
43/* 41/*
44 * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA 42 * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
@@ -175,12 +173,13 @@ static inline void set_gdma_dev(int req, int dev)
175#define omap_writel(val, reg) do {} while (0) 173#define omap_writel(val, reg) do {} while (0)
176#endif 174#endif
177 175
176#ifdef CONFIG_ARCH_OMAP1
178void omap_set_dma_priority(int lch, int dst_port, int priority) 177void omap_set_dma_priority(int lch, int dst_port, int priority)
179{ 178{
180 unsigned long reg; 179 unsigned long reg;
181 u32 l; 180 u32 l;
182 181
183 if (cpu_class_is_omap1()) { 182 if (dma_omap1()) {
184 switch (dst_port) { 183 switch (dst_port) {
185 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */ 184 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
186 reg = OMAP_TC_OCPT1_PRIOR; 185 reg = OMAP_TC_OCPT1_PRIOR;
@@ -203,18 +202,22 @@ void omap_set_dma_priority(int lch, int dst_port, int priority)
203 l |= (priority & 0xf) << 8; 202 l |= (priority & 0xf) << 8;
204 omap_writel(l, reg); 203 omap_writel(l, reg);
205 } 204 }
205}
206#endif
206 207
207 if (cpu_class_is_omap2()) { 208#ifdef CONFIG_ARCH_OMAP2PLUS
208 u32 ccr; 209void omap_set_dma_priority(int lch, int dst_port, int priority)
210{
211 u32 ccr;
209 212
210 ccr = p->dma_read(CCR, lch); 213 ccr = p->dma_read(CCR, lch);
211 if (priority) 214 if (priority)
212 ccr |= (1 << 6); 215 ccr |= (1 << 6);
213 else 216 else
214 ccr &= ~(1 << 6); 217 ccr &= ~(1 << 6);
215 p->dma_write(ccr, CCR, lch); 218 p->dma_write(ccr, CCR, lch);
216 }
217} 219}
220#endif
218EXPORT_SYMBOL(omap_set_dma_priority); 221EXPORT_SYMBOL(omap_set_dma_priority);
219 222
220void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, 223void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
@@ -228,7 +231,7 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
228 l |= data_type; 231 l |= data_type;
229 p->dma_write(l, CSDP, lch); 232 p->dma_write(l, CSDP, lch);
230 233
231 if (cpu_class_is_omap1()) { 234 if (dma_omap1()) {
232 u16 ccr; 235 u16 ccr;
233 236
234 ccr = p->dma_read(CCR, lch); 237 ccr = p->dma_read(CCR, lch);
@@ -244,7 +247,7 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
244 p->dma_write(ccr, CCR2, lch); 247 p->dma_write(ccr, CCR2, lch);
245 } 248 }
246 249
247 if (cpu_class_is_omap2() && dma_trigger) { 250 if (dma_omap2plus() && dma_trigger) {
248 u32 val; 251 u32 val;
249 252
250 val = p->dma_read(CCR, lch); 253 val = p->dma_read(CCR, lch);
@@ -284,7 +287,7 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
284{ 287{
285 BUG_ON(omap_dma_in_1510_mode()); 288 BUG_ON(omap_dma_in_1510_mode());
286 289
287 if (cpu_class_is_omap1()) { 290 if (dma_omap1()) {
288 u16 w; 291 u16 w;
289 292
290 w = p->dma_read(CCR2, lch); 293 w = p->dma_read(CCR2, lch);
@@ -314,7 +317,7 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
314 p->dma_write(w, LCH_CTRL, lch); 317 p->dma_write(w, LCH_CTRL, lch);
315 } 318 }
316 319
317 if (cpu_class_is_omap2()) { 320 if (dma_omap2plus()) {
318 u32 val; 321 u32 val;
319 322
320 val = p->dma_read(CCR, lch); 323 val = p->dma_read(CCR, lch);
@@ -342,7 +345,7 @@ EXPORT_SYMBOL(omap_set_dma_color_mode);
342 345
343void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) 346void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
344{ 347{
345 if (cpu_class_is_omap2()) { 348 if (dma_omap2plus()) {
346 u32 csdp; 349 u32 csdp;
347 350
348 csdp = p->dma_read(CSDP, lch); 351 csdp = p->dma_read(CSDP, lch);
@@ -355,7 +358,7 @@ EXPORT_SYMBOL(omap_set_dma_write_mode);
355 358
356void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode) 359void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
357{ 360{
358 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) { 361 if (dma_omap1() && !dma_omap15xx()) {
359 u32 l; 362 u32 l;
360 363
361 l = p->dma_read(LCH_CTRL, lch); 364 l = p->dma_read(LCH_CTRL, lch);
@@ -373,7 +376,7 @@ void omap_set_dma_src_params(int lch, int src_port, int src_amode,
373{ 376{
374 u32 l; 377 u32 l;
375 378
376 if (cpu_class_is_omap1()) { 379 if (dma_omap1()) {
377 u16 w; 380 u16 w;
378 381
379 w = p->dma_read(CSDP, lch); 382 w = p->dma_read(CSDP, lch);
@@ -415,7 +418,7 @@ EXPORT_SYMBOL(omap_set_dma_params);
415 418
416void omap_set_dma_src_index(int lch, int eidx, int fidx) 419void omap_set_dma_src_index(int lch, int eidx, int fidx)
417{ 420{
418 if (cpu_class_is_omap2()) 421 if (dma_omap2plus())
419 return; 422 return;
420 423
421 p->dma_write(eidx, CSEI, lch); 424 p->dma_write(eidx, CSEI, lch);
@@ -447,13 +450,13 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
447 case OMAP_DMA_DATA_BURST_DIS: 450 case OMAP_DMA_DATA_BURST_DIS:
448 break; 451 break;
449 case OMAP_DMA_DATA_BURST_4: 452 case OMAP_DMA_DATA_BURST_4:
450 if (cpu_class_is_omap2()) 453 if (dma_omap2plus())
451 burst = 0x1; 454 burst = 0x1;
452 else 455 else
453 burst = 0x2; 456 burst = 0x2;
454 break; 457 break;
455 case OMAP_DMA_DATA_BURST_8: 458 case OMAP_DMA_DATA_BURST_8:
456 if (cpu_class_is_omap2()) { 459 if (dma_omap2plus()) {
457 burst = 0x2; 460 burst = 0x2;
458 break; 461 break;
459 } 462 }
@@ -463,7 +466,7 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
463 * fall through 466 * fall through
464 */ 467 */
465 case OMAP_DMA_DATA_BURST_16: 468 case OMAP_DMA_DATA_BURST_16:
466 if (cpu_class_is_omap2()) { 469 if (dma_omap2plus()) {
467 burst = 0x3; 470 burst = 0x3;
468 break; 471 break;
469 } 472 }
@@ -487,7 +490,7 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
487{ 490{
488 u32 l; 491 u32 l;
489 492
490 if (cpu_class_is_omap1()) { 493 if (dma_omap1()) {
491 l = p->dma_read(CSDP, lch); 494 l = p->dma_read(CSDP, lch);
492 l &= ~(0x1f << 9); 495 l &= ~(0x1f << 9);
493 l |= dest_port << 9; 496 l |= dest_port << 9;
@@ -508,7 +511,7 @@ EXPORT_SYMBOL(omap_set_dma_dest_params);
508 511
509void omap_set_dma_dest_index(int lch, int eidx, int fidx) 512void omap_set_dma_dest_index(int lch, int eidx, int fidx)
510{ 513{
511 if (cpu_class_is_omap2()) 514 if (dma_omap2plus())
512 return; 515 return;
513 516
514 p->dma_write(eidx, CDEI, lch); 517 p->dma_write(eidx, CDEI, lch);
@@ -540,19 +543,19 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
540 case OMAP_DMA_DATA_BURST_DIS: 543 case OMAP_DMA_DATA_BURST_DIS:
541 break; 544 break;
542 case OMAP_DMA_DATA_BURST_4: 545 case OMAP_DMA_DATA_BURST_4:
543 if (cpu_class_is_omap2()) 546 if (dma_omap2plus())
544 burst = 0x1; 547 burst = 0x1;
545 else 548 else
546 burst = 0x2; 549 burst = 0x2;
547 break; 550 break;
548 case OMAP_DMA_DATA_BURST_8: 551 case OMAP_DMA_DATA_BURST_8:
549 if (cpu_class_is_omap2()) 552 if (dma_omap2plus())
550 burst = 0x2; 553 burst = 0x2;
551 else 554 else
552 burst = 0x3; 555 burst = 0x3;
553 break; 556 break;
554 case OMAP_DMA_DATA_BURST_16: 557 case OMAP_DMA_DATA_BURST_16:
555 if (cpu_class_is_omap2()) { 558 if (dma_omap2plus()) {
556 burst = 0x3; 559 burst = 0x3;
557 break; 560 break;
558 } 561 }
@@ -573,7 +576,7 @@ EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
573static inline void omap_enable_channel_irq(int lch) 576static inline void omap_enable_channel_irq(int lch)
574{ 577{
575 /* Clear CSR */ 578 /* Clear CSR */
576 if (cpu_class_is_omap1()) 579 if (dma_omap1())
577 p->dma_read(CSR, lch); 580 p->dma_read(CSR, lch);
578 else 581 else
579 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); 582 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
@@ -587,7 +590,7 @@ static inline void omap_disable_channel_irq(int lch)
587 /* disable channel interrupts */ 590 /* disable channel interrupts */
588 p->dma_write(0, CICR, lch); 591 p->dma_write(0, CICR, lch);
589 /* Clear CSR */ 592 /* Clear CSR */
590 if (cpu_class_is_omap1()) 593 if (dma_omap1())
591 p->dma_read(CSR, lch); 594 p->dma_read(CSR, lch);
592 else 595 else
593 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); 596 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
@@ -611,7 +614,7 @@ static inline void enable_lnk(int lch)
611 614
612 l = p->dma_read(CLNK_CTRL, lch); 615 l = p->dma_read(CLNK_CTRL, lch);
613 616
614 if (cpu_class_is_omap1()) 617 if (dma_omap1())
615 l &= ~(1 << 14); 618 l &= ~(1 << 14);
616 619
617 /* Set the ENABLE_LNK bits */ 620 /* Set the ENABLE_LNK bits */
@@ -619,7 +622,7 @@ static inline void enable_lnk(int lch)
619 l = dma_chan[lch].next_lch | (1 << 15); 622 l = dma_chan[lch].next_lch | (1 << 15);
620 623
621#ifndef CONFIG_ARCH_OMAP1 624#ifndef CONFIG_ARCH_OMAP1
622 if (cpu_class_is_omap2()) 625 if (dma_omap2plus())
623 if (dma_chan[lch].next_linked_ch != -1) 626 if (dma_chan[lch].next_linked_ch != -1)
624 l = dma_chan[lch].next_linked_ch | (1 << 15); 627 l = dma_chan[lch].next_linked_ch | (1 << 15);
625#endif 628#endif
@@ -636,12 +639,12 @@ static inline void disable_lnk(int lch)
636 /* Disable interrupts */ 639 /* Disable interrupts */
637 omap_disable_channel_irq(lch); 640 omap_disable_channel_irq(lch);
638 641
639 if (cpu_class_is_omap1()) { 642 if (dma_omap1()) {
640 /* Set the STOP_LNK bit */ 643 /* Set the STOP_LNK bit */
641 l |= 1 << 14; 644 l |= 1 << 14;
642 } 645 }
643 646
644 if (cpu_class_is_omap2()) { 647 if (dma_omap2plus()) {
645 /* Clear the ENABLE_LNK bit */ 648 /* Clear the ENABLE_LNK bit */
646 l &= ~(1 << 15); 649 l &= ~(1 << 15);
647 } 650 }
@@ -655,7 +658,7 @@ static inline void omap2_enable_irq_lch(int lch)
655 u32 val; 658 u32 val;
656 unsigned long flags; 659 unsigned long flags;
657 660
658 if (!cpu_class_is_omap2()) 661 if (dma_omap1())
659 return; 662 return;
660 663
661 spin_lock_irqsave(&dma_chan_lock, flags); 664 spin_lock_irqsave(&dma_chan_lock, flags);
@@ -673,7 +676,7 @@ static inline void omap2_disable_irq_lch(int lch)
673 u32 val; 676 u32 val;
674 unsigned long flags; 677 unsigned long flags;
675 678
676 if (!cpu_class_is_omap2()) 679 if (dma_omap1())
677 return; 680 return;
678 681
679 spin_lock_irqsave(&dma_chan_lock, flags); 682 spin_lock_irqsave(&dma_chan_lock, flags);
@@ -712,7 +715,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
712 if (p->clear_lch_regs) 715 if (p->clear_lch_regs)
713 p->clear_lch_regs(free_ch); 716 p->clear_lch_regs(free_ch);
714 717
715 if (cpu_class_is_omap2()) 718 if (dma_omap2plus())
716 omap_clear_dma(free_ch); 719 omap_clear_dma(free_ch);
717 720
718 spin_unlock_irqrestore(&dma_chan_lock, flags); 721 spin_unlock_irqrestore(&dma_chan_lock, flags);
@@ -723,7 +726,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
723 chan->flags = 0; 726 chan->flags = 0;
724 727
725#ifndef CONFIG_ARCH_OMAP1 728#ifndef CONFIG_ARCH_OMAP1
726 if (cpu_class_is_omap2()) { 729 if (dma_omap2plus()) {
727 chan->chain_id = -1; 730 chan->chain_id = -1;
728 chan->next_linked_ch = -1; 731 chan->next_linked_ch = -1;
729 } 732 }
@@ -731,13 +734,13 @@ int omap_request_dma(int dev_id, const char *dev_name,
731 734
732 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; 735 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
733 736
734 if (cpu_class_is_omap1()) 737 if (dma_omap1())
735 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ; 738 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
736 else if (cpu_class_is_omap2()) 739 else if (dma_omap2plus())
737 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ | 740 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
738 OMAP2_DMA_TRANS_ERR_IRQ; 741 OMAP2_DMA_TRANS_ERR_IRQ;
739 742
740 if (cpu_is_omap16xx()) { 743 if (dma_omap16xx()) {
741 /* If the sync device is set, configure it dynamically. */ 744 /* If the sync device is set, configure it dynamically. */
742 if (dev_id != 0) { 745 if (dev_id != 0) {
743 set_gdma_dev(free_ch + 1, dev_id); 746 set_gdma_dev(free_ch + 1, dev_id);
@@ -748,11 +751,11 @@ int omap_request_dma(int dev_id, const char *dev_name,
748 * id. 751 * id.
749 */ 752 */
750 p->dma_write(dev_id | (1 << 10), CCR, free_ch); 753 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
751 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) { 754 } else if (dma_omap1()) {
752 p->dma_write(dev_id, CCR, free_ch); 755 p->dma_write(dev_id, CCR, free_ch);
753 } 756 }
754 757
755 if (cpu_class_is_omap2()) { 758 if (dma_omap2plus()) {
756 omap_enable_channel_irq(free_ch); 759 omap_enable_channel_irq(free_ch);
757 omap2_enable_irq_lch(free_ch); 760 omap2_enable_irq_lch(free_ch);
758 } 761 }
@@ -774,7 +777,7 @@ void omap_free_dma(int lch)
774 } 777 }
775 778
776 /* Disable interrupt for logical channel */ 779 /* Disable interrupt for logical channel */
777 if (cpu_class_is_omap2()) 780 if (dma_omap2plus())
778 omap2_disable_irq_lch(lch); 781 omap2_disable_irq_lch(lch);
779 782
780 /* Disable all DMA interrupts for the channel. */ 783 /* Disable all DMA interrupts for the channel. */
@@ -784,7 +787,7 @@ void omap_free_dma(int lch)
784 p->dma_write(0, CCR, lch); 787 p->dma_write(0, CCR, lch);
785 788
786 /* Clear registers */ 789 /* Clear registers */
787 if (cpu_class_is_omap2()) 790 if (dma_omap2plus())
788 omap_clear_dma(lch); 791 omap_clear_dma(lch);
789 792
790 spin_lock_irqsave(&dma_chan_lock, flags); 793 spin_lock_irqsave(&dma_chan_lock, flags);
@@ -810,7 +813,7 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
810{ 813{
811 u32 reg; 814 u32 reg;
812 815
813 if (!cpu_class_is_omap2()) { 816 if (dma_omap1()) {
814 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__); 817 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
815 return; 818 return;
816 } 819 }
@@ -849,7 +852,7 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio,
849 } 852 }
850 l = p->dma_read(CCR, lch); 853 l = p->dma_read(CCR, lch);
851 l &= ~((1 << 6) | (1 << 26)); 854 l &= ~((1 << 6) | (1 << 26));
852 if (cpu_class_is_omap2() && !cpu_is_omap242x()) 855 if (d->dev_caps & IS_RW_PRIORITY)
853 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); 856 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
854 else 857 else
855 l |= ((read_prio & 0x1) << 6); 858 l |= ((read_prio & 0x1) << 6);
@@ -882,7 +885,7 @@ void omap_start_dma(int lch)
882 * The CPC/CDAC register needs to be initialized to zero 885 * The CPC/CDAC register needs to be initialized to zero
883 * before starting dma transfer. 886 * before starting dma transfer.
884 */ 887 */
885 if (cpu_is_omap15xx()) 888 if (dma_omap15xx())
886 p->dma_write(0, CPC, lch); 889 p->dma_write(0, CPC, lch);
887 else 890 else
888 p->dma_write(0, CDAC, lch); 891 p->dma_write(0, CDAC, lch);
@@ -1045,7 +1048,7 @@ dma_addr_t omap_get_dma_src_pos(int lch)
1045{ 1048{
1046 dma_addr_t offset = 0; 1049 dma_addr_t offset = 0;
1047 1050
1048 if (cpu_is_omap15xx()) 1051 if (dma_omap15xx())
1049 offset = p->dma_read(CPC, lch); 1052 offset = p->dma_read(CPC, lch);
1050 else 1053 else
1051 offset = p->dma_read(CSAC, lch); 1054 offset = p->dma_read(CSAC, lch);
@@ -1053,7 +1056,7 @@ dma_addr_t omap_get_dma_src_pos(int lch)
1053 if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0) 1056 if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
1054 offset = p->dma_read(CSAC, lch); 1057 offset = p->dma_read(CSAC, lch);
1055 1058
1056 if (!cpu_is_omap15xx()) { 1059 if (!dma_omap15xx()) {
1057 /* 1060 /*
1058 * CDAC == 0 indicates that the DMA transfer on the channel has 1061 * CDAC == 0 indicates that the DMA transfer on the channel has
1059 * not been started (no data has been transferred so far). 1062 * not been started (no data has been transferred so far).
@@ -1065,7 +1068,7 @@ dma_addr_t omap_get_dma_src_pos(int lch)
1065 offset = p->dma_read(CSSA, lch); 1068 offset = p->dma_read(CSSA, lch);
1066 } 1069 }
1067 1070
1068 if (cpu_class_is_omap1()) 1071 if (dma_omap1())
1069 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000); 1072 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
1070 1073
1071 return offset; 1074 return offset;
@@ -1084,7 +1087,7 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
1084{ 1087{
1085 dma_addr_t offset = 0; 1088 dma_addr_t offset = 0;
1086 1089
1087 if (cpu_is_omap15xx()) 1090 if (dma_omap15xx())
1088 offset = p->dma_read(CPC, lch); 1091 offset = p->dma_read(CPC, lch);
1089 else 1092 else
1090 offset = p->dma_read(CDAC, lch); 1093 offset = p->dma_read(CDAC, lch);
@@ -1093,7 +1096,7 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
1093 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is 1096 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1094 * read before the DMA controller finished disabling the channel. 1097 * read before the DMA controller finished disabling the channel.
1095 */ 1098 */
1096 if (!cpu_is_omap15xx() && offset == 0) { 1099 if (!dma_omap15xx() && offset == 0) {
1097 offset = p->dma_read(CDAC, lch); 1100 offset = p->dma_read(CDAC, lch);
1098 /* 1101 /*
1099 * CDAC == 0 indicates that the DMA transfer on the channel has 1102 * CDAC == 0 indicates that the DMA transfer on the channel has
@@ -1104,7 +1107,7 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
1104 offset = p->dma_read(CDSA, lch); 1107 offset = p->dma_read(CDSA, lch);
1105 } 1108 }
1106 1109
1107 if (cpu_class_is_omap1()) 1110 if (dma_omap1())
1108 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000); 1111 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1109 1112
1110 return offset; 1113 return offset;
@@ -1121,7 +1124,7 @@ int omap_dma_running(void)
1121{ 1124{
1122 int lch; 1125 int lch;
1123 1126
1124 if (cpu_class_is_omap1()) 1127 if (dma_omap1())
1125 if (omap_lcd_dma_running()) 1128 if (omap_lcd_dma_running())
1126 return 1; 1129 return 1;
1127 1130
@@ -2024,7 +2027,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
2024 dma_chan = d->chan; 2027 dma_chan = d->chan;
2025 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE; 2028 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
2026 2029
2027 if (cpu_class_is_omap2()) { 2030 if (dma_omap2plus()) {
2028 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) * 2031 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2029 dma_lch_count, GFP_KERNEL); 2032 dma_lch_count, GFP_KERNEL);
2030 if (!dma_linked_lch) { 2033 if (!dma_linked_lch) {
@@ -2036,7 +2039,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
2036 spin_lock_init(&dma_chan_lock); 2039 spin_lock_init(&dma_chan_lock);
2037 for (ch = 0; ch < dma_chan_count; ch++) { 2040 for (ch = 0; ch < dma_chan_count; ch++) {
2038 omap_clear_dma(ch); 2041 omap_clear_dma(ch);
2039 if (cpu_class_is_omap2()) 2042 if (dma_omap2plus())
2040 omap2_disable_irq_lch(ch); 2043 omap2_disable_irq_lch(ch);
2041 2044
2042 dma_chan[ch].dev_id = -1; 2045 dma_chan[ch].dev_id = -1;
@@ -2045,7 +2048,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
2045 if (ch >= 6 && enable_1510_mode) 2048 if (ch >= 6 && enable_1510_mode)
2046 continue; 2049 continue;
2047 2050
2048 if (cpu_class_is_omap1()) { 2051 if (dma_omap1()) {
2049 /* 2052 /*
2050 * request_irq() doesn't like dev_id (ie. ch) being 2053 * request_irq() doesn't like dev_id (ie. ch) being
2051 * zero, so we have to kludge around this. 2054 * zero, so we have to kludge around this.
@@ -2070,11 +2073,11 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
2070 } 2073 }
2071 } 2074 }
2072 2075
2073 if (cpu_class_is_omap2() && !cpu_is_omap242x()) 2076 if (d->dev_caps & IS_RW_PRIORITY)
2074 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, 2077 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2075 DMA_DEFAULT_FIFO_DEPTH, 0); 2078 DMA_DEFAULT_FIFO_DEPTH, 0);
2076 2079
2077 if (cpu_class_is_omap2()) { 2080 if (dma_omap2plus()) {
2078 strcpy(irq_name, "0"); 2081 strcpy(irq_name, "0");
2079 dma_irq = platform_get_irq_byname(pdev, irq_name); 2082 dma_irq = platform_get_irq_byname(pdev, irq_name);
2080 if (dma_irq < 0) { 2083 if (dma_irq < 0) {
@@ -2089,9 +2092,8 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
2089 } 2092 }
2090 } 2093 }
2091 2094
2092 /* reserve dma channels 0 and 1 in high security devices */ 2095 /* reserve dma channels 0 and 1 in high security devices on 34xx */
2093 if (cpu_is_omap34xx() && 2096 if (d->dev_caps & HS_CHANNELS_RESERVED) {
2094 (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
2095 pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n"); 2097 pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
2096 dma_chan[0].dev_id = 0; 2098 dma_chan[0].dev_id = 0;
2097 dma_chan[1].dev_id = 1; 2099 dma_chan[1].dev_id = 1;
@@ -2118,7 +2120,7 @@ static int __devexit omap_system_dma_remove(struct platform_device *pdev)
2118{ 2120{
2119 int dma_irq; 2121 int dma_irq;
2120 2122
2121 if (cpu_class_is_omap2()) { 2123 if (dma_omap2plus()) {
2122 char irq_name[4]; 2124 char irq_name[4];
2123 strcpy(irq_name, "0"); 2125 strcpy(irq_name, "0");
2124 dma_irq = platform_get_irq_byname(pdev, irq_name); 2126 dma_irq = platform_get_irq_byname(pdev, irq_name);
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index b09e55632f4b..9dca23e4d6b0 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -44,9 +44,6 @@
44#include <linux/of_device.h> 44#include <linux/of_device.h>
45 45
46#include <plat/dmtimer.h> 46#include <plat/dmtimer.h>
47#include <plat/omap-pm.h>
48
49#include <mach/hardware.h>
50 47
51static u32 omap_reserved_systimers; 48static u32 omap_reserved_systimers;
52static LIST_HEAD(omap_timer_list); 49static LIST_HEAD(omap_timer_list);
@@ -332,7 +329,7 @@ int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
332EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq); 329EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
333 330
334#if defined(CONFIG_ARCH_OMAP1) 331#if defined(CONFIG_ARCH_OMAP1)
335 332#include <mach/hardware.h>
336/** 333/**
337 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR 334 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
338 * @inputmask: current value of idlect mask 335 * @inputmask: current value of idlect mask
@@ -409,7 +406,8 @@ int omap_dm_timer_start(struct omap_dm_timer *timer)
409 omap_dm_timer_enable(timer); 406 omap_dm_timer_enable(timer);
410 407
411 if (!(timer->capability & OMAP_TIMER_ALWON)) { 408 if (!(timer->capability & OMAP_TIMER_ALWON)) {
412 if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) != 409 if (timer->get_context_loss_count &&
410 timer->get_context_loss_count(&timer->pdev->dev) !=
413 timer->ctx_loss_count) 411 timer->ctx_loss_count)
414 omap_timer_restore_context(timer); 412 omap_timer_restore_context(timer);
415 } 413 }
@@ -438,9 +436,11 @@ int omap_dm_timer_stop(struct omap_dm_timer *timer)
438 436
439 __omap_dm_timer_stop(timer, timer->posted, rate); 437 __omap_dm_timer_stop(timer, timer->posted, rate);
440 438
441 if (!(timer->capability & OMAP_TIMER_ALWON)) 439 if (!(timer->capability & OMAP_TIMER_ALWON)) {
442 timer->ctx_loss_count = 440 if (timer->get_context_loss_count)
443 omap_pm_get_dev_context_loss_count(&timer->pdev->dev); 441 timer->ctx_loss_count =
442 timer->get_context_loss_count(&timer->pdev->dev);
443 }
444 444
445 /* 445 /*
446 * Since the register values are computed and written within 446 * Since the register values are computed and written within
@@ -556,7 +556,8 @@ int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
556 omap_dm_timer_enable(timer); 556 omap_dm_timer_enable(timer);
557 557
558 if (!(timer->capability & OMAP_TIMER_ALWON)) { 558 if (!(timer->capability & OMAP_TIMER_ALWON)) {
559 if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) != 559 if (timer->get_context_loss_count &&
560 timer->get_context_loss_count(&timer->pdev->dev) !=
560 timer->ctx_loss_count) 561 timer->ctx_loss_count)
561 omap_timer_restore_context(timer); 562 omap_timer_restore_context(timer);
562 } 563 }
@@ -798,6 +799,7 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
798 timer->id = pdev->id; 799 timer->id = pdev->id;
799 timer->capability = pdata->timer_capability; 800 timer->capability = pdata->timer_capability;
800 timer->reserved = omap_dm_timer_reserved_systimer(timer->id); 801 timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
802 timer->get_context_loss_count = pdata->get_context_loss_count;
801 } 803 }
802 804
803 timer->irq = irq->start; 805 timer->irq = irq->start;
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index bcbb9d5dc293..3a77b30f53d4 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -30,9 +30,69 @@
30#include <linux/io.h> 30#include <linux/io.h>
31#include <linux/omapfb.h> 31#include <linux/omapfb.h>
32 32
33#include <mach/hardware.h>
34#include <asm/mach/map.h> 33#include <asm/mach/map.h>
35 34
35#include <plat/cpu.h>
36
37#ifdef CONFIG_OMAP2_VRFB
38
39/*
40 * The first memory resource is the register region for VRFB,
41 * the rest are VRFB virtual memory areas for each VRFB context.
42 */
43
44static const struct resource omap2_vrfb_resources[] = {
45 DEFINE_RES_MEM_NAMED(0x68008000u, 0x40, "vrfb-regs"),
46 DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
47 DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
48 DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
49 DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
50};
51
52static const struct resource omap3_vrfb_resources[] = {
53 DEFINE_RES_MEM_NAMED(0x6C000180u, 0xc0, "vrfb-regs"),
54 DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
55 DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
56 DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
57 DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
58 DEFINE_RES_MEM_NAMED(0xe0000000u, 0x4000000, "vrfb-area-4"),
59 DEFINE_RES_MEM_NAMED(0xe4000000u, 0x4000000, "vrfb-area-5"),
60 DEFINE_RES_MEM_NAMED(0xe8000000u, 0x4000000, "vrfb-area-6"),
61 DEFINE_RES_MEM_NAMED(0xec000000u, 0x4000000, "vrfb-area-7"),
62 DEFINE_RES_MEM_NAMED(0xf0000000u, 0x4000000, "vrfb-area-8"),
63 DEFINE_RES_MEM_NAMED(0xf4000000u, 0x4000000, "vrfb-area-9"),
64 DEFINE_RES_MEM_NAMED(0xf8000000u, 0x4000000, "vrfb-area-10"),
65 DEFINE_RES_MEM_NAMED(0xfc000000u, 0x4000000, "vrfb-area-11"),
66};
67
68static int __init omap_init_vrfb(void)
69{
70 struct platform_device *pdev;
71 const struct resource *res;
72 unsigned int num_res;
73
74 if (cpu_is_omap24xx()) {
75 res = omap2_vrfb_resources;
76 num_res = ARRAY_SIZE(omap2_vrfb_resources);
77 } else if (cpu_is_omap34xx()) {
78 res = omap3_vrfb_resources;
79 num_res = ARRAY_SIZE(omap3_vrfb_resources);
80 } else {
81 return 0;
82 }
83
84 pdev = platform_device_register_resndata(NULL, "omapvrfb", -1,
85 res, num_res, NULL, 0);
86
87 if (IS_ERR(pdev))
88 return PTR_ERR(pdev);
89 else
90 return 0;
91}
92
93arch_initcall(omap_init_vrfb);
94#endif
95
36#if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE) 96#if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
37 97
38static bool omapfb_lcd_configured; 98static bool omapfb_lcd_configured;
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index a5683a84c6ee..f9df624d108c 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -26,160 +26,18 @@
26#include <linux/kernel.h> 26#include <linux/kernel.h>
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/i2c.h> 28#include <linux/i2c.h>
29#include <linux/i2c-omap.h>
29#include <linux/slab.h> 30#include <linux/slab.h>
30#include <linux/err.h> 31#include <linux/err.h>
31#include <linux/clk.h> 32#include <linux/clk.h>
32 33
33#include <mach/irqs.h>
34#include <plat/i2c.h> 34#include <plat/i2c.h>
35#include <plat/omap_device.h>
36 35
37#define OMAP_I2C_SIZE 0x3f
38#define OMAP1_I2C_BASE 0xfffb3800
39#define OMAP1_INT_I2C (32 + 4)
40
41static const char name[] = "omap_i2c";
42
43#define I2C_RESOURCE_BUILDER(base, irq) \
44 { \
45 .start = (base), \
46 .end = (base) + OMAP_I2C_SIZE, \
47 .flags = IORESOURCE_MEM, \
48 }, \
49 { \
50 .start = (irq), \
51 .flags = IORESOURCE_IRQ, \
52 },
53
54static struct resource i2c_resources[][2] = {
55 { I2C_RESOURCE_BUILDER(0, 0) },
56};
57
58#define I2C_DEV_BUILDER(bus_id, res, data) \
59 { \
60 .id = (bus_id), \
61 .name = name, \
62 .num_resources = ARRAY_SIZE(res), \
63 .resource = (res), \
64 .dev = { \
65 .platform_data = (data), \
66 }, \
67 }
68
69#define MAX_OMAP_I2C_HWMOD_NAME_LEN 16
70#define OMAP_I2C_MAX_CONTROLLERS 4 36#define OMAP_I2C_MAX_CONTROLLERS 4
71static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS]; 37static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS];
72static struct platform_device omap_i2c_devices[] = {
73 I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]),
74};
75 38
76#define OMAP_I2C_CMDLINE_SETUP (BIT(31)) 39#define OMAP_I2C_CMDLINE_SETUP (BIT(31))
77 40
78static int __init omap_i2c_nr_ports(void)
79{
80 int ports = 0;
81
82 if (cpu_class_is_omap1())
83 ports = 1;
84 else if (cpu_is_omap24xx())
85 ports = 2;
86 else if (cpu_is_omap34xx())
87 ports = 3;
88 else if (cpu_is_omap44xx())
89 ports = 4;
90
91 return ports;
92}
93
94static inline int omap1_i2c_add_bus(int bus_id)
95{
96 struct platform_device *pdev;
97 struct omap_i2c_bus_platform_data *pdata;
98 struct resource *res;
99
100 omap1_i2c_mux_pins(bus_id);
101
102 pdev = &omap_i2c_devices[bus_id - 1];
103 res = pdev->resource;
104 res[0].start = OMAP1_I2C_BASE;
105 res[0].end = res[0].start + OMAP_I2C_SIZE;
106 res[1].start = OMAP1_INT_I2C;
107 pdata = &i2c_pdata[bus_id - 1];
108
109 /* all OMAP1 have IP version 1 register set */
110 pdata->rev = OMAP_I2C_IP_VERSION_1;
111
112 /* all OMAP1 I2C are implemented like this */
113 pdata->flags = OMAP_I2C_FLAG_NO_FIFO |
114 OMAP_I2C_FLAG_SIMPLE_CLOCK |
115 OMAP_I2C_FLAG_16BIT_DATA_REG |
116 OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK;
117
118 /* how the cpu bus is wired up differs for 7xx only */
119
120 if (cpu_is_omap7xx())
121 pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_1;
122 else
123 pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_2;
124
125 return platform_device_register(pdev);
126}
127
128
129#ifdef CONFIG_ARCH_OMAP2PLUS
130static inline int omap2_i2c_add_bus(int bus_id)
131{
132 int l;
133 struct omap_hwmod *oh;
134 struct platform_device *pdev;
135 char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
136 struct omap_i2c_bus_platform_data *pdata;
137 struct omap_i2c_dev_attr *dev_attr;
138
139 omap2_i2c_mux_pins(bus_id);
140
141 l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);
142 WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN,
143 "String buffer overflow in I2C%d device setup\n", bus_id);
144 oh = omap_hwmod_lookup(oh_name);
145 if (!oh) {
146 pr_err("Could not look up %s\n", oh_name);
147 return -EEXIST;
148 }
149
150 pdata = &i2c_pdata[bus_id - 1];
151 /*
152 * pass the hwmod class's CPU-specific knowledge of I2C IP revision in
153 * use, and functionality implementation flags, up to the OMAP I2C
154 * driver via platform data
155 */
156 pdata->rev = oh->class->rev;
157
158 dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr;
159 pdata->flags = dev_attr->flags;
160
161 pdev = omap_device_build(name, bus_id, oh, pdata,
162 sizeof(struct omap_i2c_bus_platform_data),
163 NULL, 0, 0);
164 WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name);
165
166 return PTR_RET(pdev);
167}
168#else
169static inline int omap2_i2c_add_bus(int bus_id)
170{
171 return 0;
172}
173#endif
174
175static int __init omap_i2c_add_bus(int bus_id)
176{
177 if (cpu_class_is_omap1())
178 return omap1_i2c_add_bus(bus_id);
179 else
180 return omap2_i2c_add_bus(bus_id);
181}
182
183/** 41/**
184 * omap_i2c_bus_setup - Process command line options for the I2C bus speed 42 * omap_i2c_bus_setup - Process command line options for the I2C bus speed
185 * @str: String of options 43 * @str: String of options
@@ -193,12 +51,11 @@ static int __init omap_i2c_add_bus(int bus_id)
193 */ 51 */
194static int __init omap_i2c_bus_setup(char *str) 52static int __init omap_i2c_bus_setup(char *str)
195{ 53{
196 int ports;
197 int ints[3]; 54 int ints[3];
198 55
199 ports = omap_i2c_nr_ports();
200 get_options(str, 3, ints); 56 get_options(str, 3, ints);
201 if (ints[0] < 2 || ints[1] < 1 || ints[1] > ports) 57 if (ints[0] < 2 || ints[1] < 1 ||
58 ints[1] > OMAP_I2C_MAX_CONTROLLERS)
202 return 0; 59 return 0;
203 i2c_pdata[ints[1] - 1].clkrate = ints[2]; 60 i2c_pdata[ints[1] - 1].clkrate = ints[2];
204 i2c_pdata[ints[1] - 1].clkrate |= OMAP_I2C_CMDLINE_SETUP; 61 i2c_pdata[ints[1] - 1].clkrate |= OMAP_I2C_CMDLINE_SETUP;
@@ -218,7 +75,7 @@ static int __init omap_register_i2c_bus_cmdline(void)
218 for (i = 0; i < ARRAY_SIZE(i2c_pdata); i++) 75 for (i = 0; i < ARRAY_SIZE(i2c_pdata); i++)
219 if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) { 76 if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) {
220 i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP; 77 i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
221 err = omap_i2c_add_bus(i + 1); 78 err = omap_i2c_add_bus(&i2c_pdata[i], i + 1);
222 if (err) 79 if (err)
223 goto out; 80 goto out;
224 } 81 }
@@ -243,7 +100,7 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
243{ 100{
244 int err; 101 int err;
245 102
246 BUG_ON(bus_id < 1 || bus_id > omap_i2c_nr_ports()); 103 BUG_ON(bus_id < 1 || bus_id > OMAP_I2C_MAX_CONTROLLERS);
247 104
248 if (info) { 105 if (info) {
249 err = i2c_register_board_info(bus_id, info, len); 106 err = i2c_register_board_info(bus_id, info, len);
@@ -256,5 +113,5 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
256 113
257 i2c_pdata[bus_id - 1].clkrate &= ~OMAP_I2C_CMDLINE_SETUP; 114 i2c_pdata[bus_id - 1].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
258 115
259 return omap_i2c_add_bus(bus_id); 116 return omap_i2c_add_bus(&i2c_pdata[bus_id - 1], bus_id);
260} 117}
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat-omap/dma-omap.h
index 0a87b052f8f7..6f506ba9e453 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat-omap/dma-omap.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * arch/arm/plat-omap/include/mach/dma.h 2 * OMAP DMA handling defines and function
3 * 3 *
4 * Copyright (C) 2003 Nokia Corporation 4 * Copyright (C) 2003 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com> 5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
@@ -23,187 +23,8 @@
23 23
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25 25
26/*
27 * TODO: These dma channel defines should go away once all
28 * the omap drivers hwmod adapted.
29 */
30
31/* Move omap4 specific defines to dma-44xx.h */
32#include "dma-44xx.h"
33
34#define INT_DMA_LCD 25 26#define INT_DMA_LCD 25
35 27
36/* DMA channels for omap1 */
37#define OMAP_DMA_NO_DEVICE 0
38#define OMAP_DMA_MCSI1_TX 1
39#define OMAP_DMA_MCSI1_RX 2
40#define OMAP_DMA_I2C_RX 3
41#define OMAP_DMA_I2C_TX 4
42#define OMAP_DMA_EXT_NDMA_REQ 5
43#define OMAP_DMA_EXT_NDMA_REQ2 6
44#define OMAP_DMA_UWIRE_TX 7
45#define OMAP_DMA_MCBSP1_TX 8
46#define OMAP_DMA_MCBSP1_RX 9
47#define OMAP_DMA_MCBSP3_TX 10
48#define OMAP_DMA_MCBSP3_RX 11
49#define OMAP_DMA_UART1_TX 12
50#define OMAP_DMA_UART1_RX 13
51#define OMAP_DMA_UART2_TX 14
52#define OMAP_DMA_UART2_RX 15
53#define OMAP_DMA_MCBSP2_TX 16
54#define OMAP_DMA_MCBSP2_RX 17
55#define OMAP_DMA_UART3_TX 18
56#define OMAP_DMA_UART3_RX 19
57#define OMAP_DMA_CAMERA_IF_RX 20
58#define OMAP_DMA_MMC_TX 21
59#define OMAP_DMA_MMC_RX 22
60#define OMAP_DMA_NAND 23
61#define OMAP_DMA_IRQ_LCD_LINE 24
62#define OMAP_DMA_MEMORY_STICK 25
63#define OMAP_DMA_USB_W2FC_RX0 26
64#define OMAP_DMA_USB_W2FC_RX1 27
65#define OMAP_DMA_USB_W2FC_RX2 28
66#define OMAP_DMA_USB_W2FC_TX0 29
67#define OMAP_DMA_USB_W2FC_TX1 30
68#define OMAP_DMA_USB_W2FC_TX2 31
69
70/* These are only for 1610 */
71#define OMAP_DMA_CRYPTO_DES_IN 32
72#define OMAP_DMA_SPI_TX 33
73#define OMAP_DMA_SPI_RX 34
74#define OMAP_DMA_CRYPTO_HASH 35
75#define OMAP_DMA_CCP_ATTN 36
76#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
77#define OMAP_DMA_CMT_APE_TX_CHAN_0 38
78#define OMAP_DMA_CMT_APE_RV_CHAN_0 39
79#define OMAP_DMA_CMT_APE_TX_CHAN_1 40
80#define OMAP_DMA_CMT_APE_RV_CHAN_1 41
81#define OMAP_DMA_CMT_APE_TX_CHAN_2 42
82#define OMAP_DMA_CMT_APE_RV_CHAN_2 43
83#define OMAP_DMA_CMT_APE_TX_CHAN_3 44
84#define OMAP_DMA_CMT_APE_RV_CHAN_3 45
85#define OMAP_DMA_CMT_APE_TX_CHAN_4 46
86#define OMAP_DMA_CMT_APE_RV_CHAN_4 47
87#define OMAP_DMA_CMT_APE_TX_CHAN_5 48
88#define OMAP_DMA_CMT_APE_RV_CHAN_5 49
89#define OMAP_DMA_CMT_APE_TX_CHAN_6 50
90#define OMAP_DMA_CMT_APE_RV_CHAN_6 51
91#define OMAP_DMA_CMT_APE_TX_CHAN_7 52
92#define OMAP_DMA_CMT_APE_RV_CHAN_7 53
93#define OMAP_DMA_MMC2_TX 54
94#define OMAP_DMA_MMC2_RX 55
95#define OMAP_DMA_CRYPTO_DES_OUT 56
96
97/* DMA channels for 24xx */
98#define OMAP24XX_DMA_NO_DEVICE 0
99#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */
100#define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */
101#define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */
102#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
103#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
104#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
105#define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */
106#define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */
107#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */
108#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */
109#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */
110#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
111#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
112#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
113#define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */
114#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */
115#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */
116#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */
117#define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */
118#define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */
119#define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
120#define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */
121#define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */
122#define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */
123#define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */
124#define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */
125#define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */
126#define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */
127#define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */
128#define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
129#define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
130#define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */
131#define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */
132#define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */
133#define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */
134#define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */
135#define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */
136#define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
137#define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
138#define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */
139#define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */
140#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */
141#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */
142#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */
143#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
144#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
145#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
146#define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */
147#define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */
148#define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */
149#define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */
150#define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
151#define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
152#define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
153#define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
154#define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
155#define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
156#define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
157#define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
158#define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
159#define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
160#define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
161#define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
162#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */
163#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */
164#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */
165#define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */
166#define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */
167#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */
168#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */
169#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */
170#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */
171#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */
172#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */
173#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */
174#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */
175#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */
176#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */
177#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */
178#define OMAP24XX_DMA_MS 63 /* S_DMA_62 */
179#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */
180#define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */
181#define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */
182#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */
183#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */
184#define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */
185#define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */
186#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */
187#define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
188#define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
189#define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */
190#define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */
191#define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */
192#define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */
193#define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */
194#define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */
195#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
196#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */
197
198#define OMAP36XX_DMA_UART4_TX 81 /* S_DMA_80 */
199#define OMAP36XX_DMA_UART4_RX 82 /* S_DMA_81 */
200
201/* Only for AM35xx */
202#define AM35XX_DMA_UART4_TX 54
203#define AM35XX_DMA_UART4_RX 55
204
205/*----------------------------------------------------------------------------*/
206
207#define OMAP1_DMA_TOUT_IRQ (1 << 0) 28#define OMAP1_DMA_TOUT_IRQ (1 << 0)
208#define OMAP_DMA_DROP_IRQ (1 << 1) 29#define OMAP_DMA_DROP_IRQ (1 << 1)
209#define OMAP_DMA_HALF_IRQ (1 << 2) 30#define OMAP_DMA_HALF_IRQ (1 << 2)
@@ -309,10 +130,12 @@
309#define SRC_PORT BIT(0x7) 130#define SRC_PORT BIT(0x7)
310#define DST_PORT BIT(0x8) 131#define DST_PORT BIT(0x8)
311#define SRC_INDEX BIT(0x9) 132#define SRC_INDEX BIT(0x9)
312#define DST_INDEX BIT(0xA) 133#define DST_INDEX BIT(0xa)
313#define IS_BURST_ONLY4 BIT(0xB) 134#define IS_BURST_ONLY4 BIT(0xb)
314#define CLEAR_CSR_ON_READ BIT(0xC) 135#define CLEAR_CSR_ON_READ BIT(0xc)
315#define IS_WORD_16 BIT(0xD) 136#define IS_WORD_16 BIT(0xd)
137#define ENABLE_16XX_MODE BIT(0xe)
138#define HS_CHANNELS_RESERVED BIT(0xf)
316 139
317/* Defines for DMA Capabilities */ 140/* Defines for DMA Capabilities */
318#define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18) 141#define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18)
@@ -449,7 +272,15 @@ struct omap_system_dma_plat_info {
449 u32 (*dma_read)(int reg, int lch); 272 u32 (*dma_read)(int reg, int lch);
450}; 273};
451 274
452extern void __init omap_init_consistent_dma_size(void); 275#ifdef CONFIG_ARCH_OMAP2PLUS
276#define dma_omap2plus() 1
277#else
278#define dma_omap2plus() 0
279#endif
280#define dma_omap1() (!dma_omap2plus())
281#define dma_omap15xx() ((dma_omap1() && (d->dev_caps & ENABLE_1510_MODE)))
282#define dma_omap16xx() ((dma_omap1() && (d->dev_caps & ENABLE_16XX_MODE)))
283
453extern void omap_set_dma_priority(int lch, int dst_port, int priority); 284extern void omap_set_dma_priority(int lch, int dst_port, int priority);
454extern int omap_request_dma(int dev_id, const char *dev_name, 285extern int omap_request_dma(int dev_id, const char *dev_name,
455 void (*callback)(int lch, u16 ch_status, void *data), 286 void (*callback)(int lch, u16 ch_status, void *data),
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
deleted file mode 100644
index 025d85a3ee86..000000000000
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * clkdev <-> OMAP integration
3 *
4 * Russell King <linux@arm.linux.org.uk>
5 *
6 */
7
8#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
9#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
10
11#include <linux/clkdev.h>
12
13struct omap_clk {
14 u16 cpu;
15 struct clk_lookup lk;
16};
17
18#define CLK(dev, con, ck, cp) \
19 { \
20 .cpu = cp, \
21 .lk = { \
22 .dev_id = dev, \
23 .con_id = con, \
24 .clk = ck, \
25 }, \
26 }
27
28/* Platform flags for the clkdev-OMAP integration code */
29#define CK_310 (1 << 0)
30#define CK_7XX (1 << 1) /* 7xx, 850 */
31#define CK_1510 (1 << 2)
32#define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */
33#define CK_242X (1 << 4)
34#define CK_243X (1 << 5) /* 243x, 253x */
35#define CK_3430ES1 (1 << 6) /* 34xxES1 only */
36#define CK_3430ES2PLUS (1 << 7) /* 34xxES2, ES3, non-Sitara 35xx only */
37#define CK_AM35XX (1 << 9) /* Sitara AM35xx */
38#define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */
39#define CK_443X (1 << 11)
40#define CK_TI816X (1 << 12)
41#define CK_446X (1 << 13)
42#define CK_AM33XX (1 << 14) /* AM33xx specific clocks */
43#define CK_1710 (1 << 15) /* 1710 extra for rate selection */
44
45
46#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
47#define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX)
48
49
50#endif
51
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
deleted file mode 100644
index e2e2d045e428..000000000000
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ /dev/null
@@ -1,309 +0,0 @@
1/*
2 * OMAP clock: data structure definitions, function prototypes, shared macros
3 *
4 * Copyright (C) 2004-2005, 2008-2010 Nokia Corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ARCH_ARM_OMAP_CLOCK_H
14#define __ARCH_ARM_OMAP_CLOCK_H
15
16#include <linux/list.h>
17
18struct module;
19struct clk;
20struct clockdomain;
21
22/* Temporary, needed during the common clock framework conversion */
23#define __clk_get_name(clk) (clk->name)
24#define __clk_get_parent(clk) (clk->parent)
25#define __clk_get_rate(clk) (clk->rate)
26
27/**
28 * struct clkops - some clock function pointers
29 * @enable: fn ptr that enables the current clock in hardware
30 * @disable: fn ptr that enables the current clock in hardware
31 * @find_idlest: function returning the IDLEST register for the clock's IP blk
32 * @find_companion: function returning the "companion" clk reg for the clock
33 * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
34 * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
35 *
36 * A "companion" clk is an accompanying clock to the one being queried
37 * that must be enabled for the IP module connected to the clock to
38 * become accessible by the hardware. Neither @find_idlest nor
39 * @find_companion should be needed; that information is IP
40 * block-specific; the hwmod code has been created to handle this, but
41 * until hwmod data is ready and drivers have been converted to use PM
42 * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
43 * @find_companion must, unfortunately, remain.
44 */
45struct clkops {
46 int (*enable)(struct clk *);
47 void (*disable)(struct clk *);
48 void (*find_idlest)(struct clk *, void __iomem **,
49 u8 *, u8 *);
50 void (*find_companion)(struct clk *, void __iomem **,
51 u8 *);
52 void (*allow_idle)(struct clk *);
53 void (*deny_idle)(struct clk *);
54};
55
56#ifdef CONFIG_ARCH_OMAP2PLUS
57
58/* struct clksel_rate.flags possibilities */
59#define RATE_IN_242X (1 << 0)
60#define RATE_IN_243X (1 << 1)
61#define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */
62#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
63#define RATE_IN_36XX (1 << 4)
64#define RATE_IN_4430 (1 << 5)
65#define RATE_IN_TI816X (1 << 6)
66#define RATE_IN_4460 (1 << 7)
67#define RATE_IN_AM33XX (1 << 8)
68#define RATE_IN_TI814X (1 << 9)
69
70#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
71#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
72#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
73#define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460)
74
75/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
76#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
77
78
79/**
80 * struct clksel_rate - register bitfield values corresponding to clk divisors
81 * @val: register bitfield value (shifted to bit 0)
82 * @div: clock divisor corresponding to @val
83 * @flags: (see "struct clksel_rate.flags possibilities" above)
84 *
85 * @val should match the value of a read from struct clk.clksel_reg
86 * AND'ed with struct clk.clksel_mask, shifted right to bit 0.
87 *
88 * @div is the divisor that should be applied to the parent clock's rate
89 * to produce the current clock's rate.
90 */
91struct clksel_rate {
92 u32 val;
93 u8 div;
94 u16 flags;
95};
96
97/**
98 * struct clksel - available parent clocks, and a pointer to their divisors
99 * @parent: struct clk * to a possible parent clock
100 * @rates: available divisors for this parent clock
101 *
102 * A struct clksel is always associated with one or more struct clks
103 * and one or more struct clksel_rates.
104 */
105struct clksel {
106 struct clk *parent;
107 const struct clksel_rate *rates;
108};
109
110/**
111 * struct dpll_data - DPLL registers and integration data
112 * @mult_div1_reg: register containing the DPLL M and N bitfields
113 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
114 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
115 * @clk_bypass: struct clk pointer to the clock's bypass clock input
116 * @clk_ref: struct clk pointer to the clock's reference clock input
117 * @control_reg: register containing the DPLL mode bitfield
118 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
119 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
120 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
121 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
122 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
123 * @min_divider: minimum valid non-bypass divider value (actual)
124 * @max_divider: maximum valid non-bypass divider value (actual)
125 * @modes: possible values of @enable_mask
126 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
127 * @idlest_reg: register containing the DPLL idle status bitfield
128 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
129 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
130 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
131 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
132 * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
133 * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
134 * @flags: DPLL type/features (see below)
135 *
136 * Possible values for @flags:
137 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
138 *
139 * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
140 *
141 * XXX Some DPLLs have multiple bypass inputs, so it's not technically
142 * correct to only have one @clk_bypass pointer.
143 *
144 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
145 * @last_rounded_n) should be separated from the runtime-fixed fields
146 * and placed into a different structure, so that the runtime-fixed data
147 * can be placed into read-only space.
148 */
149struct dpll_data {
150 void __iomem *mult_div1_reg;
151 u32 mult_mask;
152 u32 div1_mask;
153 struct clk *clk_bypass;
154 struct clk *clk_ref;
155 void __iomem *control_reg;
156 u32 enable_mask;
157 unsigned long last_rounded_rate;
158 u16 last_rounded_m;
159 u16 max_multiplier;
160 u8 last_rounded_n;
161 u8 min_divider;
162 u16 max_divider;
163 u8 modes;
164 void __iomem *autoidle_reg;
165 void __iomem *idlest_reg;
166 u32 autoidle_mask;
167 u32 freqsel_mask;
168 u32 idlest_mask;
169 u32 dco_mask;
170 u32 sddiv_mask;
171 u8 auto_recal_bit;
172 u8 recal_en_bit;
173 u8 recal_st_bit;
174 u8 flags;
175};
176
177#endif
178
179/*
180 * struct clk.flags possibilities
181 *
182 * XXX document the rest of the clock flags here
183 *
184 * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
185 * bits share the same register. This flag allows the
186 * omap4_dpllmx*() code to determine which GATE_CTRL bit field
187 * should be used. This is a temporary solution - a better approach
188 * would be to associate clock type-specific data with the clock,
189 * similar to the struct dpll_data approach.
190 */
191#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
192#define CLOCK_IDLE_CONTROL (1 << 1)
193#define CLOCK_NO_IDLE_PARENT (1 << 2)
194#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
195#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
196#define CLOCK_CLKOUTX2 (1 << 5)
197
198/**
199 * struct clk - OMAP struct clk
200 * @node: list_head connecting this clock into the full clock list
201 * @ops: struct clkops * for this clock
202 * @name: the name of the clock in the hardware (used in hwmod data and debug)
203 * @parent: pointer to this clock's parent struct clk
204 * @children: list_head connecting to the child clks' @sibling list_heads
205 * @sibling: list_head connecting this clk to its parent clk's @children
206 * @rate: current clock rate
207 * @enable_reg: register to write to enable the clock (see @enable_bit)
208 * @recalc: fn ptr that returns the clock's current rate
209 * @set_rate: fn ptr that can change the clock's current rate
210 * @round_rate: fn ptr that can round the clock's current rate
211 * @init: fn ptr to do clock-specific initialization
212 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
213 * @usecount: number of users that have requested this clock to be enabled
214 * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
215 * @flags: see "struct clk.flags possibilities" above
216 * @clksel_reg: for clksel clks, register va containing src/divisor select
217 * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
218 * @clksel: for clksel clks, pointer to struct clksel for this clock
219 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
220 * @clkdm_name: clockdomain name that this clock is contained in
221 * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
222 * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
223 * @src_offset: bitshift for source selection bitfield (OMAP1 only)
224 *
225 * XXX @rate_offset, @src_offset should probably be removed and OMAP1
226 * clock code converted to use clksel.
227 *
228 * XXX @usecount is poorly named. It should be "enable_count" or
229 * something similar. "users" in the description refers to kernel
230 * code (core code or drivers) that have called clk_enable() and not
231 * yet called clk_disable(); the usecount of parent clocks is also
232 * incremented by the clock code when clk_enable() is called on child
233 * clocks and decremented by the clock code when clk_disable() is
234 * called on child clocks.
235 *
236 * XXX @clkdm, @usecount, @children, @sibling should be marked for
237 * internal use only.
238 *
239 * @children and @sibling are used to optimize parent-to-child clock
240 * tree traversals. (child-to-parent traversals use @parent.)
241 *
242 * XXX The notion of the clock's current rate probably needs to be
243 * separated from the clock's target rate.
244 */
245struct clk {
246 struct list_head node;
247 const struct clkops *ops;
248 const char *name;
249 struct clk *parent;
250 struct list_head children;
251 struct list_head sibling; /* node for children */
252 unsigned long rate;
253 void __iomem *enable_reg;
254 unsigned long (*recalc)(struct clk *);
255 int (*set_rate)(struct clk *, unsigned long);
256 long (*round_rate)(struct clk *, unsigned long);
257 void (*init)(struct clk *);
258 u8 enable_bit;
259 s8 usecount;
260 u8 fixed_div;
261 u8 flags;
262#ifdef CONFIG_ARCH_OMAP2PLUS
263 void __iomem *clksel_reg;
264 u32 clksel_mask;
265 const struct clksel *clksel;
266 struct dpll_data *dpll_data;
267 const char *clkdm_name;
268 struct clockdomain *clkdm;
269#else
270 u8 rate_offset;
271 u8 src_offset;
272#endif
273#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
274 struct dentry *dent; /* For visible tree hierarchy */
275#endif
276};
277
278struct clk_functions {
279 int (*clk_enable)(struct clk *clk);
280 void (*clk_disable)(struct clk *clk);
281 long (*clk_round_rate)(struct clk *clk, unsigned long rate);
282 int (*clk_set_rate)(struct clk *clk, unsigned long rate);
283 int (*clk_set_parent)(struct clk *clk, struct clk *parent);
284 void (*clk_allow_idle)(struct clk *clk);
285 void (*clk_deny_idle)(struct clk *clk);
286 void (*clk_disable_unused)(struct clk *clk);
287};
288
289extern int mpurate;
290
291extern int clk_init(struct clk_functions *custom_clocks);
292extern void clk_preinit(struct clk *clk);
293extern int clk_register(struct clk *clk);
294extern void clk_reparent(struct clk *child, struct clk *parent);
295extern void clk_unregister(struct clk *clk);
296extern void propagate_rate(struct clk *clk);
297extern void recalculate_root_clocks(void);
298extern unsigned long followparent_recalc(struct clk *clk);
299extern void clk_enable_init_clocks(void);
300unsigned long omap_fixed_divisor_recalc(struct clk *clk);
301extern struct clk *omap_clk_get_by_name(const char *name);
302extern int omap_clk_enable_autoidle_all(void);
303extern int omap_clk_disable_autoidle_all(void);
304
305extern const struct clkops clkops_null;
306
307extern struct clk dummy_ck;
308
309#endif
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
deleted file mode 100644
index d1cb6f527b7e..000000000000
--- a/arch/arm/plat-omap/include/plat/common.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/common.h
3 *
4 * Header for code common to all OMAP machines.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
28#define __ARCH_ARM_MACH_OMAP_COMMON_H
29
30#include <plat/i2c.h>
31#include <plat/omap_hwmod.h>
32
33extern int __init omap_init_clocksource_32k(void __iomem *vbase);
34
35extern void __init omap_check_revision(void);
36
37extern void omap_reserve(void);
38extern int omap_dss_reset(struct omap_hwmod *);
39
40void omap_sram_init(void);
41
42#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/arch/arm/plat-omap/include/plat/counter-32k.h b/arch/arm/plat-omap/include/plat/counter-32k.h
new file mode 100644
index 000000000000..da000d482ff2
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/counter-32k.h
@@ -0,0 +1 @@
int omap_init_clocksource_32k(void __iomem *vbase);
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 67da857783ce..b4516aba67ed 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -1,6 +1,4 @@
1/* 1/*
2 * arch/arm/plat-omap/include/mach/cpu.h
3 *
4 * OMAP cpu type detection 2 * OMAP cpu type detection
5 * 3 *
6 * Copyright (C) 2004, 2008 Nokia Corporation 4 * Copyright (C) 2004, 2008 Nokia Corporation
@@ -30,470 +28,12 @@
30#ifndef __ASM_ARCH_OMAP_CPU_H 28#ifndef __ASM_ARCH_OMAP_CPU_H
31#define __ASM_ARCH_OMAP_CPU_H 29#define __ASM_ARCH_OMAP_CPU_H
32 30
33#ifndef __ASSEMBLY__ 31#ifdef CONFIG_ARCH_OMAP1
34 32#include <mach/soc.h>
35#include <linux/bitops.h>
36#include <plat/multi.h>
37
38/*
39 * Omap device type i.e. EMU/HS/TST/GP/BAD
40 */
41#define OMAP2_DEVICE_TYPE_TEST 0
42#define OMAP2_DEVICE_TYPE_EMU 1
43#define OMAP2_DEVICE_TYPE_SEC 2
44#define OMAP2_DEVICE_TYPE_GP 3
45#define OMAP2_DEVICE_TYPE_BAD 4
46
47int omap_type(void);
48
49/*
50 * omap_rev bits:
51 * CPU id bits (0730, 1510, 1710, 2422...) [31:16]
52 * CPU revision (See _REV_ defined in cpu.h) [15:08]
53 * CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00]
54 */
55unsigned int omap_rev(void);
56
57/*
58 * Get the CPU revision for OMAP devices
59 */
60#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff)
61
62/*
63 * Macros to group OMAP into cpu classes.
64 * These can be used in most places.
65 * cpu_is_omap7xx(): True for OMAP730, OMAP850
66 * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310
67 * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710
68 * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
69 * cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423
70 * cpu_is_omap243x(): True for OMAP2430
71 * cpu_is_omap343x(): True for OMAP3430
72 * cpu_is_omap443x(): True for OMAP4430
73 * cpu_is_omap446x(): True for OMAP4460
74 * cpu_is_omap447x(): True for OMAP4470
75 * soc_is_omap543x(): True for OMAP5430, OMAP5432
76 */
77#define GET_OMAP_CLASS (omap_rev() & 0xff)
78
79#define IS_OMAP_CLASS(class, id) \
80static inline int is_omap ##class (void) \
81{ \
82 return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
83}
84
85#define GET_AM_CLASS ((omap_rev() >> 24) & 0xff)
86
87#define IS_AM_CLASS(class, id) \
88static inline int is_am ##class (void) \
89{ \
90 return (GET_AM_CLASS == (id)) ? 1 : 0; \
91}
92
93#define GET_TI_CLASS ((omap_rev() >> 24) & 0xff)
94
95#define IS_TI_CLASS(class, id) \
96static inline int is_ti ##class (void) \
97{ \
98 return (GET_TI_CLASS == (id)) ? 1 : 0; \
99}
100
101#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
102
103#define IS_OMAP_SUBCLASS(subclass, id) \
104static inline int is_omap ##subclass (void) \
105{ \
106 return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
107}
108
109#define IS_TI_SUBCLASS(subclass, id) \
110static inline int is_ti ##subclass (void) \
111{ \
112 return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
113}
114
115#define IS_AM_SUBCLASS(subclass, id) \
116static inline int is_am ##subclass (void) \
117{ \
118 return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
119}
120
121IS_OMAP_CLASS(7xx, 0x07)
122IS_OMAP_CLASS(15xx, 0x15)
123IS_OMAP_CLASS(16xx, 0x16)
124IS_OMAP_CLASS(24xx, 0x24)
125IS_OMAP_CLASS(34xx, 0x34)
126IS_OMAP_CLASS(44xx, 0x44)
127IS_AM_CLASS(35xx, 0x35)
128IS_OMAP_CLASS(54xx, 0x54)
129IS_AM_CLASS(33xx, 0x33)
130
131IS_TI_CLASS(81xx, 0x81)
132
133IS_OMAP_SUBCLASS(242x, 0x242)
134IS_OMAP_SUBCLASS(243x, 0x243)
135IS_OMAP_SUBCLASS(343x, 0x343)
136IS_OMAP_SUBCLASS(363x, 0x363)
137IS_OMAP_SUBCLASS(443x, 0x443)
138IS_OMAP_SUBCLASS(446x, 0x446)
139IS_OMAP_SUBCLASS(447x, 0x447)
140IS_OMAP_SUBCLASS(543x, 0x543)
141
142IS_TI_SUBCLASS(816x, 0x816)
143IS_TI_SUBCLASS(814x, 0x814)
144IS_AM_SUBCLASS(335x, 0x335)
145
146#define cpu_is_omap7xx() 0
147#define cpu_is_omap15xx() 0
148#define cpu_is_omap16xx() 0
149#define cpu_is_omap24xx() 0
150#define cpu_is_omap242x() 0
151#define cpu_is_omap243x() 0
152#define cpu_is_omap34xx() 0
153#define cpu_is_omap343x() 0
154#define cpu_is_ti81xx() 0
155#define cpu_is_ti816x() 0
156#define cpu_is_ti814x() 0
157#define soc_is_am35xx() 0
158#define soc_is_am33xx() 0
159#define soc_is_am335x() 0
160#define cpu_is_omap44xx() 0
161#define cpu_is_omap443x() 0
162#define cpu_is_omap446x() 0
163#define cpu_is_omap447x() 0
164#define soc_is_omap54xx() 0
165#define soc_is_omap543x() 0
166
167#if defined(MULTI_OMAP1)
168# if defined(CONFIG_ARCH_OMAP730)
169# undef cpu_is_omap7xx
170# define cpu_is_omap7xx() is_omap7xx()
171# endif
172# if defined(CONFIG_ARCH_OMAP850)
173# undef cpu_is_omap7xx
174# define cpu_is_omap7xx() is_omap7xx()
175# endif
176# if defined(CONFIG_ARCH_OMAP15XX)
177# undef cpu_is_omap15xx
178# define cpu_is_omap15xx() is_omap15xx()
179# endif
180# if defined(CONFIG_ARCH_OMAP16XX)
181# undef cpu_is_omap16xx
182# define cpu_is_omap16xx() is_omap16xx()
183# endif
184#else
185# if defined(CONFIG_ARCH_OMAP730)
186# undef cpu_is_omap7xx
187# define cpu_is_omap7xx() 1
188# endif
189# if defined(CONFIG_ARCH_OMAP850)
190# undef cpu_is_omap7xx
191# define cpu_is_omap7xx() 1
192# endif
193# if defined(CONFIG_ARCH_OMAP15XX)
194# undef cpu_is_omap15xx
195# define cpu_is_omap15xx() 1
196# endif
197# if defined(CONFIG_ARCH_OMAP16XX)
198# undef cpu_is_omap16xx
199# define cpu_is_omap16xx() 1
200# endif
201#endif
202
203#if defined(MULTI_OMAP2)
204# if defined(CONFIG_ARCH_OMAP2)
205# undef cpu_is_omap24xx
206# define cpu_is_omap24xx() is_omap24xx()
207# endif
208# if defined (CONFIG_SOC_OMAP2420)
209# undef cpu_is_omap242x
210# define cpu_is_omap242x() is_omap242x()
211# endif
212# if defined (CONFIG_SOC_OMAP2430)
213# undef cpu_is_omap243x
214# define cpu_is_omap243x() is_omap243x()
215# endif
216# if defined(CONFIG_ARCH_OMAP3)
217# undef cpu_is_omap34xx
218# undef cpu_is_omap343x
219# define cpu_is_omap34xx() is_omap34xx()
220# define cpu_is_omap343x() is_omap343x()
221# endif
222#else
223# if defined(CONFIG_ARCH_OMAP2)
224# undef cpu_is_omap24xx
225# define cpu_is_omap24xx() 1
226# endif
227# if defined(CONFIG_SOC_OMAP2420)
228# undef cpu_is_omap242x
229# define cpu_is_omap242x() 1
230# endif
231# if defined(CONFIG_SOC_OMAP2430)
232# undef cpu_is_omap243x
233# define cpu_is_omap243x() 1
234# endif
235# if defined(CONFIG_ARCH_OMAP3)
236# undef cpu_is_omap34xx
237# define cpu_is_omap34xx() 1
238# endif
239# if defined(CONFIG_SOC_OMAP3430)
240# undef cpu_is_omap343x
241# define cpu_is_omap343x() 1
242# endif
243#endif
244
245/*
246 * Macros to detect individual cpu types.
247 * These are only rarely needed.
248 * cpu_is_omap310(): True for OMAP310
249 * cpu_is_omap1510(): True for OMAP1510
250 * cpu_is_omap1610(): True for OMAP1610
251 * cpu_is_omap1611(): True for OMAP1611
252 * cpu_is_omap5912(): True for OMAP5912
253 * cpu_is_omap1621(): True for OMAP1621
254 * cpu_is_omap1710(): True for OMAP1710
255 * cpu_is_omap2420(): True for OMAP2420
256 * cpu_is_omap2422(): True for OMAP2422
257 * cpu_is_omap2423(): True for OMAP2423
258 * cpu_is_omap2430(): True for OMAP2430
259 * cpu_is_omap3430(): True for OMAP3430
260 */
261#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff)
262
263#define IS_OMAP_TYPE(type, id) \
264static inline int is_omap ##type (void) \
265{ \
266 return (GET_OMAP_TYPE == (id)) ? 1 : 0; \
267}
268
269IS_OMAP_TYPE(310, 0x0310)
270IS_OMAP_TYPE(1510, 0x1510)
271IS_OMAP_TYPE(1610, 0x1610)
272IS_OMAP_TYPE(1611, 0x1611)
273IS_OMAP_TYPE(5912, 0x1611)
274IS_OMAP_TYPE(1621, 0x1621)
275IS_OMAP_TYPE(1710, 0x1710)
276IS_OMAP_TYPE(2420, 0x2420)
277IS_OMAP_TYPE(2422, 0x2422)
278IS_OMAP_TYPE(2423, 0x2423)
279IS_OMAP_TYPE(2430, 0x2430)
280IS_OMAP_TYPE(3430, 0x3430)
281
282#define cpu_is_omap310() 0
283#define cpu_is_omap1510() 0
284#define cpu_is_omap1610() 0
285#define cpu_is_omap5912() 0
286#define cpu_is_omap1611() 0
287#define cpu_is_omap1621() 0
288#define cpu_is_omap1710() 0
289#define cpu_is_omap2420() 0
290#define cpu_is_omap2422() 0
291#define cpu_is_omap2423() 0
292#define cpu_is_omap2430() 0
293#define cpu_is_omap3430() 0
294#define cpu_is_omap3630() 0
295#define soc_is_omap5430() 0
296
297/*
298 * Whether we have MULTI_OMAP1 or not, we still need to distinguish
299 * between 310 vs. 1510 and 1611B/5912 vs. 1710.
300 */
301
302#if defined(CONFIG_ARCH_OMAP15XX)
303# undef cpu_is_omap310
304# undef cpu_is_omap1510
305# define cpu_is_omap310() is_omap310()
306# define cpu_is_omap1510() is_omap1510()
307#endif
308
309#if defined(CONFIG_ARCH_OMAP16XX)
310# undef cpu_is_omap1610
311# undef cpu_is_omap1611
312# undef cpu_is_omap5912
313# undef cpu_is_omap1621
314# undef cpu_is_omap1710
315# define cpu_is_omap1610() is_omap1610()
316# define cpu_is_omap1611() is_omap1611()
317# define cpu_is_omap5912() is_omap5912()
318# define cpu_is_omap1621() is_omap1621()
319# define cpu_is_omap1710() is_omap1710()
320#endif
321
322#if defined(CONFIG_ARCH_OMAP2)
323# undef cpu_is_omap2420
324# undef cpu_is_omap2422
325# undef cpu_is_omap2423
326# undef cpu_is_omap2430
327# define cpu_is_omap2420() is_omap2420()
328# define cpu_is_omap2422() is_omap2422()
329# define cpu_is_omap2423() is_omap2423()
330# define cpu_is_omap2430() is_omap2430()
331#endif
332
333#if defined(CONFIG_ARCH_OMAP3)
334# undef cpu_is_omap3430
335# undef cpu_is_ti81xx
336# undef cpu_is_ti816x
337# undef cpu_is_ti814x
338# undef soc_is_am35xx
339# define cpu_is_omap3430() is_omap3430()
340# undef cpu_is_omap3630
341# define cpu_is_omap3630() is_omap363x()
342# define cpu_is_ti81xx() is_ti81xx()
343# define cpu_is_ti816x() is_ti816x()
344# define cpu_is_ti814x() is_ti814x()
345# define soc_is_am35xx() is_am35xx()
346#endif 33#endif
347 34
348# if defined(CONFIG_SOC_AM33XX) 35#ifdef CONFIG_ARCH_OMAP2PLUS
349# undef soc_is_am33xx 36#include "../../mach-omap2/soc.h"
350# undef soc_is_am335x
351# define soc_is_am33xx() is_am33xx()
352# define soc_is_am335x() is_am335x()
353#endif 37#endif
354 38
355# if defined(CONFIG_ARCH_OMAP4)
356# undef cpu_is_omap44xx
357# undef cpu_is_omap443x
358# undef cpu_is_omap446x
359# undef cpu_is_omap447x
360# define cpu_is_omap44xx() is_omap44xx()
361# define cpu_is_omap443x() is_omap443x()
362# define cpu_is_omap446x() is_omap446x()
363# define cpu_is_omap447x() is_omap447x()
364# endif
365
366# if defined(CONFIG_SOC_OMAP5)
367# undef soc_is_omap54xx
368# undef soc_is_omap543x
369# define soc_is_omap54xx() is_omap54xx()
370# define soc_is_omap543x() is_omap543x()
371#endif
372
373/* Macros to detect if we have OMAP1 or OMAP2 */
374#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \
375 cpu_is_omap16xx())
376#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \
377 cpu_is_omap44xx() || soc_is_omap54xx() || \
378 soc_is_am33xx())
379
380/* Various silicon revisions for omap2 */
381#define OMAP242X_CLASS 0x24200024
382#define OMAP2420_REV_ES1_0 OMAP242X_CLASS
383#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (0x1 << 8))
384
385#define OMAP243X_CLASS 0x24300024
386#define OMAP2430_REV_ES1_0 OMAP243X_CLASS
387
388#define OMAP343X_CLASS 0x34300034
389#define OMAP3430_REV_ES1_0 OMAP343X_CLASS
390#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (0x1 << 8))
391#define OMAP3430_REV_ES2_1 (OMAP343X_CLASS | (0x2 << 8))
392#define OMAP3430_REV_ES3_0 (OMAP343X_CLASS | (0x3 << 8))
393#define OMAP3430_REV_ES3_1 (OMAP343X_CLASS | (0x4 << 8))
394#define OMAP3430_REV_ES3_1_2 (OMAP343X_CLASS | (0x5 << 8))
395
396#define OMAP363X_CLASS 0x36300034
397#define OMAP3630_REV_ES1_0 OMAP363X_CLASS
398#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (0x1 << 8))
399#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (0x2 << 8))
400
401#define TI816X_CLASS 0x81600034
402#define TI8168_REV_ES1_0 TI816X_CLASS
403#define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8))
404
405#define TI814X_CLASS 0x81400034
406#define TI8148_REV_ES1_0 TI814X_CLASS
407#define TI8148_REV_ES2_0 (TI814X_CLASS | (0x1 << 8))
408#define TI8148_REV_ES2_1 (TI814X_CLASS | (0x2 << 8))
409
410#define AM35XX_CLASS 0x35170034
411#define AM35XX_REV_ES1_0 AM35XX_CLASS
412#define AM35XX_REV_ES1_1 (AM35XX_CLASS | (0x1 << 8))
413
414#define AM335X_CLASS 0x33500033
415#define AM335X_REV_ES1_0 AM335X_CLASS
416
417#define OMAP443X_CLASS 0x44300044
418#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8))
419#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8))
420#define OMAP4430_REV_ES2_1 (OMAP443X_CLASS | (0x21 << 8))
421#define OMAP4430_REV_ES2_2 (OMAP443X_CLASS | (0x22 << 8))
422#define OMAP4430_REV_ES2_3 (OMAP443X_CLASS | (0x23 << 8))
423
424#define OMAP446X_CLASS 0x44600044
425#define OMAP4460_REV_ES1_0 (OMAP446X_CLASS | (0x10 << 8))
426#define OMAP4460_REV_ES1_1 (OMAP446X_CLASS | (0x11 << 8))
427
428#define OMAP447X_CLASS 0x44700044
429#define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8))
430
431#define OMAP54XX_CLASS 0x54000054
432#define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8))
433#define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
434
435void omap2xxx_check_revision(void);
436void omap3xxx_check_revision(void);
437void omap4xxx_check_revision(void);
438void omap5xxx_check_revision(void);
439void omap3xxx_check_features(void);
440void ti81xx_check_features(void);
441void omap4xxx_check_features(void);
442
443/*
444 * Runtime detection of OMAP3 features
445 *
446 * OMAP3_HAS_IO_CHAIN_CTRL: Some later members of the OMAP3 chip
447 * family have OS-level control over the I/O chain clock. This is
448 * to avoid a window during which wakeups could potentially be lost
449 * during powerdomain transitions. If this bit is set, it
450 * indicates that the chip does support OS-level control of this
451 * feature.
452 */
453extern u32 omap_features;
454
455#define OMAP3_HAS_L2CACHE BIT(0)
456#define OMAP3_HAS_IVA BIT(1)
457#define OMAP3_HAS_SGX BIT(2)
458#define OMAP3_HAS_NEON BIT(3)
459#define OMAP3_HAS_ISP BIT(4)
460#define OMAP3_HAS_192MHZ_CLK BIT(5)
461#define OMAP3_HAS_IO_WAKEUP BIT(6)
462#define OMAP3_HAS_SDRC BIT(7)
463#define OMAP3_HAS_IO_CHAIN_CTRL BIT(8)
464#define OMAP4_HAS_MPU_1GHZ BIT(9)
465#define OMAP4_HAS_MPU_1_2GHZ BIT(10)
466#define OMAP4_HAS_MPU_1_5GHZ BIT(11)
467
468
469#define OMAP3_HAS_FEATURE(feat,flag) \
470static inline unsigned int omap3_has_ ##feat(void) \
471{ \
472 return omap_features & OMAP3_HAS_ ##flag; \
473} \
474
475OMAP3_HAS_FEATURE(l2cache, L2CACHE)
476OMAP3_HAS_FEATURE(sgx, SGX)
477OMAP3_HAS_FEATURE(iva, IVA)
478OMAP3_HAS_FEATURE(neon, NEON)
479OMAP3_HAS_FEATURE(isp, ISP)
480OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
481OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
482OMAP3_HAS_FEATURE(sdrc, SDRC)
483OMAP3_HAS_FEATURE(io_chain_ctrl, IO_CHAIN_CTRL)
484
485/*
486 * Runtime detection of OMAP4 features
487 */
488#define OMAP4_HAS_FEATURE(feat, flag) \
489static inline unsigned int omap4_has_ ##feat(void) \
490{ \
491 return omap_features & OMAP4_HAS_ ##flag; \
492} \
493
494OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ)
495OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ)
496OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ)
497
498#endif /* __ASSEMBLY__ */
499#endif 39#endif
diff --git a/arch/arm/plat-omap/include/plat/debug-devices.h b/arch/arm/plat-omap/include/plat/debug-devices.h
new file mode 100644
index 000000000000..8fc4287222dd
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/debug-devices.h
@@ -0,0 +1,2 @@
1/* for TI reference platforms sharing the same debug card */
2extern int debug_card_init(u32 addr, unsigned gpio);
diff --git a/arch/arm/plat-omap/include/plat/dma-44xx.h b/arch/arm/plat-omap/include/plat/dma-44xx.h
deleted file mode 100644
index 1f767cb2f38a..000000000000
--- a/arch/arm/plat-omap/include/plat/dma-44xx.h
+++ /dev/null
@@ -1,147 +0,0 @@
1/*
2 * OMAP4 SDMA channel definitions
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Santosh Shilimkar (santosh.shilimkar@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
9 * Paul Walmsley (paul@pwsan.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#ifndef __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H
23#define __ARCH_ARM_MACH_OMAP2_OMAP44XX_DMA_H
24
25#define OMAP44XX_DMA_SYS_REQ0 2
26#define OMAP44XX_DMA_SYS_REQ1 3
27#define OMAP44XX_DMA_GPMC 4
28#define OMAP44XX_DMA_DSS_DISPC_REQ 6
29#define OMAP44XX_DMA_SYS_REQ2 7
30#define OMAP44XX_DMA_MCASP1_AXEVT 8
31#define OMAP44XX_DMA_ISS_REQ1 9
32#define OMAP44XX_DMA_ISS_REQ2 10
33#define OMAP44XX_DMA_MCASP1_AREVT 11
34#define OMAP44XX_DMA_ISS_REQ3 12
35#define OMAP44XX_DMA_ISS_REQ4 13
36#define OMAP44XX_DMA_DSS_RFBI_REQ 14
37#define OMAP44XX_DMA_SPI3_TX0 15
38#define OMAP44XX_DMA_SPI3_RX0 16
39#define OMAP44XX_DMA_MCBSP2_TX 17
40#define OMAP44XX_DMA_MCBSP2_RX 18
41#define OMAP44XX_DMA_MCBSP3_TX 19
42#define OMAP44XX_DMA_MCBSP3_RX 20
43#define OMAP44XX_DMA_C2C_SSCM_GPO0 21
44#define OMAP44XX_DMA_C2C_SSCM_GPO1 22
45#define OMAP44XX_DMA_SPI3_TX1 23
46#define OMAP44XX_DMA_SPI3_RX1 24
47#define OMAP44XX_DMA_I2C3_TX 25
48#define OMAP44XX_DMA_I2C3_RX 26
49#define OMAP44XX_DMA_I2C1_TX 27
50#define OMAP44XX_DMA_I2C1_RX 28
51#define OMAP44XX_DMA_I2C2_TX 29
52#define OMAP44XX_DMA_I2C2_RX 30
53#define OMAP44XX_DMA_MCBSP4_TX 31
54#define OMAP44XX_DMA_MCBSP4_RX 32
55#define OMAP44XX_DMA_MCBSP1_TX 33
56#define OMAP44XX_DMA_MCBSP1_RX 34
57#define OMAP44XX_DMA_SPI1_TX0 35
58#define OMAP44XX_DMA_SPI1_RX0 36
59#define OMAP44XX_DMA_SPI1_TX1 37
60#define OMAP44XX_DMA_SPI1_RX1 38
61#define OMAP44XX_DMA_SPI1_TX2 39
62#define OMAP44XX_DMA_SPI1_RX2 40
63#define OMAP44XX_DMA_SPI1_TX3 41
64#define OMAP44XX_DMA_SPI1_RX3 42
65#define OMAP44XX_DMA_SPI2_TX0 43
66#define OMAP44XX_DMA_SPI2_RX0 44
67#define OMAP44XX_DMA_SPI2_TX1 45
68#define OMAP44XX_DMA_SPI2_RX1 46
69#define OMAP44XX_DMA_MMC2_TX 47
70#define OMAP44XX_DMA_MMC2_RX 48
71#define OMAP44XX_DMA_UART1_TX 49
72#define OMAP44XX_DMA_UART1_RX 50
73#define OMAP44XX_DMA_UART2_TX 51
74#define OMAP44XX_DMA_UART2_RX 52
75#define OMAP44XX_DMA_UART3_TX 53
76#define OMAP44XX_DMA_UART3_RX 54
77#define OMAP44XX_DMA_UART4_TX 55
78#define OMAP44XX_DMA_UART4_RX 56
79#define OMAP44XX_DMA_MMC4_TX 57
80#define OMAP44XX_DMA_MMC4_RX 58
81#define OMAP44XX_DMA_MMC5_TX 59
82#define OMAP44XX_DMA_MMC5_RX 60
83#define OMAP44XX_DMA_MMC1_TX 61
84#define OMAP44XX_DMA_MMC1_RX 62
85#define OMAP44XX_DMA_SYS_REQ3 64
86#define OMAP44XX_DMA_MCPDM_UP 65
87#define OMAP44XX_DMA_MCPDM_DL 66
88#define OMAP44XX_DMA_DMIC_REQ 67
89#define OMAP44XX_DMA_C2C_SSCM_GPO2 68
90#define OMAP44XX_DMA_C2C_SSCM_GPO3 69
91#define OMAP44XX_DMA_SPI4_TX0 70
92#define OMAP44XX_DMA_SPI4_RX0 71
93#define OMAP44XX_DMA_DSS_DSI1_REQ0 72
94#define OMAP44XX_DMA_DSS_DSI1_REQ1 73
95#define OMAP44XX_DMA_DSS_DSI1_REQ2 74
96#define OMAP44XX_DMA_DSS_DSI1_REQ3 75
97#define OMAP44XX_DMA_DSS_HDMI_REQ 76
98#define OMAP44XX_DMA_MMC3_TX 77
99#define OMAP44XX_DMA_MMC3_RX 78
100#define OMAP44XX_DMA_USIM_TX 79
101#define OMAP44XX_DMA_USIM_RX 80
102#define OMAP44XX_DMA_DSS_DSI2_REQ0 81
103#define OMAP44XX_DMA_DSS_DSI2_REQ1 82
104#define OMAP44XX_DMA_DSS_DSI2_REQ2 83
105#define OMAP44XX_DMA_DSS_DSI2_REQ3 84
106#define OMAP44XX_DMA_SLIMBUS1_TX0 85
107#define OMAP44XX_DMA_SLIMBUS1_TX1 86
108#define OMAP44XX_DMA_SLIMBUS1_TX2 87
109#define OMAP44XX_DMA_SLIMBUS1_TX3 88
110#define OMAP44XX_DMA_SLIMBUS1_RX0 89
111#define OMAP44XX_DMA_SLIMBUS1_RX1 90
112#define OMAP44XX_DMA_SLIMBUS1_RX2 91
113#define OMAP44XX_DMA_SLIMBUS1_RX3 92
114#define OMAP44XX_DMA_SLIMBUS2_TX0 93
115#define OMAP44XX_DMA_SLIMBUS2_TX1 94
116#define OMAP44XX_DMA_SLIMBUS2_TX2 95
117#define OMAP44XX_DMA_SLIMBUS2_TX3 96
118#define OMAP44XX_DMA_SLIMBUS2_RX0 97
119#define OMAP44XX_DMA_SLIMBUS2_RX1 98
120#define OMAP44XX_DMA_SLIMBUS2_RX2 99
121#define OMAP44XX_DMA_SLIMBUS2_RX3 100
122#define OMAP44XX_DMA_ABE_REQ_0 101
123#define OMAP44XX_DMA_ABE_REQ_1 102
124#define OMAP44XX_DMA_ABE_REQ_2 103
125#define OMAP44XX_DMA_ABE_REQ_3 104
126#define OMAP44XX_DMA_ABE_REQ_4 105
127#define OMAP44XX_DMA_ABE_REQ_5 106
128#define OMAP44XX_DMA_ABE_REQ_6 107
129#define OMAP44XX_DMA_ABE_REQ_7 108
130#define OMAP44XX_DMA_AES1_P_CTX_IN_REQ 109
131#define OMAP44XX_DMA_AES1_P_DATA_IN_REQ 110
132#define OMAP44XX_DMA_AES1_P_DATA_OUT_REQ 111
133#define OMAP44XX_DMA_AES2_P_CTX_IN_REQ 112
134#define OMAP44XX_DMA_AES2_P_DATA_IN_REQ 113
135#define OMAP44XX_DMA_AES2_P_DATA_OUT_REQ 114
136#define OMAP44XX_DMA_DES_P_CTX_IN_REQ 115
137#define OMAP44XX_DMA_DES_P_DATA_IN_REQ 116
138#define OMAP44XX_DMA_DES_P_DATA_OUT_REQ 117
139#define OMAP44XX_DMA_SHA2_CTXIN_P 118
140#define OMAP44XX_DMA_SHA2_DIN_P 119
141#define OMAP44XX_DMA_SHA2_CTXOUT_P 120
142#define OMAP44XX_DMA_AES1_P_CONTEXT_OUT_REQ 121
143#define OMAP44XX_DMA_AES2_P_CONTEXT_OUT_REQ 122
144#define OMAP44XX_DMA_I2C4_TX 124
145#define OMAP44XX_DMA_I2C4_RX 125
146
147#endif
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 348f855d3dab..f8943c8f9dbf 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -94,6 +94,7 @@ struct dmtimer_platform_data {
94 /* set_timer_src - Only used for OMAP1 devices */ 94 /* set_timer_src - Only used for OMAP1 devices */
95 int (*set_timer_src)(struct platform_device *pdev, int source); 95 int (*set_timer_src)(struct platform_device *pdev, int source);
96 u32 timer_capability; 96 u32 timer_capability;
97 int (*get_context_loss_count)(struct device *);
97}; 98};
98 99
99int omap_dm_timer_reserve_systimer(int id); 100int omap_dm_timer_reserve_systimer(int id);
@@ -264,6 +265,7 @@ struct omap_dm_timer {
264 unsigned reserved:1; 265 unsigned reserved:1;
265 unsigned posted:1; 266 unsigned posted:1;
266 struct timer_regs context; 267 struct timer_regs context;
268 int (*get_context_loss_count)(struct device *);
267 int ctx_loss_count; 269 int ctx_loss_count;
268 int revision; 270 int revision;
269 u32 capability; 271 u32 capability;
diff --git a/arch/arm/plat-omap/include/plat/fpga.h b/arch/arm/plat-omap/include/plat/fpga.h
deleted file mode 100644
index bd3c6324ae1f..000000000000
--- a/arch/arm/plat-omap/include/plat/fpga.h
+++ /dev/null
@@ -1,193 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/fpga.h
3 *
4 * Interrupt handler for OMAP-1510 FPGA
5 *
6 * Copyright (C) 2001 RidgeRun, Inc.
7 * Author: Greg Lonnon <glonnon@ridgerun.com>
8 *
9 * Copyright (C) 2002 MontaVista Software, Inc.
10 *
11 * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
12 * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#ifndef __ASM_ARCH_OMAP_FPGA_H
20#define __ASM_ARCH_OMAP_FPGA_H
21
22extern void omap1510_fpga_init_irq(void);
23
24#define fpga_read(reg) __raw_readb(reg)
25#define fpga_write(val, reg) __raw_writeb(val, reg)
26
27/*
28 * ---------------------------------------------------------------------------
29 * H2/P2 Debug board FPGA
30 * ---------------------------------------------------------------------------
31 */
32/* maps in the FPGA registers and the ETHR registers */
33#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */
34#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
35#define H2P2_DBG_FPGA_START 0x04000000 /* PA */
36
37#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
38#define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
39#define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */
40#define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */
41#define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */
42#define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */
43#define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */
44#define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
45
46/* NOTE: most boards don't have a static mapping for the FPGA ... */
47struct h2p2_dbg_fpga {
48 /* offset 0x00 */
49 u16 smc91x[8];
50 /* offset 0x10 */
51 u16 fpga_rev;
52 u16 board_rev;
53 u16 gpio_outputs;
54 u16 leds;
55 /* offset 0x18 */
56 u16 misc_inputs;
57 u16 lan_status;
58 u16 lan_reset;
59 u16 reserved0;
60 /* offset 0x20 */
61 u16 ps2_data;
62 u16 ps2_ctrl;
63 /* plus also 4 rs232 ports ... */
64};
65
66/* LEDs definition on debug board (16 LEDs, all physically green) */
67#define H2P2_DBG_FPGA_LED_GREEN (1 << 15)
68#define H2P2_DBG_FPGA_LED_AMBER (1 << 14)
69#define H2P2_DBG_FPGA_LED_RED (1 << 13)
70#define H2P2_DBG_FPGA_LED_BLUE (1 << 12)
71/* cpu0 load-meter LEDs */
72#define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ...
73#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11
74#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
75
76#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0)
77#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1)
78
79/*
80 * ---------------------------------------------------------------------------
81 * OMAP-1510 FPGA
82 * ---------------------------------------------------------------------------
83 */
84#define OMAP1510_FPGA_BASE 0xE8000000 /* VA */
85#define OMAP1510_FPGA_SIZE SZ_4K
86#define OMAP1510_FPGA_START 0x08000000 /* PA */
87
88/* Revision */
89#define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0)
90#define OMAP1510_FPGA_REV_HIGH IOMEM(OMAP1510_FPGA_BASE + 0x1)
91
92#define OMAP1510_FPGA_LCD_PANEL_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x2)
93#define OMAP1510_FPGA_LED_DIGIT IOMEM(OMAP1510_FPGA_BASE + 0x3)
94#define INNOVATOR_FPGA_HID_SPI IOMEM(OMAP1510_FPGA_BASE + 0x4)
95#define OMAP1510_FPGA_POWER IOMEM(OMAP1510_FPGA_BASE + 0x5)
96
97/* Interrupt status */
98#define OMAP1510_FPGA_ISR_LO IOMEM(OMAP1510_FPGA_BASE + 0x6)
99#define OMAP1510_FPGA_ISR_HI IOMEM(OMAP1510_FPGA_BASE + 0x7)
100
101/* Interrupt mask */
102#define OMAP1510_FPGA_IMR_LO IOMEM(OMAP1510_FPGA_BASE + 0x8)
103#define OMAP1510_FPGA_IMR_HI IOMEM(OMAP1510_FPGA_BASE + 0x9)
104
105/* Reset registers */
106#define OMAP1510_FPGA_HOST_RESET IOMEM(OMAP1510_FPGA_BASE + 0xa)
107#define OMAP1510_FPGA_RST IOMEM(OMAP1510_FPGA_BASE + 0xb)
108
109#define OMAP1510_FPGA_AUDIO IOMEM(OMAP1510_FPGA_BASE + 0xc)
110#define OMAP1510_FPGA_DIP IOMEM(OMAP1510_FPGA_BASE + 0xe)
111#define OMAP1510_FPGA_FPGA_IO IOMEM(OMAP1510_FPGA_BASE + 0xf)
112#define OMAP1510_FPGA_UART1 IOMEM(OMAP1510_FPGA_BASE + 0x14)
113#define OMAP1510_FPGA_UART2 IOMEM(OMAP1510_FPGA_BASE + 0x15)
114#define OMAP1510_FPGA_OMAP1510_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x16)
115#define OMAP1510_FPGA_BOARD_REV IOMEM(OMAP1510_FPGA_BASE + 0x18)
116#define OMAP1510P1_PPT_DATA IOMEM(OMAP1510_FPGA_BASE + 0x100)
117#define OMAP1510P1_PPT_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x101)
118#define OMAP1510P1_PPT_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x102)
119
120#define OMAP1510_FPGA_TOUCHSCREEN IOMEM(OMAP1510_FPGA_BASE + 0x204)
121
122#define INNOVATOR_FPGA_INFO IOMEM(OMAP1510_FPGA_BASE + 0x205)
123#define INNOVATOR_FPGA_LCD_BRIGHT_LO IOMEM(OMAP1510_FPGA_BASE + 0x206)
124#define INNOVATOR_FPGA_LCD_BRIGHT_HI IOMEM(OMAP1510_FPGA_BASE + 0x207)
125#define INNOVATOR_FPGA_LED_GRN_LO IOMEM(OMAP1510_FPGA_BASE + 0x208)
126#define INNOVATOR_FPGA_LED_GRN_HI IOMEM(OMAP1510_FPGA_BASE + 0x209)
127#define INNOVATOR_FPGA_LED_RED_LO IOMEM(OMAP1510_FPGA_BASE + 0x20a)
128#define INNOVATOR_FPGA_LED_RED_HI IOMEM(OMAP1510_FPGA_BASE + 0x20b)
129#define INNOVATOR_FPGA_CAM_USB_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20c)
130#define INNOVATOR_FPGA_EXP_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20d)
131#define INNOVATOR_FPGA_ISR2 IOMEM(OMAP1510_FPGA_BASE + 0x20e)
132#define INNOVATOR_FPGA_IMR2 IOMEM(OMAP1510_FPGA_BASE + 0x210)
133
134#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300)
135
136/*
137 * Power up Giga UART driver, turn on HID clock.
138 * Turn off BT power, since we're not using it and it
139 * draws power.
140 */
141#define OMAP1510_FPGA_RESET_VALUE 0x42
142
143#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7)
144#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6)
145#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5)
146#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4)
147#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3)
148#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2)
149#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1)
150#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0)
151
152/*
153 * Innovator/OMAP1510 FPGA HID register bit definitions
154 */
155#define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */
156#define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */
157#define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */
158#define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */
159#define OMAP1510_FPGA_HID_MISO (1<<4) /* input */
160#define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */
161#define OMAP1510_FPGA_HID_rsrvd (1<<6)
162#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
163
164/* The FPGA IRQ is cascaded through GPIO_13 */
165#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
166
167/* IRQ Numbers for interrupts muxed through the FPGA */
168#define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0)
169#define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1)
170#define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2)
171#define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3)
172#define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4)
173#define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5)
174#define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6)
175#define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7)
176#define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8)
177#define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9)
178#define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10)
179#define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11)
180#define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12)
181#define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13)
182#define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14)
183#define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15)
184#define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16)
185#define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17)
186#define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18)
187#define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19)
188#define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20)
189#define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21)
190#define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22)
191#define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23)
192
193#endif
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
deleted file mode 100644
index 2e6e2597178c..000000000000
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ /dev/null
@@ -1,190 +0,0 @@
1/*
2 * General-Purpose Memory Controller for OMAP2
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __OMAP2_GPMC_H
12#define __OMAP2_GPMC_H
13
14/* Maximum Number of Chip Selects */
15#define GPMC_CS_NUM 8
16
17#define GPMC_CS_CONFIG1 0x00
18#define GPMC_CS_CONFIG2 0x04
19#define GPMC_CS_CONFIG3 0x08
20#define GPMC_CS_CONFIG4 0x0c
21#define GPMC_CS_CONFIG5 0x10
22#define GPMC_CS_CONFIG6 0x14
23#define GPMC_CS_CONFIG7 0x18
24#define GPMC_CS_NAND_COMMAND 0x1c
25#define GPMC_CS_NAND_ADDRESS 0x20
26#define GPMC_CS_NAND_DATA 0x24
27
28/* Control Commands */
29#define GPMC_CONFIG_RDY_BSY 0x00000001
30#define GPMC_CONFIG_DEV_SIZE 0x00000002
31#define GPMC_CONFIG_DEV_TYPE 0x00000003
32#define GPMC_SET_IRQ_STATUS 0x00000004
33#define GPMC_CONFIG_WP 0x00000005
34
35#define GPMC_GET_IRQ_STATUS 0x00000006
36#define GPMC_PREFETCH_FIFO_CNT 0x00000007 /* bytes available in FIFO for r/w */
37#define GPMC_PREFETCH_COUNT 0x00000008 /* remaining bytes to be read/write*/
38#define GPMC_STATUS_BUFFER 0x00000009 /* 1: buffer is available to write */
39
40#define GPMC_NAND_COMMAND 0x0000000a
41#define GPMC_NAND_ADDRESS 0x0000000b
42#define GPMC_NAND_DATA 0x0000000c
43
44#define GPMC_ENABLE_IRQ 0x0000000d
45
46/* ECC commands */
47#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
48#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
49#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
50
51#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
52#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
53#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
54#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
55#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
56#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
57#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
58#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
59#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
60#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
61#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
62#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
63#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
64#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
65#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
66#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
67#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
68#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
69#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
70#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
71#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
72#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
73#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
74#define GPMC_CONFIG7_CSVALID (1 << 6)
75
76#define GPMC_DEVICETYPE_NOR 0
77#define GPMC_DEVICETYPE_NAND 2
78#define GPMC_CONFIG_WRITEPROTECT 0x00000010
79#define GPMC_STATUS_BUFF_EMPTY 0x00000001
80#define WR_RD_PIN_MONITORING 0x00600000
81#define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
82#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
83#define GPMC_IRQ_FIFOEVENTENABLE 0x01
84#define GPMC_IRQ_COUNT_EVENT 0x02
85
86#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
87#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
88
89enum omap_ecc {
90 /* 1-bit ecc: stored at end of spare area */
91 OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
92 OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
93 /* 1-bit ecc: stored at beginning of spare area as romcode */
94 OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
95 OMAP_ECC_BCH4_CODE_HW, /* 4-bit BCH ecc code */
96 OMAP_ECC_BCH8_CODE_HW, /* 8-bit BCH ecc code */
97};
98
99/*
100 * Note that all values in this struct are in nanoseconds except sync_clk
101 * (which is in picoseconds), while the register values are in gpmc_fck cycles.
102 */
103struct gpmc_timings {
104 /* Minimum clock period for synchronous mode (in picoseconds) */
105 u32 sync_clk;
106
107 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
108 u16 cs_on; /* Assertion time */
109 u16 cs_rd_off; /* Read deassertion time */
110 u16 cs_wr_off; /* Write deassertion time */
111
112 /* ADV signal timings corresponding to GPMC_CONFIG3 */
113 u16 adv_on; /* Assertion time */
114 u16 adv_rd_off; /* Read deassertion time */
115 u16 adv_wr_off; /* Write deassertion time */
116
117 /* WE signals timings corresponding to GPMC_CONFIG4 */
118 u16 we_on; /* WE assertion time */
119 u16 we_off; /* WE deassertion time */
120
121 /* OE signals timings corresponding to GPMC_CONFIG4 */
122 u16 oe_on; /* OE assertion time */
123 u16 oe_off; /* OE deassertion time */
124
125 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
126 u16 page_burst_access; /* Multiple access word delay */
127 u16 access; /* Start-cycle to first data valid delay */
128 u16 rd_cycle; /* Total read cycle time */
129 u16 wr_cycle; /* Total write cycle time */
130
131 /* The following are only on OMAP3430 */
132 u16 wr_access; /* WRACCESSTIME */
133 u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
134};
135
136struct gpmc_nand_regs {
137 void __iomem *gpmc_status;
138 void __iomem *gpmc_nand_command;
139 void __iomem *gpmc_nand_address;
140 void __iomem *gpmc_nand_data;
141 void __iomem *gpmc_prefetch_config1;
142 void __iomem *gpmc_prefetch_config2;
143 void __iomem *gpmc_prefetch_control;
144 void __iomem *gpmc_prefetch_status;
145 void __iomem *gpmc_ecc_config;
146 void __iomem *gpmc_ecc_control;
147 void __iomem *gpmc_ecc_size_config;
148 void __iomem *gpmc_ecc1_result;
149 void __iomem *gpmc_bch_result0;
150};
151
152extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
153extern int gpmc_get_client_irq(unsigned irq_config);
154
155extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
156extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
157extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
158extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
159extern unsigned long gpmc_get_fclk_period(void);
160
161extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
162extern u32 gpmc_cs_read_reg(int cs, int idx);
163extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
164extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
165extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
166extern void gpmc_cs_free(int cs);
167extern int gpmc_cs_set_reserved(int cs, int reserved);
168extern int gpmc_cs_reserved(int cs);
169extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
170 unsigned int u32_count, int is_write);
171extern int gpmc_prefetch_reset(int cs);
172extern void omap3_gpmc_save_context(void);
173extern void omap3_gpmc_restore_context(void);
174extern int gpmc_read_status(int cmd);
175extern int gpmc_cs_configure(int cs, int cmd, int wval);
176extern int gpmc_nand_read(int cs, int cmd);
177extern int gpmc_nand_write(int cs, int cmd, int wval);
178
179int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size);
180int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code);
181
182#ifdef CONFIG_ARCH_OMAP3
183int gpmc_init_hwecc_bch(int cs, int nsectors, int nerrors);
184int gpmc_enable_hwecc_bch(int cs, int mode, int dev_width, int nsectors,
185 int nerrors);
186int gpmc_calculate_ecc_bch4(int cs, const u_char *dat, u_char *ecc);
187int gpmc_calculate_ecc_bch8(int cs, const u_char *dat, u_char *ecc);
188#endif /* CONFIG_ARCH_OMAP3 */
189
190#endif
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
index 7c22b9e10dc3..7a9028cb5a75 100644
--- a/arch/arm/plat-omap/include/plat/i2c.h
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -18,11 +18,15 @@
18 * 02110-1301 USA 18 * 02110-1301 USA
19 * 19 *
20 */ 20 */
21#ifndef __ASM__ARCH_OMAP_I2C_H
22#define __ASM__ARCH_OMAP_I2C_H
23 21
24#include <linux/i2c.h> 22#ifndef __PLAT_OMAP_I2C_H
25#include <linux/i2c-omap.h> 23#define __PLAT_OMAP_I2C_H
24
25struct i2c_board_info;
26struct omap_i2c_bus_platform_data;
27
28int omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
29 int bus_id);
26 30
27#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE) 31#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
28extern int omap_register_i2c_bus(int bus_id, u32 clkrate, 32extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
@@ -37,23 +41,7 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
37} 41}
38#endif 42#endif
39 43
40/**
41 * i2c_dev_attr - OMAP I2C controller device attributes for omap_hwmod
42 * @fifo_depth: total controller FIFO size (in bytes)
43 * @flags: differences in hardware support capability
44 *
45 * @fifo_depth represents what exists on the hardware, not what is
46 * actually configured at runtime by the device driver.
47 */
48struct omap_i2c_dev_attr {
49 u8 fifo_depth;
50 u32 flags;
51};
52
53void __init omap1_i2c_mux_pins(int bus_id);
54void __init omap2_i2c_mux_pins(int bus_id);
55
56struct omap_hwmod; 44struct omap_hwmod;
57int omap_i2c_reset(struct omap_hwmod *oh); 45int omap_i2c_reset(struct omap_hwmod *oh);
58 46
59#endif /* __ASM__ARCH_OMAP_I2C_H */ 47#endif /* __PLAT_OMAP_I2C_H */
diff --git a/arch/arm/plat-omap/include/plat/led.h b/arch/arm/plat-omap/include/plat/led.h
deleted file mode 100644
index 25e451e7e2fd..000000000000
--- a/arch/arm/plat-omap/include/plat/led.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/led.h
3 *
4 * Copyright (C) 2006 Samsung Electronics
5 * Kyungmin Park <kyungmin.park@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef ASMARM_ARCH_LED_H
12#define ASMARM_ARCH_LED_H
13
14struct omap_led_config {
15 struct led_classdev cdev;
16 s16 gpio;
17};
18
19struct omap_led_platform_data {
20 s16 nr_leds;
21 struct omap_led_config *leds;
22};
23
24#endif
diff --git a/arch/arm/plat-omap/include/plat/menelaus.h b/arch/arm/plat-omap/include/plat/menelaus.h
deleted file mode 100644
index 4a970ec62dd1..000000000000
--- a/arch/arm/plat-omap/include/plat/menelaus.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/menelaus.h
3 *
4 * Functions to access Menelaus power management chip
5 */
6
7#ifndef __ASM_ARCH_MENELAUS_H
8#define __ASM_ARCH_MENELAUS_H
9
10struct device;
11
12struct menelaus_platform_data {
13 int (* late_init)(struct device *dev);
14};
15
16extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask),
17 void *data);
18extern void menelaus_unregister_mmc_callback(void);
19extern int menelaus_set_mmc_opendrain(int slot, int enable);
20extern int menelaus_set_mmc_slot(int slot, int enable, int power, int cd_on);
21
22extern int menelaus_set_vmem(unsigned int mV);
23extern int menelaus_set_vio(unsigned int mV);
24extern int menelaus_set_vmmc(unsigned int mV);
25extern int menelaus_set_vaux(unsigned int mV);
26extern int menelaus_set_vdcdc(int dcdc, unsigned int mV);
27extern int menelaus_set_slot_sel(int enable);
28extern int menelaus_get_slot_pin_states(void);
29extern int menelaus_set_vcore_sw(unsigned int mV);
30extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV);
31
32#define EN_VPLL_SLEEP (1 << 7)
33#define EN_VMMC_SLEEP (1 << 6)
34#define EN_VAUX_SLEEP (1 << 5)
35#define EN_VIO_SLEEP (1 << 4)
36#define EN_VMEM_SLEEP (1 << 3)
37#define EN_DC3_SLEEP (1 << 2)
38#define EN_DC2_SLEEP (1 << 1)
39#define EN_VC_SLEEP (1 << 0)
40
41extern int menelaus_set_regulator_sleep(int enable, u32 val);
42
43#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_MENELAUS)
44#define omap_has_menelaus() 1
45#else
46#define omap_has_menelaus() 0
47#endif
48
49#endif
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
deleted file mode 100644
index 8b4e4f2da2f5..000000000000
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ /dev/null
@@ -1,188 +0,0 @@
1/*
2 * MMC definitions for OMAP2
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __OMAP2_MMC_H
12#define __OMAP2_MMC_H
13
14#include <linux/types.h>
15#include <linux/device.h>
16#include <linux/mmc/host.h>
17
18#include <plat/omap_hwmod.h>
19
20#define OMAP15XX_NR_MMC 1
21#define OMAP16XX_NR_MMC 2
22#define OMAP1_MMC_SIZE 0x080
23#define OMAP1_MMC1_BASE 0xfffb7800
24#define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */
25
26#define OMAP24XX_NR_MMC 2
27#define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE
28#define OMAP2_MMC1_BASE 0x4809c000
29
30#define OMAP4_MMC_REG_OFFSET 0x100
31
32#define OMAP_MMC_MAX_SLOTS 2
33
34/*
35 * struct omap_mmc_dev_attr.flags possibilities
36 *
37 * OMAP_HSMMC_SUPPORTS_DUAL_VOLT: Some HSMMC controller instances can
38 * operate with either 1.8Vdc or 3.0Vdc card voltages; this flag
39 * should be set if this is the case. See for example Section 22.5.3
40 * "MMC/SD/SDIO1 Bus Voltage Selection" of the OMAP34xx Multimedia
41 * Device Silicon Revision 3.1.x Revision ZR (July 2011) (SWPU223R).
42 *
43 * OMAP_HSMMC_BROKEN_MULTIBLOCK_READ: Multiple-block read transfers
44 * don't work correctly on some MMC controller instances on some
45 * OMAP3 SoCs; this flag should be set if this is the case. See
46 * for example Advisory 2.1.1.128 "MMC: Multiple Block Read
47 * Operation Issue" in _OMAP3530/3525/3515/3503 Silicon Errata_
48 * Revision F (October 2010) (SPRZ278F).
49 */
50#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)
51#define OMAP_HSMMC_BROKEN_MULTIBLOCK_READ BIT(1)
52
53struct omap_mmc_dev_attr {
54 u8 flags;
55};
56
57struct omap_mmc_platform_data {
58 /* back-link to device */
59 struct device *dev;
60
61 /* number of slots per controller */
62 unsigned nr_slots:2;
63
64 /* set if your board has components or wiring that limits the
65 * maximum frequency on the MMC bus */
66 unsigned int max_freq;
67
68 /* switch the bus to a new slot */
69 int (*switch_slot)(struct device *dev, int slot);
70 /* initialize board-specific MMC functionality, can be NULL if
71 * not supported */
72 int (*init)(struct device *dev);
73 void (*cleanup)(struct device *dev);
74 void (*shutdown)(struct device *dev);
75
76 /* To handle board related suspend/resume functionality for MMC */
77 int (*suspend)(struct device *dev, int slot);
78 int (*resume)(struct device *dev, int slot);
79
80 /* Return context loss count due to PM states changing */
81 int (*get_context_loss_count)(struct device *dev);
82
83 /* Integrating attributes from the omap_hwmod layer */
84 u8 controller_flags;
85
86 /* Register offset deviation */
87 u16 reg_offset;
88
89 struct omap_mmc_slot_data {
90
91 /*
92 * 4/8 wires and any additional host capabilities
93 * need to OR'd all capabilities (ref. linux/mmc/host.h)
94 */
95 u8 wires; /* Used for the MMC driver on omap1 and 2420 */
96 u32 caps; /* Used for the MMC driver on 2430 and later */
97 u32 pm_caps; /* PM capabilities of the mmc */
98
99 /*
100 * nomux means "standard" muxing is wrong on this board, and
101 * that board-specific code handled it before common init logic.
102 */
103 unsigned nomux:1;
104
105 /* switch pin can be for card detect (default) or card cover */
106 unsigned cover:1;
107
108 /* use the internal clock */
109 unsigned internal_clock:1;
110
111 /* nonremovable e.g. eMMC */
112 unsigned nonremovable:1;
113
114 /* Try to sleep or power off when possible */
115 unsigned power_saving:1;
116
117 /* If using power_saving and the MMC power is not to go off */
118 unsigned no_off:1;
119
120 /* eMMC does not handle power off when not in sleep state */
121 unsigned no_regulator_off_init:1;
122
123 /* Regulator off remapped to sleep */
124 unsigned vcc_aux_disable_is_sleep:1;
125
126 /* we can put the features above into this variable */
127#define HSMMC_HAS_PBIAS (1 << 0)
128#define HSMMC_HAS_UPDATED_RESET (1 << 1)
129 unsigned features;
130
131 int switch_pin; /* gpio (card detect) */
132 int gpio_wp; /* gpio (write protect) */
133
134 int (*set_bus_mode)(struct device *dev, int slot, int bus_mode);
135 int (*set_power)(struct device *dev, int slot,
136 int power_on, int vdd);
137 int (*get_ro)(struct device *dev, int slot);
138 void (*remux)(struct device *dev, int slot, int power_on);
139 /* Call back before enabling / disabling regulators */
140 void (*before_set_reg)(struct device *dev, int slot,
141 int power_on, int vdd);
142 /* Call back after enabling / disabling regulators */
143 void (*after_set_reg)(struct device *dev, int slot,
144 int power_on, int vdd);
145 /* if we have special card, init it using this callback */
146 void (*init_card)(struct mmc_card *card);
147
148 /* return MMC cover switch state, can be NULL if not supported.
149 *
150 * possible return values:
151 * 0 - closed
152 * 1 - open
153 */
154 int (*get_cover_state)(struct device *dev, int slot);
155
156 const char *name;
157 u32 ocr_mask;
158
159 /* Card detection IRQs */
160 int card_detect_irq;
161 int (*card_detect)(struct device *dev, int slot);
162
163 unsigned int ban_openended:1;
164
165 } slots[OMAP_MMC_MAX_SLOTS];
166};
167
168/* called from board-specific card detection service routine */
169extern void omap_mmc_notify_cover_event(struct device *dev, int slot,
170 int is_closed);
171
172#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
173void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
174 int nr_controllers);
175void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data);
176#else
177static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
178 int nr_controllers)
179{
180}
181static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
182{
183}
184#endif
185
186extern int omap_msdi_reset(struct omap_hwmod *oh);
187
188#endif
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
deleted file mode 100644
index 324d31b14852..000000000000
--- a/arch/arm/plat-omap/include/plat/multi.h
+++ /dev/null
@@ -1,120 +0,0 @@
1/*
2 * Support for compiling in multiple OMAP processors
3 *
4 * Copyright (C) 2010 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22#ifndef __PLAT_OMAP_MULTI_H
23#define __PLAT_OMAP_MULTI_H
24
25/*
26 * Test if multicore OMAP support is needed
27 */
28#undef MULTI_OMAP1
29#undef MULTI_OMAP2
30#undef OMAP_NAME
31
32#ifdef CONFIG_ARCH_OMAP730
33# ifdef OMAP_NAME
34# undef MULTI_OMAP1
35# define MULTI_OMAP1
36# else
37# define OMAP_NAME omap730
38# endif
39#endif
40#ifdef CONFIG_ARCH_OMAP850
41# ifdef OMAP_NAME
42# undef MULTI_OMAP1
43# define MULTI_OMAP1
44# else
45# define OMAP_NAME omap850
46# endif
47#endif
48#ifdef CONFIG_ARCH_OMAP15XX
49# ifdef OMAP_NAME
50# undef MULTI_OMAP1
51# define MULTI_OMAP1
52# else
53# define OMAP_NAME omap1510
54# endif
55#endif
56#ifdef CONFIG_ARCH_OMAP16XX
57# ifdef OMAP_NAME
58# undef MULTI_OMAP1
59# define MULTI_OMAP1
60# else
61# define OMAP_NAME omap16xx
62# endif
63#endif
64#ifdef CONFIG_ARCH_OMAP2PLUS
65# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
66# error "OMAP1 and OMAP2PLUS can't be selected at the same time"
67# endif
68#endif
69#ifdef CONFIG_SOC_OMAP2420
70# ifdef OMAP_NAME
71# undef MULTI_OMAP2
72# define MULTI_OMAP2
73# else
74# define OMAP_NAME omap2420
75# endif
76#endif
77#ifdef CONFIG_SOC_OMAP2430
78# ifdef OMAP_NAME
79# undef MULTI_OMAP2
80# define MULTI_OMAP2
81# else
82# define OMAP_NAME omap2430
83# endif
84#endif
85#ifdef CONFIG_ARCH_OMAP3
86# ifdef OMAP_NAME
87# undef MULTI_OMAP2
88# define MULTI_OMAP2
89# else
90# define OMAP_NAME omap3
91# endif
92#endif
93#ifdef CONFIG_ARCH_OMAP4
94# ifdef OMAP_NAME
95# undef MULTI_OMAP2
96# define MULTI_OMAP2
97# else
98# define OMAP_NAME omap4
99# endif
100#endif
101
102#ifdef CONFIG_SOC_OMAP5
103# ifdef OMAP_NAME
104# undef MULTI_OMAP2
105# define MULTI_OMAP2
106# else
107# define OMAP_NAME omap5
108# endif
109#endif
110
111#ifdef CONFIG_SOC_AM33XX
112# ifdef OMAP_NAME
113# undef MULTI_OMAP2
114# define MULTI_OMAP2
115# else
116# define OMAP_NAME am33xx
117# endif
118#endif
119
120#endif /* __PLAT_OMAP_MULTI_H */
diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h
deleted file mode 100644
index 67faa7b8fe92..000000000000
--- a/arch/arm/plat-omap/include/plat/omap-pm.h
+++ /dev/null
@@ -1,352 +0,0 @@
1/*
2 * omap-pm.h - OMAP power management interface
3 *
4 * Copyright (C) 2008-2010 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation
6 * Paul Walmsley
7 *
8 * Interface developed by (in alphabetical order): Karthik Dasu, Jouni
9 * Högander, Tony Lindgren, Rajendra Nayak, Sakari Poussa,
10 * Veeramanikandan Raju, Anand Sawant, Igor Stoppa, Paul Walmsley,
11 * Richard Woodruff
12 */
13
14#ifndef ASM_ARM_ARCH_OMAP_OMAP_PM_H
15#define ASM_ARM_ARCH_OMAP_OMAP_PM_H
16
17#include <linux/device.h>
18#include <linux/cpufreq.h>
19#include <linux/clk.h>
20#include <linux/opp.h>
21
22/*
23 * agent_id values for use with omap_pm_set_min_bus_tput():
24 *
25 * OCP_INITIATOR_AGENT is only valid for devices that can act as
26 * initiators -- it represents the device's L3 interconnect
27 * connection. OCP_TARGET_AGENT represents the device's L4
28 * interconnect connection.
29 */
30#define OCP_TARGET_AGENT 1
31#define OCP_INITIATOR_AGENT 2
32
33/**
34 * omap_pm_if_early_init - OMAP PM init code called before clock fw init
35 * @mpu_opp_table: array ptr to struct omap_opp for MPU
36 * @dsp_opp_table: array ptr to struct omap_opp for DSP
37 * @l3_opp_table : array ptr to struct omap_opp for CORE
38 *
39 * Initialize anything that must be configured before the clock
40 * framework starts. The "_if_" is to avoid name collisions with the
41 * PM idle-loop code.
42 */
43int __init omap_pm_if_early_init(void);
44
45/**
46 * omap_pm_if_init - OMAP PM init code called after clock fw init
47 *
48 * The main initialization code. OPP tables are passed in here. The
49 * "_if_" is to avoid name collisions with the PM idle-loop code.
50 */
51int __init omap_pm_if_init(void);
52
53/**
54 * omap_pm_if_exit - OMAP PM exit code
55 *
56 * Exit code; currently unused. The "_if_" is to avoid name
57 * collisions with the PM idle-loop code.
58 */
59void omap_pm_if_exit(void);
60
61/*
62 * Device-driver-originated constraints (via board-*.c files, platform_data)
63 */
64
65
66/**
67 * omap_pm_set_max_mpu_wakeup_lat - set the maximum MPU wakeup latency
68 * @dev: struct device * requesting the constraint
69 * @t: maximum MPU wakeup latency in microseconds
70 *
71 * Request that the maximum interrupt latency for the MPU to be no
72 * greater than @t microseconds. "Interrupt latency" in this case is
73 * defined as the elapsed time from the occurrence of a hardware or
74 * timer interrupt to the time when the device driver's interrupt
75 * service routine has been entered by the MPU.
76 *
77 * It is intended that underlying PM code will use this information to
78 * determine what power state to put the MPU powerdomain into, and
79 * possibly the CORE powerdomain as well, since interrupt handling
80 * code currently runs from SDRAM. Advanced PM or board*.c code may
81 * also configure interrupt controller priorities, OCP bus priorities,
82 * CPU speed(s), etc.
83 *
84 * This function will not affect device wakeup latency, e.g., time
85 * elapsed from when a device driver enables a hardware device with
86 * clk_enable(), to when the device is ready for register access or
87 * other use. To control this device wakeup latency, use
88 * omap_pm_set_max_dev_wakeup_lat()
89 *
90 * Multiple calls to omap_pm_set_max_mpu_wakeup_lat() will replace the
91 * previous t value. To remove the latency target for the MPU, call
92 * with t = -1.
93 *
94 * XXX This constraint will be deprecated soon in favor of the more
95 * general omap_pm_set_max_dev_wakeup_lat()
96 *
97 * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
98 * is not satisfiable, or 0 upon success.
99 */
100int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
101
102
103/**
104 * omap_pm_set_min_bus_tput - set minimum bus throughput needed by device
105 * @dev: struct device * requesting the constraint
106 * @tbus_id: interconnect to operate on (OCP_{INITIATOR,TARGET}_AGENT)
107 * @r: minimum throughput (in KiB/s)
108 *
109 * Request that the minimum data throughput on the OCP interconnect
110 * attached to device @dev interconnect agent @tbus_id be no less
111 * than @r KiB/s.
112 *
113 * It is expected that the OMAP PM or bus code will use this
114 * information to set the interconnect clock to run at the lowest
115 * possible speed that satisfies all current system users. The PM or
116 * bus code will adjust the estimate based on its model of the bus, so
117 * device driver authors should attempt to specify an accurate
118 * quantity for their device use case, and let the PM or bus code
119 * overestimate the numbers as necessary to handle request/response
120 * latency, other competing users on the system, etc. On OMAP2/3, if
121 * a driver requests a minimum L4 interconnect speed constraint, the
122 * code will also need to add an minimum L3 interconnect speed
123 * constraint,
124 *
125 * Multiple calls to omap_pm_set_min_bus_tput() will replace the
126 * previous rate value for this device. To remove the interconnect
127 * throughput restriction for this device, call with r = 0.
128 *
129 * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
130 * is not satisfiable, or 0 upon success.
131 */
132int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r);
133
134
135/**
136 * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency
137 * @req_dev: struct device * requesting the constraint, or NULL if none
138 * @dev: struct device * to set the constraint one
139 * @t: maximum device wakeup latency in microseconds
140 *
141 * Request that the maximum amount of time necessary for a device @dev
142 * to become accessible after its clocks are enabled should be no
143 * greater than @t microseconds. Specifically, this represents the
144 * time from when a device driver enables device clocks with
145 * clk_enable(), to when the register reads and writes on the device
146 * will succeed. This function should be called before clk_disable()
147 * is called, since the power state transition decision may be made
148 * during clk_disable().
149 *
150 * It is intended that underlying PM code will use this information to
151 * determine what power state to put the powerdomain enclosing this
152 * device into.
153 *
154 * Multiple calls to omap_pm_set_max_dev_wakeup_lat() will replace the
155 * previous wakeup latency values for this device. To remove the
156 * wakeup latency restriction for this device, call with t = -1.
157 *
158 * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
159 * is not satisfiable, or 0 upon success.
160 */
161int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
162 long t);
163
164
165/**
166 * omap_pm_set_max_sdma_lat - set the maximum system DMA transfer start latency
167 * @dev: struct device *
168 * @t: maximum DMA transfer start latency in microseconds
169 *
170 * Request that the maximum system DMA transfer start latency for this
171 * device 'dev' should be no greater than 't' microseconds. "DMA
172 * transfer start latency" here is defined as the elapsed time from
173 * when a device (e.g., McBSP) requests that a system DMA transfer
174 * start or continue, to the time at which data starts to flow into
175 * that device from the system DMA controller.
176 *
177 * It is intended that underlying PM code will use this information to
178 * determine what power state to put the CORE powerdomain into.
179 *
180 * Since system DMA transfers may not involve the MPU, this function
181 * will not affect MPU wakeup latency. Use set_max_cpu_lat() to do
182 * so. Similarly, this function will not affect device wakeup latency
183 * -- use set_max_dev_wakeup_lat() to affect that.
184 *
185 * Multiple calls to set_max_sdma_lat() will replace the previous t
186 * value for this device. To remove the maximum DMA latency for this
187 * device, call with t = -1.
188 *
189 * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
190 * is not satisfiable, or 0 upon success.
191 */
192int omap_pm_set_max_sdma_lat(struct device *dev, long t);
193
194
195/**
196 * omap_pm_set_min_clk_rate - set minimum clock rate requested by @dev
197 * @dev: struct device * requesting the constraint
198 * @clk: struct clk * to set the minimum rate constraint on
199 * @r: minimum rate in Hz
200 *
201 * Request that the minimum clock rate on the device @dev's clk @clk
202 * be no less than @r Hz.
203 *
204 * It is expected that the OMAP PM code will use this information to
205 * find an OPP or clock setting that will satisfy this clock rate
206 * constraint, along with any other applicable system constraints on
207 * the clock rate or corresponding voltage, etc.
208 *
209 * omap_pm_set_min_clk_rate() differs from the clock code's
210 * clk_set_rate() in that it considers other constraints before taking
211 * any hardware action, and may change a system OPP rather than just a
212 * clock rate. clk_set_rate() is intended to be a low-level
213 * interface.
214 *
215 * omap_pm_set_min_clk_rate() is easily open to abuse. A better API
216 * would be something like "omap_pm_set_min_dev_performance()";
217 * however, there is no easily-generalizable concept of performance
218 * that applies to all devices. Only a device (and possibly the
219 * device subsystem) has both the subsystem-specific knowledge, and
220 * the hardware IP block-specific knowledge, to translate a constraint
221 * on "touchscreen sampling accuracy" or "number of pixels or polygons
222 * rendered per second" to a clock rate. This translation can be
223 * dependent on the hardware IP block's revision, or firmware version,
224 * and the driver is the only code on the system that has this
225 * information and can know how to translate that into a clock rate.
226 *
227 * The intended use-case for this function is for userspace or other
228 * kernel code to communicate a particular performance requirement to
229 * a subsystem; then for the subsystem to communicate that requirement
230 * to something that is meaningful to the device driver; then for the
231 * device driver to convert that requirement to a clock rate, and to
232 * then call omap_pm_set_min_clk_rate().
233 *
234 * Users of this function (such as device drivers) should not simply
235 * call this function with some high clock rate to ensure "high
236 * performance." Rather, the device driver should take a performance
237 * constraint from its subsystem, such as "render at least X polygons
238 * per second," and use some formula or table to convert that into a
239 * clock rate constraint given the hardware type and hardware
240 * revision. Device drivers or subsystems should not assume that they
241 * know how to make a power/performance tradeoff - some device use
242 * cases may tolerate a lower-fidelity device function for lower power
243 * consumption; others may demand a higher-fidelity device function,
244 * no matter what the power consumption.
245 *
246 * Multiple calls to omap_pm_set_min_clk_rate() will replace the
247 * previous rate value for the device @dev. To remove the minimum clock
248 * rate constraint for the device, call with r = 0.
249 *
250 * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
251 * is not satisfiable, or 0 upon success.
252 */
253int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r);
254
255/*
256 * DSP Bridge-specific constraints
257 */
258
259/**
260 * omap_pm_dsp_get_opp_table - get OPP->DSP clock frequency table
261 *
262 * Intended for use by DSPBridge. Returns an array of OPP->DSP clock
263 * frequency entries. The final item in the array should have .rate =
264 * .opp_id = 0.
265 */
266const struct omap_opp *omap_pm_dsp_get_opp_table(void);
267
268/**
269 * omap_pm_dsp_set_min_opp - receive desired OPP target ID from DSP Bridge
270 * @opp_id: target DSP OPP ID
271 *
272 * Set a minimum OPP ID for the DSP. This is intended to be called
273 * only from the DSP Bridge MPU-side driver. Unfortunately, the only
274 * information that code receives from the DSP/BIOS load estimator is the
275 * target OPP ID; hence, this interface. No return value.
276 */
277void omap_pm_dsp_set_min_opp(u8 opp_id);
278
279/**
280 * omap_pm_dsp_get_opp - report the current DSP OPP ID
281 *
282 * Report the current OPP for the DSP. Since on OMAP3, the DSP and
283 * MPU share a single voltage domain, the OPP ID returned back may
284 * represent a higher DSP speed than the OPP requested via
285 * omap_pm_dsp_set_min_opp().
286 *
287 * Returns the current VDD1 OPP ID, or 0 upon error.
288 */
289u8 omap_pm_dsp_get_opp(void);
290
291
292/*
293 * CPUFreq-originated constraint
294 *
295 * In the future, this should be handled by custom OPP clocktype
296 * functions.
297 */
298
299/**
300 * omap_pm_cpu_get_freq_table - return a cpufreq_frequency_table array ptr
301 *
302 * Provide a frequency table usable by CPUFreq for the current chip/board.
303 * Returns a pointer to a struct cpufreq_frequency_table array or NULL
304 * upon error.
305 */
306struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void);
307
308/**
309 * omap_pm_cpu_set_freq - set the current minimum MPU frequency
310 * @f: MPU frequency in Hz
311 *
312 * Set the current minimum CPU frequency. The actual CPU frequency
313 * used could end up higher if the DSP requested a higher OPP.
314 * Intended to be called by plat-omap/cpu_omap.c:omap_target(). No
315 * return value.
316 */
317void omap_pm_cpu_set_freq(unsigned long f);
318
319/**
320 * omap_pm_cpu_get_freq - report the current CPU frequency
321 *
322 * Returns the current MPU frequency, or 0 upon error.
323 */
324unsigned long omap_pm_cpu_get_freq(void);
325
326
327/*
328 * Device context loss tracking
329 */
330
331/**
332 * omap_pm_get_dev_context_loss_count - return count of times dev has lost ctx
333 * @dev: struct device *
334 *
335 * This function returns the number of times that the device @dev has
336 * lost its internal context. This generally occurs on a powerdomain
337 * transition to OFF. Drivers use this as an optimization to avoid restoring
338 * context if the device hasn't lost it. To use, drivers should initially
339 * call this in their context save functions and store the result. Early in
340 * the driver's context restore function, the driver should call this function
341 * again, and compare the result to the stored counter. If they differ, the
342 * driver must restore device context. If the number of context losses
343 * exceeds the maximum positive integer, the function will wrap to 0 and
344 * continue counting. Returns the number of context losses for this device,
345 * or negative value upon error.
346 */
347int omap_pm_get_dev_context_loss_count(struct device *dev);
348
349void omap_pm_enable_off_mode(void);
350void omap_pm_disable_off_mode(void);
351
352#endif
diff --git a/arch/arm/plat-omap/include/plat/omap-secure.h b/arch/arm/plat-omap/include/plat/omap-secure.h
deleted file mode 100644
index 0e4acd2d2deb..000000000000
--- a/arch/arm/plat-omap/include/plat/omap-secure.h
+++ /dev/null
@@ -1,14 +0,0 @@
1#ifndef __OMAP_SECURE_H__
2#define __OMAP_SECURE_H__
3
4#include <linux/types.h>
5
6extern int omap_secure_ram_reserve_memblock(void);
7
8#ifdef CONFIG_OMAP4_ERRATA_I688
9extern int omap_barrier_reserve_memblock(void);
10#else
11static inline void omap_barrier_reserve_memblock(void)
12{ }
13#endif
14#endif /* __OMAP_SECURE_H__ */
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
deleted file mode 100644
index 106f50665804..000000000000
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ /dev/null
@@ -1,176 +0,0 @@
1/*
2 * omap_device headers
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Paul Walmsley
6 *
7 * Developed in collaboration with (alphabetical order): Benoit
8 * Cousson, Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram
9 * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard
10 * Woodruff
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * Eventually this type of functionality should either be
17 * a) implemented via arch-specific pointers in platform_device
18 * or
19 * b) implemented as a proper omap_bus/omap_device in Linux, no more
20 * platform_device
21 *
22 * omap_device differs from omap_hwmod in that it includes external
23 * (e.g., board- and system-level) integration details. omap_hwmod
24 * stores hardware data that is invariant for a given OMAP chip.
25 *
26 * To do:
27 * - GPIO integration
28 * - regulator integration
29 *
30 */
31#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
32#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
33
34#include <linux/kernel.h>
35#include <linux/platform_device.h>
36
37#include <plat/omap_hwmod.h>
38
39extern struct dev_pm_domain omap_device_pm_domain;
40
41/* omap_device._state values */
42#define OMAP_DEVICE_STATE_UNKNOWN 0
43#define OMAP_DEVICE_STATE_ENABLED 1
44#define OMAP_DEVICE_STATE_IDLE 2
45#define OMAP_DEVICE_STATE_SHUTDOWN 3
46
47/* omap_device.flags values */
48#define OMAP_DEVICE_SUSPENDED BIT(0)
49#define OMAP_DEVICE_NO_IDLE_ON_SUSPEND BIT(1)
50
51/**
52 * struct omap_device - omap_device wrapper for platform_devices
53 * @pdev: platform_device
54 * @hwmods: (one .. many per omap_device)
55 * @hwmods_cnt: ARRAY_SIZE() of @hwmods
56 * @pm_lats: ptr to an omap_device_pm_latency table
57 * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats
58 * @pm_lat_level: array index of the last odpl entry executed - -1 if never
59 * @dev_wakeup_lat: dev wakeup latency in nanoseconds
60 * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
61 * @_state: one of OMAP_DEVICE_STATE_* (see above)
62 * @flags: device flags
63 * @_driver_status: one of BUS_NOTIFY_*_DRIVER from <linux/device.h>
64 *
65 * Integrates omap_hwmod data into Linux platform_device.
66 *
67 * Field names beginning with underscores are for the internal use of
68 * the omap_device code.
69 *
70 */
71struct omap_device {
72 struct platform_device *pdev;
73 struct omap_hwmod **hwmods;
74 struct omap_device_pm_latency *pm_lats;
75 u32 dev_wakeup_lat;
76 u32 _dev_wakeup_lat_limit;
77 unsigned long _driver_status;
78 u8 pm_lats_cnt;
79 s8 pm_lat_level;
80 u8 hwmods_cnt;
81 u8 _state;
82 u8 flags;
83};
84
85/* Device driver interface (call via platform_data fn ptrs) */
86
87int omap_device_enable(struct platform_device *pdev);
88int omap_device_idle(struct platform_device *pdev);
89int omap_device_shutdown(struct platform_device *pdev);
90
91/* Core code interface */
92
93struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
94 struct omap_hwmod *oh, void *pdata,
95 int pdata_len,
96 struct omap_device_pm_latency *pm_lats,
97 int pm_lats_cnt, int is_early_device);
98
99struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
100 struct omap_hwmod **oh, int oh_cnt,
101 void *pdata, int pdata_len,
102 struct omap_device_pm_latency *pm_lats,
103 int pm_lats_cnt, int is_early_device);
104
105struct omap_device *omap_device_alloc(struct platform_device *pdev,
106 struct omap_hwmod **ohs, int oh_cnt,
107 struct omap_device_pm_latency *pm_lats,
108 int pm_lats_cnt);
109void omap_device_delete(struct omap_device *od);
110int omap_device_register(struct platform_device *pdev);
111
112void __iomem *omap_device_get_rt_va(struct omap_device *od);
113struct device *omap_device_get_by_hwmod_name(const char *oh_name);
114
115/* OMAP PM interface */
116int omap_device_align_pm_lat(struct platform_device *pdev,
117 u32 new_wakeup_lat_limit);
118struct powerdomain *omap_device_get_pwrdm(struct omap_device *od);
119int omap_device_get_context_loss_count(struct platform_device *pdev);
120
121/* Other */
122
123int omap_device_assert_hardreset(struct platform_device *pdev,
124 const char *name);
125int omap_device_deassert_hardreset(struct platform_device *pdev,
126 const char *name);
127int omap_device_idle_hwmods(struct omap_device *od);
128int omap_device_enable_hwmods(struct omap_device *od);
129
130int omap_device_disable_clocks(struct omap_device *od);
131int omap_device_enable_clocks(struct omap_device *od);
132
133/*
134 * Entries should be kept in latency order ascending
135 *
136 * deact_lat is the maximum number of microseconds required to complete
137 * deactivate_func() at the device's slowest OPP.
138 *
139 * act_lat is the maximum number of microseconds required to complete
140 * activate_func() at the device's slowest OPP.
141 *
142 * This will result in some suboptimal power management decisions at fast
143 * OPPs, but avoids having to recompute all device power management decisions
144 * if the system shifts from a fast OPP to a slow OPP (in order to meet
145 * latency requirements).
146 *
147 * XXX should deactivate_func/activate_func() take platform_device pointers
148 * rather than omap_device pointers?
149 */
150struct omap_device_pm_latency {
151 u32 deactivate_lat;
152 u32 deactivate_lat_worst;
153 int (*deactivate_func)(struct omap_device *od);
154 u32 activate_lat;
155 u32 activate_lat_worst;
156 int (*activate_func)(struct omap_device *od);
157 u32 flags;
158};
159
160#define OMAP_DEVICE_LATENCY_AUTO_ADJUST BIT(1)
161
162/* Get omap_device pointer from platform_device pointer */
163static inline struct omap_device *to_omap_device(struct platform_device *pdev)
164{
165 return pdev ? pdev->archdata.od : NULL;
166}
167
168static inline
169void omap_device_disable_idle_on_suspend(struct platform_device *pdev)
170{
171 struct omap_device *od = to_omap_device(pdev);
172
173 od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND;
174}
175
176#endif
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
deleted file mode 100644
index b3349f7b1a2c..000000000000
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ /dev/null
@@ -1,676 +0,0 @@
1/*
2 * omap_hwmod macros, structures
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 *
8 * Created in collaboration with (alphabetical order): Benoît Cousson,
9 * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari
10 * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * These headers and macros are used to define OMAP on-chip module
17 * data and their integration with other OMAP modules and Linux.
18 * Copious documentation and references can also be found in the
19 * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this
20 * writing).
21 *
22 * To do:
23 * - add interconnect error log structures
24 * - add pinmuxing
25 * - init_conn_id_bit (CONNID_BIT_VECTOR)
26 * - implement default hwmod SMS/SDRC flags?
27 * - move Linux-specific data ("non-ROM data") out
28 *
29 */
30#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
31#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
32
33#include <linux/kernel.h>
34#include <linux/init.h>
35#include <linux/list.h>
36#include <linux/ioport.h>
37#include <linux/spinlock.h>
38#include <plat/cpu.h>
39
40struct omap_device;
41
42extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1;
43extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
44extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3;
45
46/*
47 * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant
48 * with the original PRCM protocol defined for OMAP2420
49 */
50#define SYSC_TYPE1_MIDLEMODE_SHIFT 12
51#define SYSC_TYPE1_MIDLEMODE_MASK (0x3 << SYSC_TYPE1_MIDLEMODE_SHIFT)
52#define SYSC_TYPE1_CLOCKACTIVITY_SHIFT 8
53#define SYSC_TYPE1_CLOCKACTIVITY_MASK (0x3 << SYSC_TYPE1_CLOCKACTIVITY_SHIFT)
54#define SYSC_TYPE1_SIDLEMODE_SHIFT 3
55#define SYSC_TYPE1_SIDLEMODE_MASK (0x3 << SYSC_TYPE1_SIDLEMODE_SHIFT)
56#define SYSC_TYPE1_ENAWAKEUP_SHIFT 2
57#define SYSC_TYPE1_ENAWAKEUP_MASK (1 << SYSC_TYPE1_ENAWAKEUP_SHIFT)
58#define SYSC_TYPE1_SOFTRESET_SHIFT 1
59#define SYSC_TYPE1_SOFTRESET_MASK (1 << SYSC_TYPE1_SOFTRESET_SHIFT)
60#define SYSC_TYPE1_AUTOIDLE_SHIFT 0
61#define SYSC_TYPE1_AUTOIDLE_MASK (1 << SYSC_TYPE1_AUTOIDLE_SHIFT)
62
63/*
64 * OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant
65 * with the new PRCM protocol defined for new OMAP4 IPs.
66 */
67#define SYSC_TYPE2_SOFTRESET_SHIFT 0
68#define SYSC_TYPE2_SOFTRESET_MASK (1 << SYSC_TYPE2_SOFTRESET_SHIFT)
69#define SYSC_TYPE2_SIDLEMODE_SHIFT 2
70#define SYSC_TYPE2_SIDLEMODE_MASK (0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT)
71#define SYSC_TYPE2_MIDLEMODE_SHIFT 4
72#define SYSC_TYPE2_MIDLEMODE_MASK (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT)
73#define SYSC_TYPE2_DMADISABLE_SHIFT 16
74#define SYSC_TYPE2_DMADISABLE_MASK (0x1 << SYSC_TYPE2_DMADISABLE_SHIFT)
75
76/*
77 * OCP SYSCONFIG bit shifts/masks TYPE3.
78 * This is applicable for some IPs present in AM33XX
79 */
80#define SYSC_TYPE3_SIDLEMODE_SHIFT 0
81#define SYSC_TYPE3_SIDLEMODE_MASK (0x3 << SYSC_TYPE3_SIDLEMODE_SHIFT)
82#define SYSC_TYPE3_MIDLEMODE_SHIFT 2
83#define SYSC_TYPE3_MIDLEMODE_MASK (0x3 << SYSC_TYPE3_MIDLEMODE_SHIFT)
84
85/* OCP SYSSTATUS bit shifts/masks */
86#define SYSS_RESETDONE_SHIFT 0
87#define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT)
88
89/* Master standby/slave idle mode flags */
90#define HWMOD_IDLEMODE_FORCE (1 << 0)
91#define HWMOD_IDLEMODE_NO (1 << 1)
92#define HWMOD_IDLEMODE_SMART (1 << 2)
93#define HWMOD_IDLEMODE_SMART_WKUP (1 << 3)
94
95/* modulemode control type (SW or HW) */
96#define MODULEMODE_HWCTRL 1
97#define MODULEMODE_SWCTRL 2
98
99
100/**
101 * struct omap_hwmod_mux_info - hwmod specific mux configuration
102 * @pads: array of omap_device_pad entries
103 * @nr_pads: number of omap_device_pad entries
104 *
105 * Note that this is currently built during init as needed.
106 */
107struct omap_hwmod_mux_info {
108 int nr_pads;
109 struct omap_device_pad *pads;
110 int nr_pads_dynamic;
111 struct omap_device_pad **pads_dynamic;
112 int *irqs;
113 bool enabled;
114};
115
116/**
117 * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
118 * @name: name of the IRQ channel (module local name)
119 * @irq: IRQ channel ID (should be non-negative except -1 = terminator)
120 *
121 * @name should be something short, e.g., "tx" or "rx". It is for use
122 * by platform_get_resource_byname(). It is defined locally to the
123 * hwmod.
124 */
125struct omap_hwmod_irq_info {
126 const char *name;
127 s16 irq;
128};
129
130/**
131 * struct omap_hwmod_dma_info - DMA channels used by the hwmod
132 * @name: name of the DMA channel (module local name)
133 * @dma_req: DMA request ID (should be non-negative except -1 = terminator)
134 *
135 * @name should be something short, e.g., "tx" or "rx". It is for use
136 * by platform_get_resource_byname(). It is defined locally to the
137 * hwmod.
138 */
139struct omap_hwmod_dma_info {
140 const char *name;
141 s16 dma_req;
142};
143
144/**
145 * struct omap_hwmod_rst_info - IPs reset lines use by hwmod
146 * @name: name of the reset line (module local name)
147 * @rst_shift: Offset of the reset bit
148 * @st_shift: Offset of the reset status bit (OMAP2/3 only)
149 *
150 * @name should be something short, e.g., "cpu0" or "rst". It is defined
151 * locally to the hwmod.
152 */
153struct omap_hwmod_rst_info {
154 const char *name;
155 u8 rst_shift;
156 u8 st_shift;
157};
158
159/**
160 * struct omap_hwmod_opt_clk - optional clocks used by this hwmod
161 * @role: "sys", "32k", "tv", etc -- for use in clk_get()
162 * @clk: opt clock: OMAP clock name
163 * @_clk: pointer to the struct clk (filled in at runtime)
164 *
165 * The module's interface clock and main functional clock should not
166 * be added as optional clocks.
167 */
168struct omap_hwmod_opt_clk {
169 const char *role;
170 const char *clk;
171 struct clk *_clk;
172};
173
174
175/* omap_hwmod_omap2_firewall.flags bits */
176#define OMAP_FIREWALL_L3 (1 << 0)
177#define OMAP_FIREWALL_L4 (1 << 1)
178
179/**
180 * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data
181 * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_*
182 * @l4_fw_region: L4 firewall region ID
183 * @l4_prot_group: L4 protection group ID
184 * @flags: (see omap_hwmod_omap2_firewall.flags macros above)
185 */
186struct omap_hwmod_omap2_firewall {
187 u8 l3_perm_bit;
188 u8 l4_fw_region;
189 u8 l4_prot_group;
190 u8 flags;
191};
192
193
194/*
195 * omap_hwmod_addr_space.flags bits
196 *
197 * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init.
198 * ADDR_TYPE_RT: Address space contains module register target data.
199 */
200#define ADDR_MAP_ON_INIT (1 << 0) /* XXX does not belong */
201#define ADDR_TYPE_RT (1 << 1)
202
203/**
204 * struct omap_hwmod_addr_space - address space handled by the hwmod
205 * @name: name of the address space
206 * @pa_start: starting physical address
207 * @pa_end: ending physical address
208 * @flags: (see omap_hwmod_addr_space.flags macros above)
209 *
210 * Address space doesn't necessarily follow physical interconnect
211 * structure. GPMC is one example.
212 */
213struct omap_hwmod_addr_space {
214 const char *name;
215 u32 pa_start;
216 u32 pa_end;
217 u8 flags;
218};
219
220
221/*
222 * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this
223 * interface to interact with the hwmod. Used to add sleep dependencies
224 * when the module is enabled or disabled.
225 */
226#define OCP_USER_MPU (1 << 0)
227#define OCP_USER_SDMA (1 << 1)
228#define OCP_USER_DSP (1 << 2)
229#define OCP_USER_IVA (1 << 3)
230
231/* omap_hwmod_ocp_if.flags bits */
232#define OCPIF_SWSUP_IDLE (1 << 0)
233#define OCPIF_CAN_BURST (1 << 1)
234
235/* omap_hwmod_ocp_if._int_flags possibilities */
236#define _OCPIF_INT_FLAGS_REGISTERED (1 << 0)
237
238
239/**
240 * struct omap_hwmod_ocp_if - OCP interface data
241 * @master: struct omap_hwmod that initiates OCP transactions on this link
242 * @slave: struct omap_hwmod that responds to OCP transactions on this link
243 * @addr: address space associated with this link
244 * @clk: interface clock: OMAP clock name
245 * @_clk: pointer to the interface struct clk (filled in at runtime)
246 * @fw: interface firewall data
247 * @width: OCP data width
248 * @user: initiators using this interface (see OCP_USER_* macros above)
249 * @flags: OCP interface flags (see OCPIF_* macros above)
250 * @_int_flags: internal flags (see _OCPIF_INT_FLAGS* macros above)
251 *
252 * It may also be useful to add a tag_cnt field for OCP2.x devices.
253 *
254 * Parameter names beginning with an underscore are managed internally by
255 * the omap_hwmod code and should not be set during initialization.
256 */
257struct omap_hwmod_ocp_if {
258 struct omap_hwmod *master;
259 struct omap_hwmod *slave;
260 struct omap_hwmod_addr_space *addr;
261 const char *clk;
262 struct clk *_clk;
263 union {
264 struct omap_hwmod_omap2_firewall omap2;
265 } fw;
266 u8 width;
267 u8 user;
268 u8 flags;
269 u8 _int_flags;
270};
271
272
273/* Macros for use in struct omap_hwmod_sysconfig */
274
275/* Flags for use in omap_hwmod_sysconfig.idlemodes */
276#define MASTER_STANDBY_SHIFT 4
277#define SLAVE_IDLE_SHIFT 0
278#define SIDLE_FORCE (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT)
279#define SIDLE_NO (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT)
280#define SIDLE_SMART (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT)
281#define SIDLE_SMART_WKUP (HWMOD_IDLEMODE_SMART_WKUP << SLAVE_IDLE_SHIFT)
282#define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
283#define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
284#define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
285#define MSTANDBY_SMART_WKUP (HWMOD_IDLEMODE_SMART_WKUP << MASTER_STANDBY_SHIFT)
286
287/* omap_hwmod_sysconfig.sysc_flags capability flags */
288#define SYSC_HAS_AUTOIDLE (1 << 0)
289#define SYSC_HAS_SOFTRESET (1 << 1)
290#define SYSC_HAS_ENAWAKEUP (1 << 2)
291#define SYSC_HAS_EMUFREE (1 << 3)
292#define SYSC_HAS_CLOCKACTIVITY (1 << 4)
293#define SYSC_HAS_SIDLEMODE (1 << 5)
294#define SYSC_HAS_MIDLEMODE (1 << 6)
295#define SYSS_HAS_RESET_STATUS (1 << 7)
296#define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */
297#define SYSC_HAS_RESET_STATUS (1 << 9)
298#define SYSC_HAS_DMADISABLE (1 << 10)
299
300/* omap_hwmod_sysconfig.clockact flags */
301#define CLOCKACT_TEST_BOTH 0x0
302#define CLOCKACT_TEST_MAIN 0x1
303#define CLOCKACT_TEST_ICLK 0x2
304#define CLOCKACT_TEST_NONE 0x3
305
306/**
307 * struct omap_hwmod_sysc_fields - hwmod OCP_SYSCONFIG register field offsets.
308 * @midle_shift: Offset of the midle bit
309 * @clkact_shift: Offset of the clockactivity bit
310 * @sidle_shift: Offset of the sidle bit
311 * @enwkup_shift: Offset of the enawakeup bit
312 * @srst_shift: Offset of the softreset bit
313 * @autoidle_shift: Offset of the autoidle bit
314 * @dmadisable_shift: Offset of the dmadisable bit
315 */
316struct omap_hwmod_sysc_fields {
317 u8 midle_shift;
318 u8 clkact_shift;
319 u8 sidle_shift;
320 u8 enwkup_shift;
321 u8 srst_shift;
322 u8 autoidle_shift;
323 u8 dmadisable_shift;
324};
325
326/**
327 * struct omap_hwmod_class_sysconfig - hwmod class OCP_SYS* data
328 * @rev_offs: IP block revision register offset (from module base addr)
329 * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
330 * @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
331 * @srst_udelay: Delay needed after doing a softreset in usecs
332 * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
333 * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
334 * @clockact: the default value of the module CLOCKACTIVITY bits
335 *
336 * @clockact describes to the module which clocks are likely to be
337 * disabled when the PRCM issues its idle request to the module. Some
338 * modules have separate clockdomains for the interface clock and main
339 * functional clock, and can check whether they should acknowledge the
340 * idle request based on the internal module functionality that has
341 * been associated with the clocks marked in @clockact. This field is
342 * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below)
343 *
344 * @sysc_fields: structure containing the offset positions of various bits in
345 * SYSCONFIG register. This can be populated using omap_hwmod_sysc_type1 or
346 * omap_hwmod_sysc_type2 defined in omap_hwmod_common_data.c depending on
347 * whether the device ip is compliant with the original PRCM protocol
348 * defined for OMAP2420 or the new PRCM protocol for new OMAP4 IPs.
349 * If the device follows a different scheme for the sysconfig register ,
350 * then this field has to be populated with the correct offset structure.
351 */
352struct omap_hwmod_class_sysconfig {
353 u32 rev_offs;
354 u32 sysc_offs;
355 u32 syss_offs;
356 u16 sysc_flags;
357 struct omap_hwmod_sysc_fields *sysc_fields;
358 u8 srst_udelay;
359 u8 idlemodes;
360 u8 clockact;
361};
362
363/**
364 * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data
365 * @module_offs: PRCM submodule offset from the start of the PRM/CM
366 * @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3)
367 * @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs
368 * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3)
369 * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit
370 * @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit
371 *
372 * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST,
373 * WKEN, GRPSEL registers. In an ideal world, no extra information
374 * would be needed for IDLEST information, but alas, there are some
375 * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit
376 * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST)
377 */
378struct omap_hwmod_omap2_prcm {
379 s16 module_offs;
380 u8 prcm_reg_id;
381 u8 module_bit;
382 u8 idlest_reg_id;
383 u8 idlest_idle_bit;
384 u8 idlest_stdby_bit;
385};
386
387/*
388 * Possible values for struct omap_hwmod_omap4_prcm.flags
389 *
390 * HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT: Some IP blocks don't have a PRCM
391 * module-level context loss register associated with them; this
392 * flag bit should be set in those cases
393 */
394#define HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT (1 << 0)
395
396/**
397 * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
398 * @clkctrl_reg: PRCM address of the clock control register
399 * @rstctrl_reg: address of the XXX_RSTCTRL register located in the PRM
400 * @lostcontext_mask: bitmask for selecting bits from RM_*_CONTEXT register
401 * @rstst_reg: (AM33XX only) address of the XXX_RSTST register in the PRM
402 * @submodule_wkdep_bit: bit shift of the WKDEP range
403 * @flags: PRCM register capabilities for this IP block
404 *
405 * If @lostcontext_mask is not defined, context loss check code uses
406 * whole register without masking. @lostcontext_mask should only be
407 * defined in cases where @context_offs register is shared by two or
408 * more hwmods.
409 */
410struct omap_hwmod_omap4_prcm {
411 u16 clkctrl_offs;
412 u16 rstctrl_offs;
413 u16 rstst_offs;
414 u16 context_offs;
415 u32 lostcontext_mask;
416 u8 submodule_wkdep_bit;
417 u8 modulemode;
418 u8 flags;
419};
420
421
422/*
423 * omap_hwmod.flags definitions
424 *
425 * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
426 * of idle, rather than relying on module smart-idle
427 * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
428 * of standby, rather than relying on module smart-standby
429 * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
430 * SDRAM controller, etc. XXX probably belongs outside the main hwmod file
431 * XXX Should be HWMOD_SETUP_NO_RESET
432 * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
433 * controller, etc. XXX probably belongs outside the main hwmod file
434 * XXX Should be HWMOD_SETUP_NO_IDLE
435 * HWMOD_NO_OCP_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
436 * when module is enabled, rather than the default, which is to
437 * enable autoidle
438 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
439 * HWMOD_NO_IDLEST: this module does not have idle status - this is the case
440 * only for few initiator modules on OMAP2 & 3.
441 * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset.
442 * This is needed for devices like DSS that require optional clocks enabled
443 * in order to complete the reset. Optional clocks will be disabled
444 * again after the reset.
445 * HWMOD_16BIT_REG: Module has 16bit registers
446 */
447#define HWMOD_SWSUP_SIDLE (1 << 0)
448#define HWMOD_SWSUP_MSTANDBY (1 << 1)
449#define HWMOD_INIT_NO_RESET (1 << 2)
450#define HWMOD_INIT_NO_IDLE (1 << 3)
451#define HWMOD_NO_OCP_AUTOIDLE (1 << 4)
452#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5)
453#define HWMOD_NO_IDLEST (1 << 6)
454#define HWMOD_CONTROL_OPT_CLKS_IN_RESET (1 << 7)
455#define HWMOD_16BIT_REG (1 << 8)
456
457/*
458 * omap_hwmod._int_flags definitions
459 * These are for internal use only and are managed by the omap_hwmod code.
460 *
461 * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
462 * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
463 * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
464 * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) -
465 * causes the first call to _enable() to only update the pinmux
466 */
467#define _HWMOD_NO_MPU_PORT (1 << 0)
468#define _HWMOD_WAKEUP_ENABLED (1 << 1)
469#define _HWMOD_SYSCONFIG_LOADED (1 << 2)
470#define _HWMOD_SKIP_ENABLE (1 << 3)
471
472/*
473 * omap_hwmod._state definitions
474 *
475 * INITIALIZED: reset (optionally), initialized, enabled, disabled
476 * (optionally)
477 *
478 *
479 */
480#define _HWMOD_STATE_UNKNOWN 0
481#define _HWMOD_STATE_REGISTERED 1
482#define _HWMOD_STATE_CLKS_INITED 2
483#define _HWMOD_STATE_INITIALIZED 3
484#define _HWMOD_STATE_ENABLED 4
485#define _HWMOD_STATE_IDLE 5
486#define _HWMOD_STATE_DISABLED 6
487
488/**
489 * struct omap_hwmod_class - the type of an IP block
490 * @name: name of the hwmod_class
491 * @sysc: device SYSCONFIG/SYSSTATUS register data
492 * @rev: revision of the IP class
493 * @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown
494 * @reset: ptr to fn to be executed in place of the standard hwmod reset fn
495 *
496 * Represent the class of a OMAP hardware "modules" (e.g. timer,
497 * smartreflex, gpio, uart...)
498 *
499 * @pre_shutdown is a function that will be run immediately before
500 * hwmod clocks are disabled, etc. It is intended for use for hwmods
501 * like the MPU watchdog, which cannot be disabled with the standard
502 * omap_hwmod_shutdown(). The function should return 0 upon success,
503 * or some negative error upon failure. Returning an error will cause
504 * omap_hwmod_shutdown() to abort the device shutdown and return an
505 * error.
506 *
507 * If @reset is defined, then the function it points to will be
508 * executed in place of the standard hwmod _reset() code in
509 * mach-omap2/omap_hwmod.c. This is needed for IP blocks which have
510 * unusual reset sequences - usually processor IP blocks like the IVA.
511 */
512struct omap_hwmod_class {
513 const char *name;
514 struct omap_hwmod_class_sysconfig *sysc;
515 u32 rev;
516 int (*pre_shutdown)(struct omap_hwmod *oh);
517 int (*reset)(struct omap_hwmod *oh);
518};
519
520/**
521 * struct omap_hwmod_link - internal structure linking hwmods with ocp_ifs
522 * @ocp_if: OCP interface structure record pointer
523 * @node: list_head pointing to next struct omap_hwmod_link in a list
524 */
525struct omap_hwmod_link {
526 struct omap_hwmod_ocp_if *ocp_if;
527 struct list_head node;
528};
529
530/**
531 * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
532 * @name: name of the hwmod
533 * @class: struct omap_hwmod_class * to the class of this hwmod
534 * @od: struct omap_device currently associated with this hwmod (internal use)
535 * @mpu_irqs: ptr to an array of MPU IRQs
536 * @sdma_reqs: ptr to an array of System DMA request IDs
537 * @prcm: PRCM data pertaining to this hwmod
538 * @main_clk: main clock: OMAP clock name
539 * @_clk: pointer to the main struct clk (filled in at runtime)
540 * @opt_clks: other device clocks that drivers can request (0..*)
541 * @voltdm: pointer to voltage domain (filled in at runtime)
542 * @dev_attr: arbitrary device attributes that can be passed to the driver
543 * @_sysc_cache: internal-use hwmod flags
544 * @_mpu_rt_va: cached register target start address (internal use)
545 * @_mpu_port: cached MPU register target slave (internal use)
546 * @opt_clks_cnt: number of @opt_clks
547 * @master_cnt: number of @master entries
548 * @slaves_cnt: number of @slave entries
549 * @response_lat: device OCP response latency (in interface clock cycles)
550 * @_int_flags: internal-use hwmod flags
551 * @_state: internal-use hwmod state
552 * @_postsetup_state: internal-use state to leave the hwmod in after _setup()
553 * @flags: hwmod flags (documented below)
554 * @_lock: spinlock serializing operations on this hwmod
555 * @node: list node for hwmod list (internal use)
556 *
557 * @main_clk refers to this module's "main clock," which for our
558 * purposes is defined as "the functional clock needed for register
559 * accesses to complete." Modules may not have a main clock if the
560 * interface clock also serves as a main clock.
561 *
562 * Parameter names beginning with an underscore are managed internally by
563 * the omap_hwmod code and should not be set during initialization.
564 *
565 * @masters and @slaves are now deprecated.
566 */
567struct omap_hwmod {
568 const char *name;
569 struct omap_hwmod_class *class;
570 struct omap_device *od;
571 struct omap_hwmod_mux_info *mux;
572 struct omap_hwmod_irq_info *mpu_irqs;
573 struct omap_hwmod_dma_info *sdma_reqs;
574 struct omap_hwmod_rst_info *rst_lines;
575 union {
576 struct omap_hwmod_omap2_prcm omap2;
577 struct omap_hwmod_omap4_prcm omap4;
578 } prcm;
579 const char *main_clk;
580 struct clk *_clk;
581 struct omap_hwmod_opt_clk *opt_clks;
582 char *clkdm_name;
583 struct clockdomain *clkdm;
584 struct list_head master_ports; /* connect to *_IA */
585 struct list_head slave_ports; /* connect to *_TA */
586 void *dev_attr;
587 u32 _sysc_cache;
588 void __iomem *_mpu_rt_va;
589 spinlock_t _lock;
590 struct list_head node;
591 struct omap_hwmod_ocp_if *_mpu_port;
592 u16 flags;
593 u8 response_lat;
594 u8 rst_lines_cnt;
595 u8 opt_clks_cnt;
596 u8 masters_cnt;
597 u8 slaves_cnt;
598 u8 hwmods_cnt;
599 u8 _int_flags;
600 u8 _state;
601 u8 _postsetup_state;
602};
603
604struct omap_hwmod *omap_hwmod_lookup(const char *name);
605int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
606 void *data);
607
608int __init omap_hwmod_setup_one(const char *name);
609
610int omap_hwmod_enable(struct omap_hwmod *oh);
611int omap_hwmod_idle(struct omap_hwmod *oh);
612int omap_hwmod_shutdown(struct omap_hwmod *oh);
613
614int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name);
615int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name);
616int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name);
617
618int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
619int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
620
621int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode);
622int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle);
623
624int omap_hwmod_reset(struct omap_hwmod *oh);
625void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
626
627void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
628u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
629int omap_hwmod_softreset(struct omap_hwmod *oh);
630
631int omap_hwmod_count_resources(struct omap_hwmod *oh);
632int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
633int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res);
634int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
635 const char *name, struct resource *res);
636
637struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
638void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh);
639
640int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
641 struct omap_hwmod *init_oh);
642int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
643 struct omap_hwmod *init_oh);
644
645int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
646int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
647
648int omap_hwmod_for_each_by_class(const char *classname,
649 int (*fn)(struct omap_hwmod *oh,
650 void *user),
651 void *user);
652
653int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state);
654int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
655
656int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);
657
658int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx);
659
660extern void __init omap_hwmod_init(void);
661
662const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh);
663
664/*
665 * Chip variant-specific hwmod init routines - XXX should be converted
666 * to use initcalls once the initial boot ordering is straightened out
667 */
668extern int omap2420_hwmod_init(void);
669extern int omap2430_hwmod_init(void);
670extern int omap3xxx_hwmod_init(void);
671extern int omap44xx_hwmod_init(void);
672extern int am33xx_hwmod_init(void);
673
674extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
675
676#endif
diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
deleted file mode 100644
index 36d6a7666216..000000000000
--- a/arch/arm/plat-omap/include/plat/sdrc.h
+++ /dev/null
@@ -1,164 +0,0 @@
1#ifndef ____ASM_ARCH_SDRC_H
2#define ____ASM_ARCH_SDRC_H
3
4/*
5 * OMAP2/3 SDRC/SMS register definitions
6 *
7 * Copyright (C) 2007-2008 Texas Instruments, Inc.
8 * Copyright (C) 2007-2008 Nokia Corporation
9 *
10 * Tony Lindgren
11 * Paul Walmsley
12 * Richard Woodruff
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19
20/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
21
22#define SDRC_SYSCONFIG 0x010
23#define SDRC_CS_CFG 0x040
24#define SDRC_SHARING 0x044
25#define SDRC_ERR_TYPE 0x04C
26#define SDRC_DLLA_CTRL 0x060
27#define SDRC_DLLA_STATUS 0x064
28#define SDRC_DLLB_CTRL 0x068
29#define SDRC_DLLB_STATUS 0x06C
30#define SDRC_POWER 0x070
31#define SDRC_MCFG_0 0x080
32#define SDRC_MR_0 0x084
33#define SDRC_EMR2_0 0x08c
34#define SDRC_ACTIM_CTRL_A_0 0x09c
35#define SDRC_ACTIM_CTRL_B_0 0x0a0
36#define SDRC_RFR_CTRL_0 0x0a4
37#define SDRC_MANUAL_0 0x0a8
38#define SDRC_MCFG_1 0x0B0
39#define SDRC_MR_1 0x0B4
40#define SDRC_EMR2_1 0x0BC
41#define SDRC_ACTIM_CTRL_A_1 0x0C4
42#define SDRC_ACTIM_CTRL_B_1 0x0C8
43#define SDRC_RFR_CTRL_1 0x0D4
44#define SDRC_MANUAL_1 0x0D8
45
46#define SDRC_POWER_AUTOCOUNT_SHIFT 8
47#define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
48#define SDRC_POWER_CLKCTRL_SHIFT 4
49#define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
50#define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
51
52/*
53 * These values represent the number of memory clock cycles between
54 * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
55 * rows per device, and include a subtraction of a 50 cycle window in the
56 * event that the autorefresh command is delayed due to other SDRC activity.
57 * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
58 * counter reaches 0.
59 *
60 * These represent optimal values for common parts, it won't work for all.
61 * As long as you scale down, most parameters are still work, they just
62 * become sub-optimal. The RFR value goes in the opposite direction. If you
63 * don't adjust it down as your clock period increases the refresh interval
64 * will not be met. Setting all parameters for complete worst case may work,
65 * but may cut memory performance by 2x. Due to errata the DLLs need to be
66 * unlocked and their value needs run time calibration. A dynamic call is
67 * need for that as no single right value exists acorss production samples.
68 *
69 * Only the FULL speed values are given. Current code is such that rate
70 * changes must be made at DPLLoutx2. The actual value adjustment for low
71 * frequency operation will be handled by omap_set_performance()
72 *
73 * By having the boot loader boot up in the fastest L4 speed available likely
74 * will result in something which you can switch between.
75 */
76#define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1)
77#define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
78#define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
79#define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
80#define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
81
82
83/*
84 * SMS register access
85 */
86
87#define OMAP242X_SMS_REGADDR(reg) \
88 (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
89#define OMAP243X_SMS_REGADDR(reg) \
90 (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
91#define OMAP343X_SMS_REGADDR(reg) \
92 (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
93
94/* SMS register offsets - read/write with sms_{read,write}_reg() */
95
96#define SMS_SYSCONFIG 0x010
97#define SMS_ROT_CONTROL(context) (0x180 + 0x10 * context)
98#define SMS_ROT_SIZE(context) (0x184 + 0x10 * context)
99#define SMS_ROT_PHYSICAL_BA(context) (0x188 + 0x10 * context)
100/* REVISIT: fill in other SMS registers here */
101
102
103#ifndef __ASSEMBLER__
104
105/**
106 * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
107 * @rate: SDRC clock rate (in Hz)
108 * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
109 * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
110 * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
111 * @mr: Value to program to SDRC_MR for this rate
112 *
113 * This structure holds a pre-computed set of register values for the
114 * SDRC for a given SDRC clock rate and SDRAM chip. These are
115 * intended to be pre-computed and specified in an array in the board-*.c
116 * files. The structure is keyed off the 'rate' field.
117 */
118struct omap_sdrc_params {
119 unsigned long rate;
120 u32 actim_ctrla;
121 u32 actim_ctrlb;
122 u32 rfr_ctrl;
123 u32 mr;
124};
125
126#ifdef CONFIG_SOC_HAS_OMAP2_SDRC
127void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
128 struct omap_sdrc_params *sdrc_cs1);
129#else
130static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
131 struct omap_sdrc_params *sdrc_cs1) {};
132#endif
133
134int omap2_sdrc_get_params(unsigned long r,
135 struct omap_sdrc_params **sdrc_cs0,
136 struct omap_sdrc_params **sdrc_cs1);
137void omap2_sms_save_context(void);
138void omap2_sms_restore_context(void);
139
140void omap2_sms_write_rot_control(u32 val, unsigned ctx);
141void omap2_sms_write_rot_size(u32 val, unsigned ctx);
142void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx);
143
144#ifdef CONFIG_ARCH_OMAP2
145
146struct memory_timings {
147 u32 m_type; /* ddr = 1, sdr = 0 */
148 u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
149 u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
150 u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
151 u32 base_cs; /* base chip select to use for calculations */
152};
153
154extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
155struct omap_sdrc_params *rx51_get_sdram_timings(void);
156
157u32 omap2xxx_sdrc_dll_is_unlocked(void);
158u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
159
160#endif /* CONFIG_ARCH_OMAP2 */
161
162#endif /* __ASSEMBLER__ */
163
164#endif
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
deleted file mode 100644
index 65fce44dce34..000000000000
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ /dev/null
@@ -1,132 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/serial.h
3 *
4 * Copyright (C) 2009 Texas Instruments
5 * Added OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __ASM_ARCH_SERIAL_H
14#define __ASM_ARCH_SERIAL_H
15
16#include <linux/init.h>
17
18/*
19 * Memory entry used for the DEBUG_LL UART configuration, relative to
20 * start of RAM. See also uncompress.h and debug-macro.S.
21 *
22 * Note that using a memory location for storing the UART configuration
23 * has at least two limitations:
24 *
25 * 1. Kernel uncompress code cannot overlap OMAP_UART_INFO as the
26 * uncompress code could then partially overwrite itself
27 * 2. We assume printascii is called at least once before paging_init,
28 * and addruart has a chance to read OMAP_UART_INFO
29 */
30#define OMAP_UART_INFO_OFS 0x3ffc
31
32/* OMAP1 serial ports */
33#define OMAP1_UART1_BASE 0xfffb0000
34#define OMAP1_UART2_BASE 0xfffb0800
35#define OMAP1_UART3_BASE 0xfffb9800
36
37/* OMAP2 serial ports */
38#define OMAP2_UART1_BASE 0x4806a000
39#define OMAP2_UART2_BASE 0x4806c000
40#define OMAP2_UART3_BASE 0x4806e000
41
42/* OMAP3 serial ports */
43#define OMAP3_UART1_BASE OMAP2_UART1_BASE
44#define OMAP3_UART2_BASE OMAP2_UART2_BASE
45#define OMAP3_UART3_BASE 0x49020000
46#define OMAP3_UART4_BASE 0x49042000 /* Only on 36xx */
47#define OMAP3_UART4_AM35XX_BASE 0x4809E000 /* Only on AM35xx */
48
49/* OMAP4 serial ports */
50#define OMAP4_UART1_BASE OMAP2_UART1_BASE
51#define OMAP4_UART2_BASE OMAP2_UART2_BASE
52#define OMAP4_UART3_BASE 0x48020000
53#define OMAP4_UART4_BASE 0x4806e000
54
55/* TI81XX serial ports */
56#define TI81XX_UART1_BASE 0x48020000
57#define TI81XX_UART2_BASE 0x48022000
58#define TI81XX_UART3_BASE 0x48024000
59
60/* AM3505/3517 UART4 */
61#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
62
63/* AM33XX serial port */
64#define AM33XX_UART1_BASE 0x44E09000
65
66/* OMAP5 serial ports */
67#define OMAP5_UART1_BASE OMAP2_UART1_BASE
68#define OMAP5_UART2_BASE OMAP2_UART2_BASE
69#define OMAP5_UART3_BASE OMAP4_UART3_BASE
70#define OMAP5_UART4_BASE OMAP4_UART4_BASE
71#define OMAP5_UART5_BASE 0x48066000
72#define OMAP5_UART6_BASE 0x48068000
73
74/* External port on Zoom2/3 */
75#define ZOOM_UART_BASE 0x10000000
76#define ZOOM_UART_VIRT 0xfa400000
77
78#define OMAP_PORT_SHIFT 2
79#define OMAP7XX_PORT_SHIFT 0
80#define ZOOM_PORT_SHIFT 1
81
82#define OMAP1510_BASE_BAUD (12000000/16)
83#define OMAP16XX_BASE_BAUD (48000000/16)
84#define OMAP24XX_BASE_BAUD (48000000/16)
85
86/*
87 * DEBUG_LL port encoding stored into the UART1 scratchpad register by
88 * decomp_setup in uncompress.h
89 */
90#define OMAP1UART1 11
91#define OMAP1UART2 12
92#define OMAP1UART3 13
93#define OMAP2UART1 21
94#define OMAP2UART2 22
95#define OMAP2UART3 23
96#define OMAP3UART1 OMAP2UART1
97#define OMAP3UART2 OMAP2UART2
98#define OMAP3UART3 33
99#define OMAP3UART4 34 /* Only on 36xx */
100#define OMAP4UART1 OMAP2UART1
101#define OMAP4UART2 OMAP2UART2
102#define OMAP4UART3 43
103#define OMAP4UART4 44
104#define TI81XXUART1 81
105#define TI81XXUART2 82
106#define TI81XXUART3 83
107#define AM33XXUART1 84
108#define OMAP5UART3 OMAP4UART3
109#define OMAP5UART4 OMAP4UART4
110#define ZOOM_UART 95 /* Only on zoom2/3 */
111
112/* This is only used by 8250.c for omap1510 */
113#define is_omap_port(pt) ({int __ret = 0; \
114 if ((pt)->port.mapbase == OMAP1_UART1_BASE || \
115 (pt)->port.mapbase == OMAP1_UART2_BASE || \
116 (pt)->port.mapbase == OMAP1_UART3_BASE) \
117 __ret = 1; \
118 __ret; \
119 })
120
121#ifndef __ASSEMBLER__
122
123struct omap_board_data;
124struct omap_uart_port_info;
125
126extern void omap_serial_init(void);
127extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
128extern void omap_serial_init_port(struct omap_board_data *bdata,
129 struct omap_uart_port_info *platform_data);
130#endif
131
132#endif
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 227ae2657554..ba4525059a99 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -1,18 +1,8 @@
1/* 1int omap_sram_init(void);
2 * arch/arm/plat-omap/include/mach/sram.h
3 *
4 * Interface for functions that need to be run in internal SRAM
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 2
11#ifndef __ARCH_ARM_OMAP_SRAM_H 3void omap_map_sram(unsigned long start, unsigned long size,
12#define __ARCH_ARM_OMAP_SRAM_H 4 unsigned long skip, int cached);
13 5void omap_sram_reset(void);
14#ifndef __ASSEMBLY__
15#include <asm/fncpy.h>
16 6
17extern void *omap_sram_push_address(unsigned long size); 7extern void *omap_sram_push_address(unsigned long size);
18 8
@@ -24,82 +14,3 @@ extern void *omap_sram_push_address(unsigned long size);
24 _res = fncpy(_sram_address, &(funcp), size); \ 14 _res = fncpy(_sram_address, &(funcp), size); \
25 _res; \ 15 _res; \
26}) 16})
27
28extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
29
30extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
31 u32 base_cs, u32 force_unlock);
32extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
33 u32 mem_type);
34extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
35
36extern u32 omap3_configure_core_dpll(
37 u32 m2, u32 unlock_dll, u32 f, u32 inc,
38 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
39 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
40 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
41 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
42extern void omap3_sram_restore_context(void);
43
44/* Do not use these */
45extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
46extern unsigned long omap1_sram_reprogram_clock_sz;
47
48extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
49extern unsigned long omap24xx_sram_reprogram_clock_sz;
50
51extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
52 u32 base_cs, u32 force_unlock);
53extern unsigned long omap242x_sram_ddr_init_sz;
54
55extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
56 int bypass);
57extern unsigned long omap242x_sram_set_prcm_sz;
58
59extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
60 u32 mem_type);
61extern unsigned long omap242x_sram_reprogram_sdrc_sz;
62
63
64extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
65 u32 base_cs, u32 force_unlock);
66extern unsigned long omap243x_sram_ddr_init_sz;
67
68extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
69 int bypass);
70extern unsigned long omap243x_sram_set_prcm_sz;
71
72extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
73 u32 mem_type);
74extern unsigned long omap243x_sram_reprogram_sdrc_sz;
75
76extern u32 omap3_sram_configure_core_dpll(
77 u32 m2, u32 unlock_dll, u32 f, u32 inc,
78 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
79 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
80 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
81 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
82extern unsigned long omap3_sram_configure_core_dpll_sz;
83
84#ifdef CONFIG_PM
85extern void omap_push_sram_idle(void);
86#else
87static inline void omap_push_sram_idle(void) {}
88#endif /* CONFIG_PM */
89
90#endif /* __ASSEMBLY__ */
91
92/*
93 * OMAP2+: define the SRAM PA addresses.
94 * Used by the SRAM management code and the idle sleep code.
95 */
96#define OMAP2_SRAM_PA 0x40200000
97#define OMAP3_SRAM_PA 0x40200000
98#ifdef CONFIG_OMAP4_ERRATA_I688
99#define OMAP4_SRAM_PA 0x40304000
100#define OMAP4_SRAM_VA 0xfe404000
101#else
102#define OMAP4_SRAM_PA 0x40300000
103#endif
104#define AM33XX_SRAM_PA 0x40300000
105#endif
diff --git a/arch/arm/plat-omap/include/plat/tc.h b/arch/arm/plat-omap/include/plat/tc.h
deleted file mode 100644
index 1b4b2da86203..000000000000
--- a/arch/arm/plat-omap/include/plat/tc.h
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/tc.h
3 *
4 * OMAP Traffic Controller
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 * Author: Imre Deak <imre.deak@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#ifndef __ASM_ARCH_TC_H
25#define __ASM_ARCH_TC_H
26
27#define TCMIF_BASE 0xfffecc00
28#define OMAP_TC_OCPT1_PRIOR (TCMIF_BASE + 0x00)
29#define OMAP_TC_EMIFS_PRIOR (TCMIF_BASE + 0x04)
30#define OMAP_TC_EMIFF_PRIOR (TCMIF_BASE + 0x08)
31#define EMIFS_CONFIG (TCMIF_BASE + 0x0c)
32#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10)
33#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14)
34#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18)
35#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c)
36#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20)
37#define EMIFF_MRS (TCMIF_BASE + 0x24)
38#define TC_TIMEOUT1 (TCMIF_BASE + 0x28)
39#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c)
40#define TC_TIMEOUT3 (TCMIF_BASE + 0x30)
41#define TC_ENDIANISM (TCMIF_BASE + 0x34)
42#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c)
43#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40)
44#define EMIFS_ACS0 (TCMIF_BASE + 0x50)
45#define EMIFS_ACS1 (TCMIF_BASE + 0x54)
46#define EMIFS_ACS2 (TCMIF_BASE + 0x58)
47#define EMIFS_ACS3 (TCMIF_BASE + 0x5c)
48#define OMAP_TC_OCPT2_PRIOR (TCMIF_BASE + 0xd0)
49
50/* external EMIFS chipselect regions */
51#define OMAP_CS0_PHYS 0x00000000
52#define OMAP_CS0_SIZE SZ_64M
53
54#define OMAP_CS1_PHYS 0x04000000
55#define OMAP_CS1_SIZE SZ_64M
56
57#define OMAP_CS1A_PHYS OMAP_CS1_PHYS
58#define OMAP_CS1A_SIZE SZ_32M
59
60#define OMAP_CS1B_PHYS (OMAP_CS1A_PHYS + OMAP_CS1A_SIZE)
61#define OMAP_CS1B_SIZE SZ_32M
62
63#define OMAP_CS2_PHYS 0x08000000
64#define OMAP_CS2_SIZE SZ_64M
65
66#define OMAP_CS2A_PHYS OMAP_CS2_PHYS
67#define OMAP_CS2A_SIZE SZ_32M
68
69#define OMAP_CS2B_PHYS (OMAP_CS2A_PHYS + OMAP_CS2A_SIZE)
70#define OMAP_CS2B_SIZE SZ_32M
71
72#define OMAP_CS3_PHYS 0x0c000000
73#define OMAP_CS3_SIZE SZ_64M
74
75#ifndef __ASSEMBLER__
76
77/* EMIF Slow Interface Configuration Register */
78#define OMAP_EMIFS_CONFIG_FR (1 << 4)
79#define OMAP_EMIFS_CONFIG_PDE (1 << 3)
80#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2)
81#define OMAP_EMIFS_CONFIG_BM (1 << 1)
82#define OMAP_EMIFS_CONFIG_WP (1 << 0)
83
84#define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n)))
85#define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n)))
86
87#endif /* __ASSEMBLER__ */
88
89#endif /* __ASM_ARCH_TC_H */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
deleted file mode 100644
index 7f7b112acccb..000000000000
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ /dev/null
@@ -1,204 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/uncompress.h
3 *
4 * Serial port stubs for kernel decompress status messages
5 *
6 * Initially based on:
7 * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
8 * Copyright (C) 2000 RidgeRun, Inc.
9 * Author: Greg Lonnon <glonnon@ridgerun.com>
10 *
11 * Rewritten by:
12 * Author: <source@mvista.com>
13 * 2004 (c) MontaVista Software, Inc.
14 *
15 * This file is licensed under the terms of the GNU General Public License
16 * version 2. This program is licensed "as is" without any warranty of any
17 * kind, whether express or implied.
18 */
19
20#include <linux/types.h>
21#include <linux/serial_reg.h>
22
23#include <asm/memory.h>
24#include <asm/mach-types.h>
25
26#include <plat/serial.h>
27
28#define MDR1_MODE_MASK 0x07
29
30volatile u8 *uart_base;
31int uart_shift;
32
33/*
34 * Store the DEBUG_LL uart number into memory.
35 * See also debug-macro.S, and serial.c for related code.
36 */
37static void set_omap_uart_info(unsigned char port)
38{
39 /*
40 * Get address of some.bss variable and round it down
41 * a la CONFIG_AUTO_ZRELADDR.
42 */
43 u32 ram_start = (u32)&uart_shift & 0xf8000000;
44 u32 *uart_info = (u32 *)(ram_start + OMAP_UART_INFO_OFS);
45 *uart_info = port;
46}
47
48static void putc(int c)
49{
50 if (!uart_base)
51 return;
52
53 /* Check for UART 16x mode */
54 if ((uart_base[UART_OMAP_MDR1 << uart_shift] & MDR1_MODE_MASK) != 0)
55 return;
56
57 while (!(uart_base[UART_LSR << uart_shift] & UART_LSR_THRE))
58 barrier();
59 uart_base[UART_TX << uart_shift] = c;
60}
61
62static inline void flush(void)
63{
64}
65
66/*
67 * Macros to configure UART1 and debug UART
68 */
69#define _DEBUG_LL_ENTRY(mach, dbg_uart, dbg_shft, dbg_id) \
70 if (machine_is_##mach()) { \
71 uart_base = (volatile u8 *)(dbg_uart); \
72 uart_shift = (dbg_shft); \
73 port = (dbg_id); \
74 set_omap_uart_info(port); \
75 break; \
76 }
77
78#define DEBUG_LL_OMAP7XX(p, mach) \
79 _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP7XX_PORT_SHIFT, \
80 OMAP1UART##p)
81
82#define DEBUG_LL_OMAP1(p, mach) \
83 _DEBUG_LL_ENTRY(mach, OMAP1_UART##p##_BASE, OMAP_PORT_SHIFT, \
84 OMAP1UART##p)
85
86#define DEBUG_LL_OMAP2(p, mach) \
87 _DEBUG_LL_ENTRY(mach, OMAP2_UART##p##_BASE, OMAP_PORT_SHIFT, \
88 OMAP2UART##p)
89
90#define DEBUG_LL_OMAP3(p, mach) \
91 _DEBUG_LL_ENTRY(mach, OMAP3_UART##p##_BASE, OMAP_PORT_SHIFT, \
92 OMAP3UART##p)
93
94#define DEBUG_LL_OMAP4(p, mach) \
95 _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, \
96 OMAP4UART##p)
97
98#define DEBUG_LL_OMAP5(p, mach) \
99 _DEBUG_LL_ENTRY(mach, OMAP5_UART##p##_BASE, OMAP_PORT_SHIFT, \
100 OMAP5UART##p)
101/* Zoom2/3 shift is different for UART1 and external port */
102#define DEBUG_LL_ZOOM(mach) \
103 _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
104
105#define DEBUG_LL_TI81XX(p, mach) \
106 _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
107 TI81XXUART##p)
108
109#define DEBUG_LL_AM33XX(p, mach) \
110 _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
111 AM33XXUART##p)
112
113static inline void arch_decomp_setup(void)
114{
115 int port = 0;
116
117 /*
118 * Initialize the port based on the machine ID from the bootloader.
119 * Note that we're using macros here instead of switch statement
120 * as machine_is functions are optimized out for the boards that
121 * are not selected.
122 */
123 do {
124 /* omap7xx/8xx based boards using UART1 with shift 0 */
125 DEBUG_LL_OMAP7XX(1, herald);
126 DEBUG_LL_OMAP7XX(1, omap_perseus2);
127
128 /* omap15xx/16xx based boards using UART1 */
129 DEBUG_LL_OMAP1(1, ams_delta);
130 DEBUG_LL_OMAP1(1, nokia770);
131 DEBUG_LL_OMAP1(1, omap_h2);
132 DEBUG_LL_OMAP1(1, omap_h3);
133 DEBUG_LL_OMAP1(1, omap_innovator);
134 DEBUG_LL_OMAP1(1, omap_osk);
135 DEBUG_LL_OMAP1(1, omap_palmte);
136 DEBUG_LL_OMAP1(1, omap_palmz71);
137
138 /* omap15xx/16xx based boards using UART2 */
139 DEBUG_LL_OMAP1(2, omap_palmtt);
140
141 /* omap15xx/16xx based boards using UART3 */
142 DEBUG_LL_OMAP1(3, sx1);
143
144 /* omap2 based boards using UART1 */
145 DEBUG_LL_OMAP2(1, omap_2430sdp);
146 DEBUG_LL_OMAP2(1, omap_apollon);
147 DEBUG_LL_OMAP2(1, omap_h4);
148
149 /* omap2 based boards using UART3 */
150 DEBUG_LL_OMAP2(3, nokia_n800);
151 DEBUG_LL_OMAP2(3, nokia_n810);
152 DEBUG_LL_OMAP2(3, nokia_n810_wimax);
153
154 /* omap3 based boards using UART1 */
155 DEBUG_LL_OMAP2(1, omap3evm);
156 DEBUG_LL_OMAP3(1, omap_3430sdp);
157 DEBUG_LL_OMAP3(1, omap_3630sdp);
158 DEBUG_LL_OMAP3(1, omap3530_lv_som);
159 DEBUG_LL_OMAP3(1, omap3_torpedo);
160
161 /* omap3 based boards using UART3 */
162 DEBUG_LL_OMAP3(3, cm_t35);
163 DEBUG_LL_OMAP3(3, cm_t3517);
164 DEBUG_LL_OMAP3(3, cm_t3730);
165 DEBUG_LL_OMAP3(3, craneboard);
166 DEBUG_LL_OMAP3(3, devkit8000);
167 DEBUG_LL_OMAP3(3, igep0020);
168 DEBUG_LL_OMAP3(3, igep0030);
169 DEBUG_LL_OMAP3(3, nokia_rm680);
170 DEBUG_LL_OMAP3(3, nokia_rm696);
171 DEBUG_LL_OMAP3(3, nokia_rx51);
172 DEBUG_LL_OMAP3(3, omap3517evm);
173 DEBUG_LL_OMAP3(3, omap3_beagle);
174 DEBUG_LL_OMAP3(3, omap3_pandora);
175 DEBUG_LL_OMAP3(3, omap_ldp);
176 DEBUG_LL_OMAP3(3, overo);
177 DEBUG_LL_OMAP3(3, touchbook);
178
179 /* omap4 based boards using UART3 */
180 DEBUG_LL_OMAP4(3, omap_4430sdp);
181 DEBUG_LL_OMAP4(3, omap4_panda);
182
183 /* omap5 based boards using UART3 */
184 DEBUG_LL_OMAP5(3, omap5_sevm);
185
186 /* zoom2/3 external uart */
187 DEBUG_LL_ZOOM(omap_zoom2);
188 DEBUG_LL_ZOOM(omap_zoom3);
189
190 /* TI8168 base boards using UART3 */
191 DEBUG_LL_TI81XX(3, ti8168evm);
192
193 /* TI8148 base boards using UART1 */
194 DEBUG_LL_TI81XX(1, ti8148evm);
195
196 /* AM33XX base boards using UART1 */
197 DEBUG_LL_AM33XX(1, am335xevm);
198 } while (0);
199}
200
201/*
202 * nothing to do
203 */
204#define arch_decomp_wdog()
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
deleted file mode 100644
index 87ee140fefaa..000000000000
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ /dev/null
@@ -1,179 +0,0 @@
1// include/asm-arm/mach-omap/usb.h
2
3#ifndef __ASM_ARCH_OMAP_USB_H
4#define __ASM_ARCH_OMAP_USB_H
5
6#include <linux/io.h>
7#include <linux/platform_device.h>
8#include <linux/usb/musb.h>
9
10#define OMAP3_HS_USB_PORTS 3
11
12enum usbhs_omap_port_mode {
13 OMAP_USBHS_PORT_MODE_UNUSED,
14 OMAP_EHCI_PORT_MODE_PHY,
15 OMAP_EHCI_PORT_MODE_TLL,
16 OMAP_EHCI_PORT_MODE_HSIC,
17 OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
18 OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
19 OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
20 OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
21 OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
22 OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
23 OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
24 OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
25 OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
26 OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
27};
28
29struct usbhs_omap_board_data {
30 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
31
32 /* have to be valid if phy_reset is true and portx is in phy mode */
33 int reset_gpio_port[OMAP3_HS_USB_PORTS];
34
35 /* Set this to true for ES2.x silicon */
36 unsigned es2_compatibility:1;
37
38 unsigned phy_reset:1;
39
40 /*
41 * Regulators for USB PHYs.
42 * Each PHY can have a separate regulator.
43 */
44 struct regulator *regulator[OMAP3_HS_USB_PORTS];
45};
46
47#ifdef CONFIG_ARCH_OMAP2PLUS
48
49struct ehci_hcd_omap_platform_data {
50 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
51 int reset_gpio_port[OMAP3_HS_USB_PORTS];
52 struct regulator *regulator[OMAP3_HS_USB_PORTS];
53 unsigned phy_reset:1;
54};
55
56struct ohci_hcd_omap_platform_data {
57 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
58 unsigned es2_compatibility:1;
59};
60
61struct usbhs_omap_platform_data {
62 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
63
64 struct ehci_hcd_omap_platform_data *ehci_data;
65 struct ohci_hcd_omap_platform_data *ohci_data;
66};
67
68struct usbtll_omap_platform_data {
69 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
70};
71/*-------------------------------------------------------------------------*/
72
73struct omap_musb_board_data {
74 u8 interface_type;
75 u8 mode;
76 u16 power;
77 unsigned extvbus:1;
78 void (*set_phy_power)(u8 on);
79 void (*clear_irq)(void);
80 void (*set_mode)(u8 mode);
81 void (*reset)(void);
82};
83
84enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
85
86extern void usb_musb_init(struct omap_musb_board_data *board_data);
87
88extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
89extern int omap_tll_enable(void);
90extern int omap_tll_disable(void);
91
92extern int omap4430_phy_power(struct device *dev, int ID, int on);
93extern int omap4430_phy_set_clk(struct device *dev, int on);
94extern int omap4430_phy_init(struct device *dev);
95extern int omap4430_phy_exit(struct device *dev);
96extern int omap4430_phy_suspend(struct device *dev, int suspend);
97
98#endif
99
100extern void am35x_musb_reset(void);
101extern void am35x_musb_phy_power(u8 on);
102extern void am35x_musb_clear_irq(void);
103extern void am35x_set_mode(u8 musb_mode);
104extern void ti81xx_musb_phy_power(u8 on);
105
106/* AM35x */
107/* USB 2.0 PHY Control */
108#define CONF2_PHY_GPIOMODE (1 << 23)
109#define CONF2_OTGMODE (3 << 14)
110#define CONF2_NO_OVERRIDE (0 << 14)
111#define CONF2_FORCE_HOST (1 << 14)
112#define CONF2_FORCE_DEVICE (2 << 14)
113#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
114#define CONF2_SESENDEN (1 << 13)
115#define CONF2_VBDTCTEN (1 << 12)
116#define CONF2_REFFREQ_24MHZ (2 << 8)
117#define CONF2_REFFREQ_26MHZ (7 << 8)
118#define CONF2_REFFREQ_13MHZ (6 << 8)
119#define CONF2_REFFREQ (0xf << 8)
120#define CONF2_PHYCLKGD (1 << 7)
121#define CONF2_VBUSSENSE (1 << 6)
122#define CONF2_PHY_PLLON (1 << 5)
123#define CONF2_RESET (1 << 4)
124#define CONF2_PHYPWRDN (1 << 3)
125#define CONF2_OTGPWRDN (1 << 2)
126#define CONF2_DATPOL (1 << 1)
127
128/* TI81XX specific definitions */
129#define USBCTRL0 0x620
130#define USBSTAT0 0x624
131
132/* TI816X PHY controls bits */
133#define TI816X_USBPHY0_NORMAL_MODE (1 << 0)
134#define TI816X_USBPHY_REFCLK_OSC (1 << 8)
135
136/* TI814X PHY controls bits */
137#define USBPHY_CM_PWRDN (1 << 0)
138#define USBPHY_OTG_PWRDN (1 << 1)
139#define USBPHY_CHGDET_DIS (1 << 2)
140#define USBPHY_CHGDET_RSTRT (1 << 3)
141#define USBPHY_SRCONDM (1 << 4)
142#define USBPHY_SINKONDP (1 << 5)
143#define USBPHY_CHGISINK_EN (1 << 6)
144#define USBPHY_CHGVSRC_EN (1 << 7)
145#define USBPHY_DMPULLUP (1 << 8)
146#define USBPHY_DPPULLUP (1 << 9)
147#define USBPHY_CDET_EXTCTL (1 << 10)
148#define USBPHY_GPIO_MODE (1 << 12)
149#define USBPHY_DPOPBUFCTL (1 << 13)
150#define USBPHY_DMOPBUFCTL (1 << 14)
151#define USBPHY_DPINPUT (1 << 15)
152#define USBPHY_DMINPUT (1 << 16)
153#define USBPHY_DPGPIO_PD (1 << 17)
154#define USBPHY_DMGPIO_PD (1 << 18)
155#define USBPHY_OTGVDET_EN (1 << 19)
156#define USBPHY_OTGSESSEND_EN (1 << 20)
157#define USBPHY_DATA_POLARITY (1 << 23)
158
159#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
160u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
161u32 omap1_usb1_init(unsigned nwires);
162u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup);
163#else
164static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device)
165{
166 return 0;
167}
168static inline u32 omap1_usb1_init(unsigned nwires)
169{
170 return 0;
171
172}
173static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
174{
175 return 0;
176}
177#endif
178
179#endif /* __ASM_ARCH_OMAP_USB_H */
diff --git a/arch/arm/plat-omap/include/plat/vrfb.h b/arch/arm/plat-omap/include/plat/vrfb.h
deleted file mode 100644
index 3792bdea2f6d..000000000000
--- a/arch/arm/plat-omap/include/plat/vrfb.h
+++ /dev/null
@@ -1,66 +0,0 @@
1/*
2 * VRFB Rotation Engine
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21#ifndef __OMAP_VRFB_H__
22#define __OMAP_VRFB_H__
23
24#define OMAP_VRFB_LINE_LEN 2048
25
26struct vrfb {
27 u8 context;
28 void __iomem *vaddr[4];
29 unsigned long paddr[4];
30 u16 xres;
31 u16 yres;
32 u16 xoffset;
33 u16 yoffset;
34 u8 bytespp;
35 bool yuv_mode;
36};
37
38#ifdef CONFIG_OMAP2_VRFB
39extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
40extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
41extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
42 u8 bytespp);
43extern u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp);
44extern u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp);
45extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
46 u16 width, u16 height,
47 unsigned bytespp, bool yuv_mode);
48extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot);
49extern void omap_vrfb_restore_context(void);
50
51#else
52static inline int omap_vrfb_request_ctx(struct vrfb *vrfb) { return 0; }
53static inline void omap_vrfb_release_ctx(struct vrfb *vrfb) {}
54static inline void omap_vrfb_adjust_size(u16 *width, u16 *height,
55 u8 bytespp) {}
56static inline u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp)
57 { return 0; }
58static inline u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp)
59 { return 0; }
60static inline void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
61 u16 width, u16 height, unsigned bytespp, bool yuv_mode) {}
62static inline int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot)
63 { return 0; }
64static inline void omap_vrfb_restore_context(void) {}
65#endif
66#endif /* __VRFB_H */
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c
deleted file mode 100644
index 9722f418ae1f..000000000000
--- a/arch/arm/plat-omap/omap-pm-noop.c
+++ /dev/null
@@ -1,372 +0,0 @@
1/*
2 * omap-pm-noop.c - OMAP power management interface - dummy version
3 *
4 * This code implements the OMAP power management interface to
5 * drivers, CPUIdle, CPUFreq, and DSP Bridge. It is strictly for
6 * debug/demonstration use, as it does nothing but printk() whenever a
7 * function is called (when DEBUG is defined, below)
8 *
9 * Copyright (C) 2008-2009 Texas Instruments, Inc.
10 * Copyright (C) 2008-2009 Nokia Corporation
11 * Paul Walmsley
12 *
13 * Interface developed by (in alphabetical order):
14 * Karthik Dasu, Tony Lindgren, Rajendra Nayak, Sakari Poussa, Veeramanikandan
15 * Raju, Anand Sawant, Igor Stoppa, Paul Walmsley, Richard Woodruff
16 */
17
18#undef DEBUG
19
20#include <linux/init.h>
21#include <linux/cpufreq.h>
22#include <linux/device.h>
23#include <linux/platform_device.h>
24
25/* Interface documentation is in mach/omap-pm.h */
26#include <plat/omap-pm.h>
27#include <plat/omap_device.h>
28
29static bool off_mode_enabled;
30static int dummy_context_loss_counter;
31
32/*
33 * Device-driver-originated constraints (via board-*.c files)
34 */
35
36int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t)
37{
38 if (!dev || t < -1) {
39 WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
40 return -EINVAL;
41 }
42
43 if (t == -1)
44 pr_debug("OMAP PM: remove max MPU wakeup latency constraint: dev %s\n",
45 dev_name(dev));
46 else
47 pr_debug("OMAP PM: add max MPU wakeup latency constraint: dev %s, t = %ld usec\n",
48 dev_name(dev), t);
49
50 /*
51 * For current Linux, this needs to map the MPU to a
52 * powerdomain, then go through the list of current max lat
53 * constraints on the MPU and find the smallest. If
54 * the latency constraint has changed, the code should
55 * recompute the state to enter for the next powerdomain
56 * state.
57 *
58 * TI CDP code can call constraint_set here.
59 */
60
61 return 0;
62}
63
64int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r)
65{
66 if (!dev || (agent_id != OCP_INITIATOR_AGENT &&
67 agent_id != OCP_TARGET_AGENT)) {
68 WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
69 return -EINVAL;
70 }
71
72 if (r == 0)
73 pr_debug("OMAP PM: remove min bus tput constraint: dev %s for agent_id %d\n",
74 dev_name(dev), agent_id);
75 else
76 pr_debug("OMAP PM: add min bus tput constraint: dev %s for agent_id %d: rate %ld KiB\n",
77 dev_name(dev), agent_id, r);
78
79 /*
80 * This code should model the interconnect and compute the
81 * required clock frequency, convert that to a VDD2 OPP ID, then
82 * set the VDD2 OPP appropriately.
83 *
84 * TI CDP code can call constraint_set here on the VDD2 OPP.
85 */
86
87 return 0;
88}
89
90int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
91 long t)
92{
93 if (!req_dev || !dev || t < -1) {
94 WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
95 return -EINVAL;
96 }
97
98 if (t == -1)
99 pr_debug("OMAP PM: remove max device latency constraint: dev %s\n",
100 dev_name(dev));
101 else
102 pr_debug("OMAP PM: add max device latency constraint: dev %s, t = %ld usec\n",
103 dev_name(dev), t);
104
105 /*
106 * For current Linux, this needs to map the device to a
107 * powerdomain, then go through the list of current max lat
108 * constraints on that powerdomain and find the smallest. If
109 * the latency constraint has changed, the code should
110 * recompute the state to enter for the next powerdomain
111 * state. Conceivably, this code should also determine
112 * whether to actually disable the device clocks or not,
113 * depending on how long it takes to re-enable the clocks.
114 *
115 * TI CDP code can call constraint_set here.
116 */
117
118 return 0;
119}
120
121int omap_pm_set_max_sdma_lat(struct device *dev, long t)
122{
123 if (!dev || t < -1) {
124 WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
125 return -EINVAL;
126 }
127
128 if (t == -1)
129 pr_debug("OMAP PM: remove max DMA latency constraint: dev %s\n",
130 dev_name(dev));
131 else
132 pr_debug("OMAP PM: add max DMA latency constraint: dev %s, t = %ld usec\n",
133 dev_name(dev), t);
134
135 /*
136 * For current Linux PM QOS params, this code should scan the
137 * list of maximum CPU and DMA latencies and select the
138 * smallest, then set cpu_dma_latency pm_qos_param
139 * accordingly.
140 *
141 * For future Linux PM QOS params, with separate CPU and DMA
142 * latency params, this code should just set the dma_latency param.
143 *
144 * TI CDP code can call constraint_set here.
145 */
146
147 return 0;
148}
149
150int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r)
151{
152 if (!dev || !c || r < 0) {
153 WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
154 return -EINVAL;
155 }
156
157 if (r == 0)
158 pr_debug("OMAP PM: remove min clk rate constraint: dev %s\n",
159 dev_name(dev));
160 else
161 pr_debug("OMAP PM: add min clk rate constraint: dev %s, rate = %ld Hz\n",
162 dev_name(dev), r);
163
164 /*
165 * Code in a real implementation should keep track of these
166 * constraints on the clock, and determine the highest minimum
167 * clock rate. It should iterate over each OPP and determine
168 * whether the OPP will result in a clock rate that would
169 * satisfy this constraint (and any other PM constraint in effect
170 * at that time). Once it finds the lowest-voltage OPP that
171 * meets those conditions, it should switch to it, or return
172 * an error if the code is not capable of doing so.
173 */
174
175 return 0;
176}
177
178/*
179 * DSP Bridge-specific constraints
180 */
181
182const struct omap_opp *omap_pm_dsp_get_opp_table(void)
183{
184 pr_debug("OMAP PM: DSP request for OPP table\n");
185
186 /*
187 * Return DSP frequency table here: The final item in the
188 * array should have .rate = .opp_id = 0.
189 */
190
191 return NULL;
192}
193
194void omap_pm_dsp_set_min_opp(u8 opp_id)
195{
196 if (opp_id == 0) {
197 WARN_ON(1);
198 return;
199 }
200
201 pr_debug("OMAP PM: DSP requests minimum VDD1 OPP to be %d\n", opp_id);
202
203 /*
204 *
205 * For l-o dev tree, our VDD1 clk is keyed on OPP ID, so we
206 * can just test to see which is higher, the CPU's desired OPP
207 * ID or the DSP's desired OPP ID, and use whichever is
208 * highest.
209 *
210 * In CDP12.14+, the VDD1 OPP custom clock that controls the DSP
211 * rate is keyed on MPU speed, not the OPP ID. So we need to
212 * map the OPP ID to the MPU speed for use with clk_set_rate()
213 * if it is higher than the current OPP clock rate.
214 *
215 */
216}
217
218
219u8 omap_pm_dsp_get_opp(void)
220{
221 pr_debug("OMAP PM: DSP requests current DSP OPP ID\n");
222
223 /*
224 * For l-o dev tree, call clk_get_rate() on VDD1 OPP clock
225 *
226 * CDP12.14+:
227 * Call clk_get_rate() on the OPP custom clock, map that to an
228 * OPP ID using the tables defined in board-*.c/chip-*.c files.
229 */
230
231 return 0;
232}
233
234/*
235 * CPUFreq-originated constraint
236 *
237 * In the future, this should be handled by custom OPP clocktype
238 * functions.
239 */
240
241struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void)
242{
243 pr_debug("OMAP PM: CPUFreq request for frequency table\n");
244
245 /*
246 * Return CPUFreq frequency table here: loop over
247 * all VDD1 clkrates, pull out the mpu_ck frequencies, build
248 * table
249 */
250
251 return NULL;
252}
253
254void omap_pm_cpu_set_freq(unsigned long f)
255{
256 if (f == 0) {
257 WARN_ON(1);
258 return;
259 }
260
261 pr_debug("OMAP PM: CPUFreq requests CPU frequency to be set to %lu\n",
262 f);
263
264 /*
265 * For l-o dev tree, determine whether MPU freq or DSP OPP id
266 * freq is higher. Find the OPP ID corresponding to the
267 * higher frequency. Call clk_round_rate() and clk_set_rate()
268 * on the OPP custom clock.
269 *
270 * CDP should just be able to set the VDD1 OPP clock rate here.
271 */
272}
273
274unsigned long omap_pm_cpu_get_freq(void)
275{
276 pr_debug("OMAP PM: CPUFreq requests current CPU frequency\n");
277
278 /*
279 * Call clk_get_rate() on the mpu_ck.
280 */
281
282 return 0;
283}
284
285/**
286 * omap_pm_enable_off_mode - notify OMAP PM that off-mode is enabled
287 *
288 * Intended for use only by OMAP PM core code to notify this layer
289 * that off mode has been enabled.
290 */
291void omap_pm_enable_off_mode(void)
292{
293 off_mode_enabled = true;
294}
295
296/**
297 * omap_pm_disable_off_mode - notify OMAP PM that off-mode is disabled
298 *
299 * Intended for use only by OMAP PM core code to notify this layer
300 * that off mode has been disabled.
301 */
302void omap_pm_disable_off_mode(void)
303{
304 off_mode_enabled = false;
305}
306
307/*
308 * Device context loss tracking
309 */
310
311#ifdef CONFIG_ARCH_OMAP2PLUS
312
313int omap_pm_get_dev_context_loss_count(struct device *dev)
314{
315 struct platform_device *pdev = to_platform_device(dev);
316 int count;
317
318 if (WARN_ON(!dev))
319 return -ENODEV;
320
321 if (dev->pm_domain == &omap_device_pm_domain) {
322 count = omap_device_get_context_loss_count(pdev);
323 } else {
324 WARN_ONCE(off_mode_enabled, "omap_pm: using dummy context loss counter; device %s should be converted to omap_device",
325 dev_name(dev));
326
327 count = dummy_context_loss_counter;
328
329 if (off_mode_enabled) {
330 count++;
331 /*
332 * Context loss count has to be a non-negative value.
333 * Clear the sign bit to get a value range from 0 to
334 * INT_MAX.
335 */
336 count &= INT_MAX;
337 dummy_context_loss_counter = count;
338 }
339 }
340
341 pr_debug("OMAP PM: context loss count for dev %s = %d\n",
342 dev_name(dev), count);
343
344 return count;
345}
346
347#else
348
349int omap_pm_get_dev_context_loss_count(struct device *dev)
350{
351 return dummy_context_loss_counter;
352}
353
354#endif
355
356/* Should be called before clk framework init */
357int __init omap_pm_if_early_init(void)
358{
359 return 0;
360}
361
362/* Must be called after clock framework is initialized */
363int __init omap_pm_if_init(void)
364{
365 return 0;
366}
367
368void omap_pm_if_exit(void)
369{
370 /* Deallocate CPUFreq frequency table here */
371}
372
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
deleted file mode 100644
index 7a7d1f2a65e9..000000000000
--- a/arch/arm/plat-omap/omap_device.c
+++ /dev/null
@@ -1,1278 +0,0 @@
1/*
2 * omap_device implementation
3 *
4 * Copyright (C) 2009-2010 Nokia Corporation
5 * Paul Walmsley, Kevin Hilman
6 *
7 * Developed in collaboration with (alphabetical order): Benoit
8 * Cousson, Thara Gopinath, Tony Lindgren, Rajendra Nayak, Vikram
9 * Pandita, Sakari Poussa, Anand Sawant, Santosh Shilimkar, Richard
10 * Woodruff
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * This code provides a consistent interface for OMAP device drivers
17 * to control power management and interconnect properties of their
18 * devices.
19 *
20 * In the medium- to long-term, this code should either be
21 * a) implemented via arch-specific pointers in platform_data
22 * or
23 * b) implemented as a proper omap_bus/omap_device in Linux, no more
24 * platform_data func pointers
25 *
26 *
27 * Guidelines for usage by driver authors:
28 *
29 * 1. These functions are intended to be used by device drivers via
30 * function pointers in struct platform_data. As an example,
31 * omap_device_enable() should be passed to the driver as
32 *
33 * struct foo_driver_platform_data {
34 * ...
35 * int (*device_enable)(struct platform_device *pdev);
36 * ...
37 * }
38 *
39 * Note that the generic "device_enable" name is used, rather than
40 * "omap_device_enable". This is so other architectures can pass in their
41 * own enable/disable functions here.
42 *
43 * This should be populated during device setup:
44 *
45 * ...
46 * pdata->device_enable = omap_device_enable;
47 * ...
48 *
49 * 2. Drivers should first check to ensure the function pointer is not null
50 * before calling it, as in:
51 *
52 * if (pdata->device_enable)
53 * pdata->device_enable(pdev);
54 *
55 * This allows other architectures that don't use similar device_enable()/
56 * device_shutdown() functions to execute normally.
57 *
58 * ...
59 *
60 * Suggested usage by device drivers:
61 *
62 * During device initialization:
63 * device_enable()
64 *
65 * During device idle:
66 * (save remaining device context if necessary)
67 * device_idle();
68 *
69 * During device resume:
70 * device_enable();
71 * (restore context if necessary)
72 *
73 * During device shutdown:
74 * device_shutdown()
75 * (device must be reinitialized at this point to use it again)
76 *
77 */
78#undef DEBUG
79
80#include <linux/kernel.h>
81#include <linux/export.h>
82#include <linux/platform_device.h>
83#include <linux/slab.h>
84#include <linux/err.h>
85#include <linux/io.h>
86#include <linux/clk.h>
87#include <linux/clkdev.h>
88#include <linux/pm_runtime.h>
89#include <linux/of.h>
90#include <linux/notifier.h>
91
92#include <plat/omap_device.h>
93#include <plat/omap_hwmod.h>
94#include <plat/clock.h>
95
96/* These parameters are passed to _omap_device_{de,}activate() */
97#define USE_WAKEUP_LAT 0
98#define IGNORE_WAKEUP_LAT 1
99
100static int omap_early_device_register(struct platform_device *pdev);
101
102static struct omap_device_pm_latency omap_default_latency[] = {
103 {
104 .deactivate_func = omap_device_idle_hwmods,
105 .activate_func = omap_device_enable_hwmods,
106 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
107 }
108};
109
110/* Private functions */
111
112/**
113 * _omap_device_activate - increase device readiness
114 * @od: struct omap_device *
115 * @ignore_lat: increase to latency target (0) or full readiness (1)?
116 *
117 * Increase readiness of omap_device @od (thus decreasing device
118 * wakeup latency, but consuming more power). If @ignore_lat is
119 * IGNORE_WAKEUP_LAT, make the omap_device fully active. Otherwise,
120 * if @ignore_lat is USE_WAKEUP_LAT, and the device's maximum wakeup
121 * latency is greater than the requested maximum wakeup latency, step
122 * backwards in the omap_device_pm_latency table to ensure the
123 * device's maximum wakeup latency is less than or equal to the
124 * requested maximum wakeup latency. Returns 0.
125 */
126static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
127{
128 struct timespec a, b, c;
129
130 dev_dbg(&od->pdev->dev, "omap_device: activating\n");
131
132 while (od->pm_lat_level > 0) {
133 struct omap_device_pm_latency *odpl;
134 unsigned long long act_lat = 0;
135
136 od->pm_lat_level--;
137
138 odpl = od->pm_lats + od->pm_lat_level;
139
140 if (!ignore_lat &&
141 (od->dev_wakeup_lat <= od->_dev_wakeup_lat_limit))
142 break;
143
144 read_persistent_clock(&a);
145
146 /* XXX check return code */
147 odpl->activate_func(od);
148
149 read_persistent_clock(&b);
150
151 c = timespec_sub(b, a);
152 act_lat = timespec_to_ns(&c);
153
154 dev_dbg(&od->pdev->dev,
155 "omap_device: pm_lat %d: activate: elapsed time %llu nsec\n",
156 od->pm_lat_level, act_lat);
157
158 if (act_lat > odpl->activate_lat) {
159 odpl->activate_lat_worst = act_lat;
160 if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
161 odpl->activate_lat = act_lat;
162 dev_dbg(&od->pdev->dev,
163 "new worst case activate latency %d: %llu\n",
164 od->pm_lat_level, act_lat);
165 } else
166 dev_warn(&od->pdev->dev,
167 "activate latency %d higher than expected. (%llu > %d)\n",
168 od->pm_lat_level, act_lat,
169 odpl->activate_lat);
170 }
171
172 od->dev_wakeup_lat -= odpl->activate_lat;
173 }
174
175 return 0;
176}
177
178/**
179 * _omap_device_deactivate - decrease device readiness
180 * @od: struct omap_device *
181 * @ignore_lat: decrease to latency target (0) or full inactivity (1)?
182 *
183 * Decrease readiness of omap_device @od (thus increasing device
184 * wakeup latency, but conserving power). If @ignore_lat is
185 * IGNORE_WAKEUP_LAT, make the omap_device fully inactive. Otherwise,
186 * if @ignore_lat is USE_WAKEUP_LAT, and the device's maximum wakeup
187 * latency is less than the requested maximum wakeup latency, step
188 * forwards in the omap_device_pm_latency table to ensure the device's
189 * maximum wakeup latency is less than or equal to the requested
190 * maximum wakeup latency. Returns 0.
191 */
192static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
193{
194 struct timespec a, b, c;
195
196 dev_dbg(&od->pdev->dev, "omap_device: deactivating\n");
197
198 while (od->pm_lat_level < od->pm_lats_cnt) {
199 struct omap_device_pm_latency *odpl;
200 unsigned long long deact_lat = 0;
201
202 odpl = od->pm_lats + od->pm_lat_level;
203
204 if (!ignore_lat &&
205 ((od->dev_wakeup_lat + odpl->activate_lat) >
206 od->_dev_wakeup_lat_limit))
207 break;
208
209 read_persistent_clock(&a);
210
211 /* XXX check return code */
212 odpl->deactivate_func(od);
213
214 read_persistent_clock(&b);
215
216 c = timespec_sub(b, a);
217 deact_lat = timespec_to_ns(&c);
218
219 dev_dbg(&od->pdev->dev,
220 "omap_device: pm_lat %d: deactivate: elapsed time %llu nsec\n",
221 od->pm_lat_level, deact_lat);
222
223 if (deact_lat > odpl->deactivate_lat) {
224 odpl->deactivate_lat_worst = deact_lat;
225 if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
226 odpl->deactivate_lat = deact_lat;
227 dev_dbg(&od->pdev->dev,
228 "new worst case deactivate latency %d: %llu\n",
229 od->pm_lat_level, deact_lat);
230 } else
231 dev_warn(&od->pdev->dev,
232 "deactivate latency %d higher than expected. (%llu > %d)\n",
233 od->pm_lat_level, deact_lat,
234 odpl->deactivate_lat);
235 }
236
237 od->dev_wakeup_lat += odpl->activate_lat;
238
239 od->pm_lat_level++;
240 }
241
242 return 0;
243}
244
245static void _add_clkdev(struct omap_device *od, const char *clk_alias,
246 const char *clk_name)
247{
248 struct clk *r;
249 struct clk_lookup *l;
250
251 if (!clk_alias || !clk_name)
252 return;
253
254 dev_dbg(&od->pdev->dev, "Creating %s -> %s\n", clk_alias, clk_name);
255
256 r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias);
257 if (!IS_ERR(r)) {
258 dev_warn(&od->pdev->dev,
259 "alias %s already exists\n", clk_alias);
260 clk_put(r);
261 return;
262 }
263
264 r = clk_get(NULL, clk_name);
265 if (IS_ERR(r)) {
266 dev_err(&od->pdev->dev,
267 "clk_get for %s failed\n", clk_name);
268 return;
269 }
270
271 l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev->dev));
272 if (!l) {
273 dev_err(&od->pdev->dev,
274 "clkdev_alloc for %s failed\n", clk_alias);
275 return;
276 }
277
278 clkdev_add(l);
279}
280
281/**
282 * _add_hwmod_clocks_clkdev - Add clkdev entry for hwmod optional clocks
283 * and main clock
284 * @od: struct omap_device *od
285 * @oh: struct omap_hwmod *oh
286 *
287 * For the main clock and every optional clock present per hwmod per
288 * omap_device, this function adds an entry in the clkdev table of the
289 * form <dev-id=dev_name, con-id=role> if it does not exist already.
290 *
291 * The function is called from inside omap_device_build_ss(), after
292 * omap_device_register.
293 *
294 * This allows drivers to get a pointer to its optional clocks based on its role
295 * by calling clk_get(<dev*>, <role>).
296 * In the case of the main clock, a "fck" alias is used.
297 *
298 * No return value.
299 */
300static void _add_hwmod_clocks_clkdev(struct omap_device *od,
301 struct omap_hwmod *oh)
302{
303 int i;
304
305 _add_clkdev(od, "fck", oh->main_clk);
306
307 for (i = 0; i < oh->opt_clks_cnt; i++)
308 _add_clkdev(od, oh->opt_clks[i].role, oh->opt_clks[i].clk);
309}
310
311
312/**
313 * omap_device_build_from_dt - build an omap_device with multiple hwmods
314 * @pdev_name: name of the platform_device driver to use
315 * @pdev_id: this platform_device's connection ID
316 * @oh: ptr to the single omap_hwmod that backs this omap_device
317 * @pdata: platform_data ptr to associate with the platform_device
318 * @pdata_len: amount of memory pointed to by @pdata
319 * @pm_lats: pointer to a omap_device_pm_latency array for this device
320 * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
321 * @is_early_device: should the device be registered as an early device or not
322 *
323 * Function for building an omap_device already registered from device-tree
324 *
325 * Returns 0 or PTR_ERR() on error.
326 */
327static int omap_device_build_from_dt(struct platform_device *pdev)
328{
329 struct omap_hwmod **hwmods;
330 struct omap_device *od;
331 struct omap_hwmod *oh;
332 struct device_node *node = pdev->dev.of_node;
333 const char *oh_name;
334 int oh_cnt, i, ret = 0;
335
336 oh_cnt = of_property_count_strings(node, "ti,hwmods");
337 if (!oh_cnt || IS_ERR_VALUE(oh_cnt)) {
338 dev_dbg(&pdev->dev, "No 'hwmods' to build omap_device\n");
339 return -ENODEV;
340 }
341
342 hwmods = kzalloc(sizeof(struct omap_hwmod *) * oh_cnt, GFP_KERNEL);
343 if (!hwmods) {
344 ret = -ENOMEM;
345 goto odbfd_exit;
346 }
347
348 for (i = 0; i < oh_cnt; i++) {
349 of_property_read_string_index(node, "ti,hwmods", i, &oh_name);
350 oh = omap_hwmod_lookup(oh_name);
351 if (!oh) {
352 dev_err(&pdev->dev, "Cannot lookup hwmod '%s'\n",
353 oh_name);
354 ret = -EINVAL;
355 goto odbfd_exit1;
356 }
357 hwmods[i] = oh;
358 }
359
360 od = omap_device_alloc(pdev, hwmods, oh_cnt, NULL, 0);
361 if (!od) {
362 dev_err(&pdev->dev, "Cannot allocate omap_device for :%s\n",
363 oh_name);
364 ret = PTR_ERR(od);
365 goto odbfd_exit1;
366 }
367
368 /* Fix up missing resource names */
369 for (i = 0; i < pdev->num_resources; i++) {
370 struct resource *r = &pdev->resource[i];
371
372 if (r->name == NULL)
373 r->name = dev_name(&pdev->dev);
374 }
375
376 if (of_get_property(node, "ti,no_idle_on_suspend", NULL))
377 omap_device_disable_idle_on_suspend(pdev);
378
379 pdev->dev.pm_domain = &omap_device_pm_domain;
380
381odbfd_exit1:
382 kfree(hwmods);
383odbfd_exit:
384 return ret;
385}
386
387static int _omap_device_notifier_call(struct notifier_block *nb,
388 unsigned long event, void *dev)
389{
390 struct platform_device *pdev = to_platform_device(dev);
391 struct omap_device *od;
392
393 switch (event) {
394 case BUS_NOTIFY_DEL_DEVICE:
395 if (pdev->archdata.od)
396 omap_device_delete(pdev->archdata.od);
397 break;
398 case BUS_NOTIFY_ADD_DEVICE:
399 if (pdev->dev.of_node)
400 omap_device_build_from_dt(pdev);
401 /* fall through */
402 default:
403 od = to_omap_device(pdev);
404 if (od)
405 od->_driver_status = event;
406 }
407
408 return NOTIFY_DONE;
409}
410
411
412/* Public functions for use by core code */
413
414/**
415 * omap_device_get_context_loss_count - get lost context count
416 * @od: struct omap_device *
417 *
418 * Using the primary hwmod, query the context loss count for this
419 * device.
420 *
421 * Callers should consider context for this device lost any time this
422 * function returns a value different than the value the caller got
423 * the last time it called this function.
424 *
425 * If any hwmods exist for the omap_device assoiated with @pdev,
426 * return the context loss counter for that hwmod, otherwise return
427 * zero.
428 */
429int omap_device_get_context_loss_count(struct platform_device *pdev)
430{
431 struct omap_device *od;
432 u32 ret = 0;
433
434 od = to_omap_device(pdev);
435
436 if (od->hwmods_cnt)
437 ret = omap_hwmod_get_context_loss_count(od->hwmods[0]);
438
439 return ret;
440}
441
442/**
443 * omap_device_count_resources - count number of struct resource entries needed
444 * @od: struct omap_device *
445 *
446 * Count the number of struct resource entries needed for this
447 * omap_device @od. Used by omap_device_build_ss() to determine how
448 * much memory to allocate before calling
449 * omap_device_fill_resources(). Returns the count.
450 */
451static int omap_device_count_resources(struct omap_device *od)
452{
453 int c = 0;
454 int i;
455
456 for (i = 0; i < od->hwmods_cnt; i++)
457 c += omap_hwmod_count_resources(od->hwmods[i]);
458
459 pr_debug("omap_device: %s: counted %d total resources across %d hwmods\n",
460 od->pdev->name, c, od->hwmods_cnt);
461
462 return c;
463}
464
465/**
466 * omap_device_fill_resources - fill in array of struct resource
467 * @od: struct omap_device *
468 * @res: pointer to an array of struct resource to be filled in
469 *
470 * Populate one or more empty struct resource pointed to by @res with
471 * the resource data for this omap_device @od. Used by
472 * omap_device_build_ss() after calling omap_device_count_resources().
473 * Ideally this function would not be needed at all. If omap_device
474 * replaces platform_device, then we can specify our own
475 * get_resource()/ get_irq()/etc functions that use the underlying
476 * omap_hwmod information. Or if platform_device is extended to use
477 * subarchitecture-specific function pointers, the various
478 * platform_device functions can simply call omap_device internal
479 * functions to get device resources. Hacking around the existing
480 * platform_device code wastes memory. Returns 0.
481 */
482static int omap_device_fill_resources(struct omap_device *od,
483 struct resource *res)
484{
485 int i, r;
486
487 for (i = 0; i < od->hwmods_cnt; i++) {
488 r = omap_hwmod_fill_resources(od->hwmods[i], res);
489 res += r;
490 }
491
492 return 0;
493}
494
495/**
496 * _od_fill_dma_resources - fill in array of struct resource with dma resources
497 * @od: struct omap_device *
498 * @res: pointer to an array of struct resource to be filled in
499 *
500 * Populate one or more empty struct resource pointed to by @res with
501 * the dma resource data for this omap_device @od. Used by
502 * omap_device_alloc() after calling omap_device_count_resources().
503 *
504 * Ideally this function would not be needed at all. If we have
505 * mechanism to get dma resources from DT.
506 *
507 * Returns 0.
508 */
509static int _od_fill_dma_resources(struct omap_device *od,
510 struct resource *res)
511{
512 int i, r;
513
514 for (i = 0; i < od->hwmods_cnt; i++) {
515 r = omap_hwmod_fill_dma_resources(od->hwmods[i], res);
516 res += r;
517 }
518
519 return 0;
520}
521
522/**
523 * omap_device_alloc - allocate an omap_device
524 * @pdev: platform_device that will be included in this omap_device
525 * @oh: ptr to the single omap_hwmod that backs this omap_device
526 * @pdata: platform_data ptr to associate with the platform_device
527 * @pdata_len: amount of memory pointed to by @pdata
528 * @pm_lats: pointer to a omap_device_pm_latency array for this device
529 * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
530 *
531 * Convenience function for allocating an omap_device structure and filling
532 * hwmods, resources and pm_latency attributes.
533 *
534 * Returns an struct omap_device pointer or ERR_PTR() on error;
535 */
536struct omap_device *omap_device_alloc(struct platform_device *pdev,
537 struct omap_hwmod **ohs, int oh_cnt,
538 struct omap_device_pm_latency *pm_lats,
539 int pm_lats_cnt)
540{
541 int ret = -ENOMEM;
542 struct omap_device *od;
543 struct resource *res = NULL;
544 int i, res_count;
545 struct omap_hwmod **hwmods;
546
547 od = kzalloc(sizeof(struct omap_device), GFP_KERNEL);
548 if (!od) {
549 ret = -ENOMEM;
550 goto oda_exit1;
551 }
552 od->hwmods_cnt = oh_cnt;
553
554 hwmods = kmemdup(ohs, sizeof(struct omap_hwmod *) * oh_cnt, GFP_KERNEL);
555 if (!hwmods)
556 goto oda_exit2;
557
558 od->hwmods = hwmods;
559 od->pdev = pdev;
560
561 res_count = omap_device_count_resources(od);
562 /*
563 * DT Boot:
564 * OF framework will construct the resource structure (currently
565 * does for MEM & IRQ resource) and we should respect/use these
566 * resources, killing hwmod dependency.
567 * If pdev->num_resources > 0, we assume that MEM & IRQ resources
568 * have been allocated by OF layer already (through DTB).
569 *
570 * Non-DT Boot:
571 * Here, pdev->num_resources = 0, and we should get all the
572 * resources from hwmod.
573 *
574 * TODO: Once DMA resource is available from OF layer, we should
575 * kill filling any resources from hwmod.
576 */
577 if (res_count > pdev->num_resources) {
578 /* Allocate resources memory to account for new resources */
579 res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
580 if (!res)
581 goto oda_exit3;
582
583 /*
584 * If pdev->num_resources > 0, then assume that,
585 * MEM and IRQ resources will only come from DT and only
586 * fill DMA resource from hwmod layer.
587 */
588 if (pdev->num_resources && pdev->resource) {
589 dev_dbg(&pdev->dev, "%s(): resources already allocated %d\n",
590 __func__, res_count);
591 memcpy(res, pdev->resource,
592 sizeof(struct resource) * pdev->num_resources);
593 _od_fill_dma_resources(od, &res[pdev->num_resources]);
594 } else {
595 dev_dbg(&pdev->dev, "%s(): using resources from hwmod %d\n",
596 __func__, res_count);
597 omap_device_fill_resources(od, res);
598 }
599
600 ret = platform_device_add_resources(pdev, res, res_count);
601 kfree(res);
602
603 if (ret)
604 goto oda_exit3;
605 }
606
607 if (!pm_lats) {
608 pm_lats = omap_default_latency;
609 pm_lats_cnt = ARRAY_SIZE(omap_default_latency);
610 }
611
612 od->pm_lats_cnt = pm_lats_cnt;
613 od->pm_lats = kmemdup(pm_lats,
614 sizeof(struct omap_device_pm_latency) * pm_lats_cnt,
615 GFP_KERNEL);
616 if (!od->pm_lats)
617 goto oda_exit3;
618
619 pdev->archdata.od = od;
620
621 for (i = 0; i < oh_cnt; i++) {
622 hwmods[i]->od = od;
623 _add_hwmod_clocks_clkdev(od, hwmods[i]);
624 }
625
626 return od;
627
628oda_exit3:
629 kfree(hwmods);
630oda_exit2:
631 kfree(od);
632oda_exit1:
633 dev_err(&pdev->dev, "omap_device: build failed (%d)\n", ret);
634
635 return ERR_PTR(ret);
636}
637
638void omap_device_delete(struct omap_device *od)
639{
640 if (!od)
641 return;
642
643 od->pdev->archdata.od = NULL;
644 kfree(od->pm_lats);
645 kfree(od->hwmods);
646 kfree(od);
647}
648
649/**
650 * omap_device_build - build and register an omap_device with one omap_hwmod
651 * @pdev_name: name of the platform_device driver to use
652 * @pdev_id: this platform_device's connection ID
653 * @oh: ptr to the single omap_hwmod that backs this omap_device
654 * @pdata: platform_data ptr to associate with the platform_device
655 * @pdata_len: amount of memory pointed to by @pdata
656 * @pm_lats: pointer to a omap_device_pm_latency array for this device
657 * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
658 * @is_early_device: should the device be registered as an early device or not
659 *
660 * Convenience function for building and registering a single
661 * omap_device record, which in turn builds and registers a
662 * platform_device record. See omap_device_build_ss() for more
663 * information. Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise,
664 * passes along the return value of omap_device_build_ss().
665 */
666struct platform_device __init *omap_device_build(const char *pdev_name, int pdev_id,
667 struct omap_hwmod *oh, void *pdata,
668 int pdata_len,
669 struct omap_device_pm_latency *pm_lats,
670 int pm_lats_cnt, int is_early_device)
671{
672 struct omap_hwmod *ohs[] = { oh };
673
674 if (!oh)
675 return ERR_PTR(-EINVAL);
676
677 return omap_device_build_ss(pdev_name, pdev_id, ohs, 1, pdata,
678 pdata_len, pm_lats, pm_lats_cnt,
679 is_early_device);
680}
681
682/**
683 * omap_device_build_ss - build and register an omap_device with multiple hwmods
684 * @pdev_name: name of the platform_device driver to use
685 * @pdev_id: this platform_device's connection ID
686 * @oh: ptr to the single omap_hwmod that backs this omap_device
687 * @pdata: platform_data ptr to associate with the platform_device
688 * @pdata_len: amount of memory pointed to by @pdata
689 * @pm_lats: pointer to a omap_device_pm_latency array for this device
690 * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
691 * @is_early_device: should the device be registered as an early device or not
692 *
693 * Convenience function for building and registering an omap_device
694 * subsystem record. Subsystem records consist of multiple
695 * omap_hwmods. This function in turn builds and registers a
696 * platform_device record. Returns an ERR_PTR() on error, or passes
697 * along the return value of omap_device_register().
698 */
699struct platform_device __init *omap_device_build_ss(const char *pdev_name, int pdev_id,
700 struct omap_hwmod **ohs, int oh_cnt,
701 void *pdata, int pdata_len,
702 struct omap_device_pm_latency *pm_lats,
703 int pm_lats_cnt, int is_early_device)
704{
705 int ret = -ENOMEM;
706 struct platform_device *pdev;
707 struct omap_device *od;
708
709 if (!ohs || oh_cnt == 0 || !pdev_name)
710 return ERR_PTR(-EINVAL);
711
712 if (!pdata && pdata_len > 0)
713 return ERR_PTR(-EINVAL);
714
715 pdev = platform_device_alloc(pdev_name, pdev_id);
716 if (!pdev) {
717 ret = -ENOMEM;
718 goto odbs_exit;
719 }
720
721 /* Set the dev_name early to allow dev_xxx in omap_device_alloc */
722 if (pdev->id != -1)
723 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
724 else
725 dev_set_name(&pdev->dev, "%s", pdev->name);
726
727 od = omap_device_alloc(pdev, ohs, oh_cnt, pm_lats, pm_lats_cnt);
728 if (IS_ERR(od))
729 goto odbs_exit1;
730
731 ret = platform_device_add_data(pdev, pdata, pdata_len);
732 if (ret)
733 goto odbs_exit2;
734
735 if (is_early_device)
736 ret = omap_early_device_register(pdev);
737 else
738 ret = omap_device_register(pdev);
739 if (ret)
740 goto odbs_exit2;
741
742 return pdev;
743
744odbs_exit2:
745 omap_device_delete(od);
746odbs_exit1:
747 platform_device_put(pdev);
748odbs_exit:
749
750 pr_err("omap_device: %s: build failed (%d)\n", pdev_name, ret);
751
752 return ERR_PTR(ret);
753}
754
755/**
756 * omap_early_device_register - register an omap_device as an early platform
757 * device.
758 * @od: struct omap_device * to register
759 *
760 * Register the omap_device structure. This currently just calls
761 * platform_early_add_device() on the underlying platform_device.
762 * Returns 0 by default.
763 */
764static int __init omap_early_device_register(struct platform_device *pdev)
765{
766 struct platform_device *devices[1];
767
768 devices[0] = pdev;
769 early_platform_add_devices(devices, 1);
770 return 0;
771}
772
773#ifdef CONFIG_PM_RUNTIME
774static int _od_runtime_suspend(struct device *dev)
775{
776 struct platform_device *pdev = to_platform_device(dev);
777 int ret;
778
779 ret = pm_generic_runtime_suspend(dev);
780
781 if (!ret)
782 omap_device_idle(pdev);
783
784 return ret;
785}
786
787static int _od_runtime_idle(struct device *dev)
788{
789 return pm_generic_runtime_idle(dev);
790}
791
792static int _od_runtime_resume(struct device *dev)
793{
794 struct platform_device *pdev = to_platform_device(dev);
795
796 omap_device_enable(pdev);
797
798 return pm_generic_runtime_resume(dev);
799}
800#endif
801
802#ifdef CONFIG_SUSPEND
803static int _od_suspend_noirq(struct device *dev)
804{
805 struct platform_device *pdev = to_platform_device(dev);
806 struct omap_device *od = to_omap_device(pdev);
807 int ret;
808
809 /* Don't attempt late suspend on a driver that is not bound */
810 if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER)
811 return 0;
812
813 ret = pm_generic_suspend_noirq(dev);
814
815 if (!ret && !pm_runtime_status_suspended(dev)) {
816 if (pm_generic_runtime_suspend(dev) == 0) {
817 if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND))
818 omap_device_idle(pdev);
819 od->flags |= OMAP_DEVICE_SUSPENDED;
820 }
821 }
822
823 return ret;
824}
825
826static int _od_resume_noirq(struct device *dev)
827{
828 struct platform_device *pdev = to_platform_device(dev);
829 struct omap_device *od = to_omap_device(pdev);
830
831 if ((od->flags & OMAP_DEVICE_SUSPENDED) &&
832 !pm_runtime_status_suspended(dev)) {
833 od->flags &= ~OMAP_DEVICE_SUSPENDED;
834 if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND))
835 omap_device_enable(pdev);
836 pm_generic_runtime_resume(dev);
837 }
838
839 return pm_generic_resume_noirq(dev);
840}
841#else
842#define _od_suspend_noirq NULL
843#define _od_resume_noirq NULL
844#endif
845
846struct dev_pm_domain omap_device_pm_domain = {
847 .ops = {
848 SET_RUNTIME_PM_OPS(_od_runtime_suspend, _od_runtime_resume,
849 _od_runtime_idle)
850 USE_PLATFORM_PM_SLEEP_OPS
851 .suspend_noirq = _od_suspend_noirq,
852 .resume_noirq = _od_resume_noirq,
853 }
854};
855
856/**
857 * omap_device_register - register an omap_device with one omap_hwmod
858 * @od: struct omap_device * to register
859 *
860 * Register the omap_device structure. This currently just calls
861 * platform_device_register() on the underlying platform_device.
862 * Returns the return value of platform_device_register().
863 */
864int omap_device_register(struct platform_device *pdev)
865{
866 pr_debug("omap_device: %s: registering\n", pdev->name);
867
868 pdev->dev.pm_domain = &omap_device_pm_domain;
869 return platform_device_add(pdev);
870}
871
872
873/* Public functions for use by device drivers through struct platform_data */
874
875/**
876 * omap_device_enable - fully activate an omap_device
877 * @od: struct omap_device * to activate
878 *
879 * Do whatever is necessary for the hwmods underlying omap_device @od
880 * to be accessible and ready to operate. This generally involves
881 * enabling clocks, setting SYSCONFIG registers; and in the future may
882 * involve remuxing pins. Device drivers should call this function
883 * (through platform_data function pointers) where they would normally
884 * enable clocks, etc. Returns -EINVAL if called when the omap_device
885 * is already enabled, or passes along the return value of
886 * _omap_device_activate().
887 */
888int omap_device_enable(struct platform_device *pdev)
889{
890 int ret;
891 struct omap_device *od;
892
893 od = to_omap_device(pdev);
894
895 if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
896 dev_warn(&pdev->dev,
897 "omap_device: %s() called from invalid state %d\n",
898 __func__, od->_state);
899 return -EINVAL;
900 }
901
902 /* Enable everything if we're enabling this device from scratch */
903 if (od->_state == OMAP_DEVICE_STATE_UNKNOWN)
904 od->pm_lat_level = od->pm_lats_cnt;
905
906 ret = _omap_device_activate(od, IGNORE_WAKEUP_LAT);
907
908 od->dev_wakeup_lat = 0;
909 od->_dev_wakeup_lat_limit = UINT_MAX;
910 od->_state = OMAP_DEVICE_STATE_ENABLED;
911
912 return ret;
913}
914
915/**
916 * omap_device_idle - idle an omap_device
917 * @od: struct omap_device * to idle
918 *
919 * Idle omap_device @od by calling as many .deactivate_func() entries
920 * in the omap_device's pm_lats table as is possible without exceeding
921 * the device's maximum wakeup latency limit, pm_lat_limit. Device
922 * drivers should call this function (through platform_data function
923 * pointers) where they would normally disable clocks after operations
924 * complete, etc.. Returns -EINVAL if the omap_device is not
925 * currently enabled, or passes along the return value of
926 * _omap_device_deactivate().
927 */
928int omap_device_idle(struct platform_device *pdev)
929{
930 int ret;
931 struct omap_device *od;
932
933 od = to_omap_device(pdev);
934
935 if (od->_state != OMAP_DEVICE_STATE_ENABLED) {
936 dev_warn(&pdev->dev,
937 "omap_device: %s() called from invalid state %d\n",
938 __func__, od->_state);
939 return -EINVAL;
940 }
941
942 ret = _omap_device_deactivate(od, USE_WAKEUP_LAT);
943
944 od->_state = OMAP_DEVICE_STATE_IDLE;
945
946 return ret;
947}
948
949/**
950 * omap_device_shutdown - shut down an omap_device
951 * @od: struct omap_device * to shut down
952 *
953 * Shut down omap_device @od by calling all .deactivate_func() entries
954 * in the omap_device's pm_lats table and then shutting down all of
955 * the underlying omap_hwmods. Used when a device is being "removed"
956 * or a device driver is being unloaded. Returns -EINVAL if the
957 * omap_device is not currently enabled or idle, or passes along the
958 * return value of _omap_device_deactivate().
959 */
960int omap_device_shutdown(struct platform_device *pdev)
961{
962 int ret, i;
963 struct omap_device *od;
964
965 od = to_omap_device(pdev);
966
967 if (od->_state != OMAP_DEVICE_STATE_ENABLED &&
968 od->_state != OMAP_DEVICE_STATE_IDLE) {
969 dev_warn(&pdev->dev,
970 "omap_device: %s() called from invalid state %d\n",
971 __func__, od->_state);
972 return -EINVAL;
973 }
974
975 ret = _omap_device_deactivate(od, IGNORE_WAKEUP_LAT);
976
977 for (i = 0; i < od->hwmods_cnt; i++)
978 omap_hwmod_shutdown(od->hwmods[i]);
979
980 od->_state = OMAP_DEVICE_STATE_SHUTDOWN;
981
982 return ret;
983}
984
985/**
986 * omap_device_assert_hardreset - set a device's hardreset line
987 * @pdev: struct platform_device * to reset
988 * @name: const char * name of the reset line
989 *
990 * Set the hardreset line identified by @name on the IP blocks
991 * associated with the hwmods backing the platform_device @pdev. All
992 * of the hwmods associated with @pdev must have the same hardreset
993 * line linked to them for this to work. Passes along the return value
994 * of omap_hwmod_assert_hardreset() in the event of any failure, or
995 * returns 0 upon success.
996 */
997int omap_device_assert_hardreset(struct platform_device *pdev, const char *name)
998{
999 struct omap_device *od = to_omap_device(pdev);
1000 int ret = 0;
1001 int i;
1002
1003 for (i = 0; i < od->hwmods_cnt; i++) {
1004 ret = omap_hwmod_assert_hardreset(od->hwmods[i], name);
1005 if (ret)
1006 break;
1007 }
1008
1009 return ret;
1010}
1011
1012/**
1013 * omap_device_deassert_hardreset - release a device's hardreset line
1014 * @pdev: struct platform_device * to reset
1015 * @name: const char * name of the reset line
1016 *
1017 * Release the hardreset line identified by @name on the IP blocks
1018 * associated with the hwmods backing the platform_device @pdev. All
1019 * of the hwmods associated with @pdev must have the same hardreset
1020 * line linked to them for this to work. Passes along the return
1021 * value of omap_hwmod_deassert_hardreset() in the event of any
1022 * failure, or returns 0 upon success.
1023 */
1024int omap_device_deassert_hardreset(struct platform_device *pdev,
1025 const char *name)
1026{
1027 struct omap_device *od = to_omap_device(pdev);
1028 int ret = 0;
1029 int i;
1030
1031 for (i = 0; i < od->hwmods_cnt; i++) {
1032 ret = omap_hwmod_deassert_hardreset(od->hwmods[i], name);
1033 if (ret)
1034 break;
1035 }
1036
1037 return ret;
1038}
1039
1040/**
1041 * omap_device_align_pm_lat - activate/deactivate device to match wakeup lat lim
1042 * @od: struct omap_device *
1043 *
1044 * When a device's maximum wakeup latency limit changes, call some of
1045 * the .activate_func or .deactivate_func function pointers in the
1046 * omap_device's pm_lats array to ensure that the device's maximum
1047 * wakeup latency is less than or equal to the new latency limit.
1048 * Intended to be called by OMAP PM code whenever a device's maximum
1049 * wakeup latency limit changes (e.g., via
1050 * omap_pm_set_dev_wakeup_lat()). Returns 0 if nothing needs to be
1051 * done (e.g., if the omap_device is not currently idle, or if the
1052 * wakeup latency is already current with the new limit) or passes
1053 * along the return value of _omap_device_deactivate() or
1054 * _omap_device_activate().
1055 */
1056int omap_device_align_pm_lat(struct platform_device *pdev,
1057 u32 new_wakeup_lat_limit)
1058{
1059 int ret = -EINVAL;
1060 struct omap_device *od;
1061
1062 od = to_omap_device(pdev);
1063
1064 if (new_wakeup_lat_limit == od->dev_wakeup_lat)
1065 return 0;
1066
1067 od->_dev_wakeup_lat_limit = new_wakeup_lat_limit;
1068
1069 if (od->_state != OMAP_DEVICE_STATE_IDLE)
1070 return 0;
1071 else if (new_wakeup_lat_limit > od->dev_wakeup_lat)
1072 ret = _omap_device_deactivate(od, USE_WAKEUP_LAT);
1073 else if (new_wakeup_lat_limit < od->dev_wakeup_lat)
1074 ret = _omap_device_activate(od, USE_WAKEUP_LAT);
1075
1076 return ret;
1077}
1078
1079/**
1080 * omap_device_get_pwrdm - return the powerdomain * associated with @od
1081 * @od: struct omap_device *
1082 *
1083 * Return the powerdomain associated with the first underlying
1084 * omap_hwmod for this omap_device. Intended for use by core OMAP PM
1085 * code. Returns NULL on error or a struct powerdomain * upon
1086 * success.
1087 */
1088struct powerdomain *omap_device_get_pwrdm(struct omap_device *od)
1089{
1090 /*
1091 * XXX Assumes that all omap_hwmod powerdomains are identical.
1092 * This may not necessarily be true. There should be a sanity
1093 * check in here to WARN() if any difference appears.
1094 */
1095 if (!od->hwmods_cnt)
1096 return NULL;
1097
1098 return omap_hwmod_get_pwrdm(od->hwmods[0]);
1099}
1100
1101/**
1102 * omap_device_get_mpu_rt_va - return the MPU's virtual addr for the hwmod base
1103 * @od: struct omap_device *
1104 *
1105 * Return the MPU's virtual address for the base of the hwmod, from
1106 * the ioremap() that the hwmod code does. Only valid if there is one
1107 * hwmod associated with this device. Returns NULL if there are zero
1108 * or more than one hwmods associated with this omap_device;
1109 * otherwise, passes along the return value from
1110 * omap_hwmod_get_mpu_rt_va().
1111 */
1112void __iomem *omap_device_get_rt_va(struct omap_device *od)
1113{
1114 if (od->hwmods_cnt != 1)
1115 return NULL;
1116
1117 return omap_hwmod_get_mpu_rt_va(od->hwmods[0]);
1118}
1119
1120/**
1121 * omap_device_get_by_hwmod_name() - convert a hwmod name to
1122 * device pointer.
1123 * @oh_name: name of the hwmod device
1124 *
1125 * Returns back a struct device * pointer associated with a hwmod
1126 * device represented by a hwmod_name
1127 */
1128struct device *omap_device_get_by_hwmod_name(const char *oh_name)
1129{
1130 struct omap_hwmod *oh;
1131
1132 if (!oh_name) {
1133 WARN(1, "%s: no hwmod name!\n", __func__);
1134 return ERR_PTR(-EINVAL);
1135 }
1136
1137 oh = omap_hwmod_lookup(oh_name);
1138 if (IS_ERR_OR_NULL(oh)) {
1139 WARN(1, "%s: no hwmod for %s\n", __func__,
1140 oh_name);
1141 return ERR_PTR(oh ? PTR_ERR(oh) : -ENODEV);
1142 }
1143 if (IS_ERR_OR_NULL(oh->od)) {
1144 WARN(1, "%s: no omap_device for %s\n", __func__,
1145 oh_name);
1146 return ERR_PTR(oh->od ? PTR_ERR(oh->od) : -ENODEV);
1147 }
1148
1149 if (IS_ERR_OR_NULL(oh->od->pdev))
1150 return ERR_PTR(oh->od->pdev ? PTR_ERR(oh->od->pdev) : -ENODEV);
1151
1152 return &oh->od->pdev->dev;
1153}
1154EXPORT_SYMBOL(omap_device_get_by_hwmod_name);
1155
1156/*
1157 * Public functions intended for use in omap_device_pm_latency
1158 * .activate_func and .deactivate_func function pointers
1159 */
1160
1161/**
1162 * omap_device_enable_hwmods - call omap_hwmod_enable() on all hwmods
1163 * @od: struct omap_device *od
1164 *
1165 * Enable all underlying hwmods. Returns 0.
1166 */
1167int omap_device_enable_hwmods(struct omap_device *od)
1168{
1169 int i;
1170
1171 for (i = 0; i < od->hwmods_cnt; i++)
1172 omap_hwmod_enable(od->hwmods[i]);
1173
1174 /* XXX pass along return value here? */
1175 return 0;
1176}
1177
1178/**
1179 * omap_device_idle_hwmods - call omap_hwmod_idle() on all hwmods
1180 * @od: struct omap_device *od
1181 *
1182 * Idle all underlying hwmods. Returns 0.
1183 */
1184int omap_device_idle_hwmods(struct omap_device *od)
1185{
1186 int i;
1187
1188 for (i = 0; i < od->hwmods_cnt; i++)
1189 omap_hwmod_idle(od->hwmods[i]);
1190
1191 /* XXX pass along return value here? */
1192 return 0;
1193}
1194
1195/**
1196 * omap_device_disable_clocks - disable all main and interface clocks
1197 * @od: struct omap_device *od
1198 *
1199 * Disable the main functional clock and interface clock for all of the
1200 * omap_hwmods associated with the omap_device. Returns 0.
1201 */
1202int omap_device_disable_clocks(struct omap_device *od)
1203{
1204 int i;
1205
1206 for (i = 0; i < od->hwmods_cnt; i++)
1207 omap_hwmod_disable_clocks(od->hwmods[i]);
1208
1209 /* XXX pass along return value here? */
1210 return 0;
1211}
1212
1213/**
1214 * omap_device_enable_clocks - enable all main and interface clocks
1215 * @od: struct omap_device *od
1216 *
1217 * Enable the main functional clock and interface clock for all of the
1218 * omap_hwmods associated with the omap_device. Returns 0.
1219 */
1220int omap_device_enable_clocks(struct omap_device *od)
1221{
1222 int i;
1223
1224 for (i = 0; i < od->hwmods_cnt; i++)
1225 omap_hwmod_enable_clocks(od->hwmods[i]);
1226
1227 /* XXX pass along return value here? */
1228 return 0;
1229}
1230
1231static struct notifier_block platform_nb = {
1232 .notifier_call = _omap_device_notifier_call,
1233};
1234
1235static int __init omap_device_init(void)
1236{
1237 bus_register_notifier(&platform_bus_type, &platform_nb);
1238 return 0;
1239}
1240core_initcall(omap_device_init);
1241
1242/**
1243 * omap_device_late_idle - idle devices without drivers
1244 * @dev: struct device * associated with omap_device
1245 * @data: unused
1246 *
1247 * Check the driver bound status of this device, and idle it
1248 * if there is no driver attached.
1249 */
1250static int __init omap_device_late_idle(struct device *dev, void *data)
1251{
1252 struct platform_device *pdev = to_platform_device(dev);
1253 struct omap_device *od = to_omap_device(pdev);
1254
1255 if (!od)
1256 return 0;
1257
1258 /*
1259 * If omap_device state is enabled, but has no driver bound,
1260 * idle it.
1261 */
1262 if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER) {
1263 if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
1264 dev_warn(dev, "%s: enabled but no driver. Idling\n",
1265 __func__);
1266 omap_device_idle(pdev);
1267 }
1268 }
1269
1270 return 0;
1271}
1272
1273static int __init omap_device_late_init(void)
1274{
1275 bus_for_each_dev(&platform_bus_type, NULL, NULL, omap_device_late_idle);
1276 return 0;
1277}
1278late_initcall(omap_device_late_init);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 28acb383e7df..743fc2836f7a 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -20,198 +20,20 @@
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/io.h> 21#include <linux/io.h>
22 22
23#include <asm/fncpy.h>
23#include <asm/tlb.h> 24#include <asm/tlb.h>
24#include <asm/cacheflush.h> 25#include <asm/cacheflush.h>
25 26
26#include <asm/mach/map.h> 27#include <asm/mach/map.h>
27 28
28#include <plat/sram.h>
29#include <plat/cpu.h>
30
31#include "sram.h"
32
33/* XXX These "sideways" includes will disappear when sram.c becomes a driver */
34#include "../mach-omap2/iomap.h"
35#include "../mach-omap2/prm2xxx_3xxx.h"
36#include "../mach-omap2/sdrc.h"
37
38#define OMAP1_SRAM_PA 0x20000000
39#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
40#define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
41#ifdef CONFIG_OMAP4_ERRATA_I688
42#define OMAP4_SRAM_PUB_PA OMAP4_SRAM_PA
43#else
44#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
45#endif
46#define OMAP5_SRAM_PA 0x40300000
47
48#if defined(CONFIG_ARCH_OMAP2PLUS)
49#define SRAM_BOOTLOADER_SZ 0x00
50#else
51#define SRAM_BOOTLOADER_SZ 0x80
52#endif
53
54#define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048)
55#define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050)
56#define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058)
57
58#define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848)
59#define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850)
60#define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
61#define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880)
62#define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048)
63
64#define GP_DEVICE 0x300
65
66#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) 29#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
67 30
68static unsigned long omap_sram_start;
69static void __iomem *omap_sram_base; 31static void __iomem *omap_sram_base;
70static unsigned long omap_sram_skip; 32static unsigned long omap_sram_skip;
71static unsigned long omap_sram_size; 33static unsigned long omap_sram_size;
72static void __iomem *omap_sram_ceil; 34static void __iomem *omap_sram_ceil;
73 35
74/* 36/*
75 * Depending on the target RAMFS firewall setup, the public usable amount of
76 * SRAM varies. The default accessible size for all device types is 2k. A GP
77 * device allows ARM11 but not other initiators for full size. This
78 * functionality seems ok until some nice security API happens.
79 */
80static int is_sram_locked(void)
81{
82 if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
83 /* RAMFW: R/W access to all initiators for all qualifier sets */
84 if (cpu_is_omap242x()) {
85 __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
86 __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
87 __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
88 }
89 if (cpu_is_omap34xx()) {
90 __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
91 __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
92 __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
93 __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
94 __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
95 }
96 return 0;
97 } else
98 return 1; /* assume locked with no PPA or security driver */
99}
100
101/*
102 * The amount of SRAM depends on the core type.
103 * Note that we cannot try to test for SRAM here because writes
104 * to secure SRAM will hang the system. Also the SRAM is not
105 * yet mapped at this point.
106 */
107static void __init omap_detect_sram(void)
108{
109 omap_sram_skip = SRAM_BOOTLOADER_SZ;
110 if (cpu_class_is_omap2()) {
111 if (is_sram_locked()) {
112 if (cpu_is_omap34xx()) {
113 omap_sram_start = OMAP3_SRAM_PUB_PA;
114 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
115 (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
116 omap_sram_size = 0x7000; /* 28K */
117 omap_sram_skip += SZ_16K;
118 } else {
119 omap_sram_size = 0x8000; /* 32K */
120 }
121 } else if (cpu_is_omap44xx()) {
122 omap_sram_start = OMAP4_SRAM_PUB_PA;
123 omap_sram_size = 0xa000; /* 40K */
124 } else if (soc_is_omap54xx()) {
125 omap_sram_start = OMAP5_SRAM_PA;
126 omap_sram_size = SZ_128K; /* 128KB */
127 } else {
128 omap_sram_start = OMAP2_SRAM_PUB_PA;
129 omap_sram_size = 0x800; /* 2K */
130 }
131 } else {
132 if (soc_is_am33xx()) {
133 omap_sram_start = AM33XX_SRAM_PA;
134 omap_sram_size = 0x10000; /* 64K */
135 } else if (cpu_is_omap34xx()) {
136 omap_sram_start = OMAP3_SRAM_PA;
137 omap_sram_size = 0x10000; /* 64K */
138 } else if (cpu_is_omap44xx()) {
139 omap_sram_start = OMAP4_SRAM_PA;
140 omap_sram_size = 0xe000; /* 56K */
141 } else if (soc_is_omap54xx()) {
142 omap_sram_start = OMAP5_SRAM_PA;
143 omap_sram_size = SZ_128K; /* 128KB */
144 } else {
145 omap_sram_start = OMAP2_SRAM_PA;
146 if (cpu_is_omap242x())
147 omap_sram_size = 0xa0000; /* 640K */
148 else if (cpu_is_omap243x())
149 omap_sram_size = 0x10000; /* 64K */
150 }
151 }
152 } else {
153 omap_sram_start = OMAP1_SRAM_PA;
154
155 if (cpu_is_omap7xx())
156 omap_sram_size = 0x32000; /* 200K */
157 else if (cpu_is_omap15xx())
158 omap_sram_size = 0x30000; /* 192K */
159 else if (cpu_is_omap1610() || cpu_is_omap1611() ||
160 cpu_is_omap1621() || cpu_is_omap1710())
161 omap_sram_size = 0x4000; /* 16K */
162 else {
163 pr_err("Could not detect SRAM size\n");
164 omap_sram_size = 0x4000;
165 }
166 }
167}
168
169/*
170 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
171 */
172static void __init omap_map_sram(void)
173{
174 int cached = 1;
175
176 if (omap_sram_size == 0)
177 return;
178
179#ifdef CONFIG_OMAP4_ERRATA_I688
180 if (cpu_is_omap44xx()) {
181 omap_sram_start += PAGE_SIZE;
182 omap_sram_size -= SZ_16K;
183 }
184#endif
185 if (cpu_is_omap34xx()) {
186 /*
187 * SRAM must be marked as non-cached on OMAP3 since the
188 * CORE DPLL M2 divider change code (in SRAM) runs with the
189 * SDRAM controller disabled, and if it is marked cached,
190 * the ARM may attempt to write cache lines back to SDRAM
191 * which will cause the system to hang.
192 */
193 cached = 0;
194 }
195
196 omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
197 omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size,
198 cached);
199 if (!omap_sram_base) {
200 pr_err("SRAM: Could not map\n");
201 return;
202 }
203
204 omap_sram_ceil = omap_sram_base + omap_sram_size;
205
206 /*
207 * Looks like we need to preserve some bootloader code at the
208 * beginning of SRAM for jumping to flash for reboot to work...
209 */
210 memset_io(omap_sram_base + omap_sram_skip, 0,
211 omap_sram_size - omap_sram_skip);
212}
213
214/*
215 * Memory allocator for SRAM: calculates the new ceiling address 37 * Memory allocator for SRAM: calculates the new ceiling address
216 * for pushing a function using the fncpy API. 38 * for pushing a function using the fncpy API.
217 * 39 *
@@ -236,171 +58,39 @@ void *omap_sram_push_address(unsigned long size)
236 return (void *)omap_sram_ceil; 58 return (void *)omap_sram_ceil;
237} 59}
238 60
239#ifdef CONFIG_ARCH_OMAP1 61/*
240 62 * The SRAM context is lost during off-idle and stack
241static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl); 63 * needs to be reset.
242 64 */
243void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl) 65void omap_sram_reset(void)
244{
245 BUG_ON(!_omap_sram_reprogram_clock);
246 /* On 730, bit 13 must always be 1 */
247 if (cpu_is_omap7xx())
248 ckctl |= 0x2000;
249 _omap_sram_reprogram_clock(dpllctl, ckctl);
250}
251
252static int __init omap1_sram_init(void)
253{
254 _omap_sram_reprogram_clock =
255 omap_sram_push(omap1_sram_reprogram_clock,
256 omap1_sram_reprogram_clock_sz);
257
258 return 0;
259}
260
261#else
262#define omap1_sram_init() do {} while (0)
263#endif
264
265#if defined(CONFIG_ARCH_OMAP2)
266
267static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
268 u32 base_cs, u32 force_unlock);
269
270void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
271 u32 base_cs, u32 force_unlock)
272{
273 BUG_ON(!_omap2_sram_ddr_init);
274 _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
275 base_cs, force_unlock);
276}
277
278static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
279 u32 mem_type);
280
281void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
282{
283 BUG_ON(!_omap2_sram_reprogram_sdrc);
284 _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
285}
286
287static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
288
289u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
290{
291 BUG_ON(!_omap2_set_prcm);
292 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
293}
294#endif
295
296#ifdef CONFIG_SOC_OMAP2420
297static int __init omap242x_sram_init(void)
298{
299 _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
300 omap242x_sram_ddr_init_sz);
301
302 _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
303 omap242x_sram_reprogram_sdrc_sz);
304
305 _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
306 omap242x_sram_set_prcm_sz);
307
308 return 0;
309}
310#else
311static inline int omap242x_sram_init(void)
312{
313 return 0;
314}
315#endif
316
317#ifdef CONFIG_SOC_OMAP2430
318static int __init omap243x_sram_init(void)
319{
320 _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
321 omap243x_sram_ddr_init_sz);
322
323 _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
324 omap243x_sram_reprogram_sdrc_sz);
325
326 _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
327 omap243x_sram_set_prcm_sz);
328
329 return 0;
330}
331#else
332static inline int omap243x_sram_init(void)
333{
334 return 0;
335}
336#endif
337
338#ifdef CONFIG_ARCH_OMAP3
339
340static u32 (*_omap3_sram_configure_core_dpll)(
341 u32 m2, u32 unlock_dll, u32 f, u32 inc,
342 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
343 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
344 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
345 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
346
347u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
348 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
349 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
350 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
351 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
352{
353 BUG_ON(!_omap3_sram_configure_core_dpll);
354 return _omap3_sram_configure_core_dpll(
355 m2, unlock_dll, f, inc,
356 sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
357 sdrc_actim_ctrl_b_0, sdrc_mr_0,
358 sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
359 sdrc_actim_ctrl_b_1, sdrc_mr_1);
360}
361
362void omap3_sram_restore_context(void)
363{ 66{
364 omap_sram_ceil = omap_sram_base + omap_sram_size; 67 omap_sram_ceil = omap_sram_base + omap_sram_size;
365
366 _omap3_sram_configure_core_dpll =
367 omap_sram_push(omap3_sram_configure_core_dpll,
368 omap3_sram_configure_core_dpll_sz);
369 omap_push_sram_idle();
370} 68}
371 69
372static inline int omap34xx_sram_init(void) 70/*
373{ 71 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
374 omap3_sram_restore_context(); 72 */
375 return 0; 73void __init omap_map_sram(unsigned long start, unsigned long size,
376} 74 unsigned long skip, int cached)
377#else
378static inline int omap34xx_sram_init(void)
379{
380 return 0;
381}
382#endif /* CONFIG_ARCH_OMAP3 */
383
384static inline int am33xx_sram_init(void)
385{ 75{
386 return 0; 76 if (size == 0)
387} 77 return;
388 78
389int __init omap_sram_init(void) 79 start = ROUND_DOWN(start, PAGE_SIZE);
390{ 80 omap_sram_size = size;
391 omap_detect_sram(); 81 omap_sram_skip = skip;
392 omap_map_sram(); 82 omap_sram_base = __arm_ioremap_exec(start, size, cached);
83 if (!omap_sram_base) {
84 pr_err("SRAM: Could not map\n");
85 return;
86 }
393 87
394 if (!(cpu_class_is_omap2())) 88 omap_sram_reset();
395 omap1_sram_init();
396 else if (cpu_is_omap242x())
397 omap242x_sram_init();
398 else if (cpu_is_omap2430())
399 omap243x_sram_init();
400 else if (soc_is_am33xx())
401 am33xx_sram_init();
402 else if (cpu_is_omap34xx())
403 omap34xx_sram_init();
404 89
405 return 0; 90 /*
91 * Looks like we need to preserve some bootloader code at the
92 * beginning of SRAM for jumping to flash for reboot to work...
93 */
94 memset_io(omap_sram_base + omap_sram_skip, 0,
95 omap_sram_size - omap_sram_skip);
406} 96}
diff --git a/arch/arm/plat-omap/sram.h b/arch/arm/plat-omap/sram.h
deleted file mode 100644
index 29b43ef97f20..000000000000
--- a/arch/arm/plat-omap/sram.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef __PLAT_OMAP_SRAM_H__
2#define __PLAT_OMAP_SRAM_H__
3
4extern int __init omap_sram_init(void);
5
6#endif /* __PLAT_OMAP_SRAM_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 21:42:52 -0500