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authorTony Lindgren <tony@atomide.com>2009-10-15 21:16:10 -0400
committerTony Lindgren <tony@atomide.com>2009-10-15 21:16:10 -0400
commita2bb28a0dbcc1370104a543d25eb28aab81d4a91 (patch)
treeaf81c8fe399a5e828b584617ffe6ee3df9f6fc07 /arch/arm/plat-omap
parent012abeea669ea49636cf952d13298bb68654146a (diff)
parentf8631e7bba34d46d6ccea4cd90f7a0482770ff70 (diff)
Merge branch 'omap7xx-fortony-rc3' of git://robotfuzz.com/linwizard-kernel into omap7xx
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r--arch/arm/plat-omap/devices.c22
-rw-r--r--arch/arm/plat-omap/gpio.c227
-rw-r--r--arch/arm/plat-omap/include/mach/entry-macro.S8
-rw-r--r--arch/arm/plat-omap/include/mach/hardware.h2
-rw-r--r--arch/arm/plat-omap/include/mach/irqs.h229
-rw-r--r--arch/arm/plat-omap/include/mach/mcbsp.h6
-rw-r--r--arch/arm/plat-omap/include/mach/mux.h100
-rw-r--r--arch/arm/plat-omap/include/mach/omap7xx.h104
-rw-r--r--arch/arm/plat-omap/include/mach/uncompress.h3
-rw-r--r--arch/arm/plat-omap/io.c14
-rw-r--r--arch/arm/plat-omap/usb.c10
11 files changed, 297 insertions, 428 deletions
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index a64b692a1bfe..d2f54753b016 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -113,17 +113,17 @@ static void omap_init_kp(void)
113 omap_cfg_reg(E19_1610_KBR4); 113 omap_cfg_reg(E19_1610_KBR4);
114 omap_cfg_reg(N19_1610_KBR5); 114 omap_cfg_reg(N19_1610_KBR5);
115 } else if (machine_is_omap_perseus2() || machine_is_omap_fsample()) { 115 } else if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
116 omap_cfg_reg(E2_730_KBR0); 116 omap_cfg_reg(E2_7XX_KBR0);
117 omap_cfg_reg(J7_730_KBR1); 117 omap_cfg_reg(J7_7XX_KBR1);
118 omap_cfg_reg(E1_730_KBR2); 118 omap_cfg_reg(E1_7XX_KBR2);
119 omap_cfg_reg(F3_730_KBR3); 119 omap_cfg_reg(F3_7XX_KBR3);
120 omap_cfg_reg(D2_730_KBR4); 120 omap_cfg_reg(D2_7XX_KBR4);
121 121
122 omap_cfg_reg(C2_730_KBC0); 122 omap_cfg_reg(C2_7XX_KBC0);
123 omap_cfg_reg(D3_730_KBC1); 123 omap_cfg_reg(D3_7XX_KBC1);
124 omap_cfg_reg(E4_730_KBC2); 124 omap_cfg_reg(E4_7XX_KBC2);
125 omap_cfg_reg(F4_730_KBC3); 125 omap_cfg_reg(F4_7XX_KBC3);
126 omap_cfg_reg(E3_730_KBC4); 126 omap_cfg_reg(E3_7XX_KBC4);
127 } else if (machine_is_omap_h4()) { 127 } else if (machine_is_omap_h4()) {
128 omap_cfg_reg(T19_24XX_KBR0); 128 omap_cfg_reg(T19_24XX_KBR0);
129 omap_cfg_reg(R19_24XX_KBR1); 129 omap_cfg_reg(R19_24XX_KBR1);
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 71ebd7fcfea1..b0c73613a4e9 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -68,36 +68,20 @@
68#define OMAP1610_GPIO_SET_DATAOUT 0x00f0 68#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
69 69
70/* 70/*
71 * OMAP730 specific GPIO registers 71 * OMAP7XX specific GPIO registers
72 */ 72 */
73#define OMAP730_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000) 73#define OMAP7XX_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000)
74#define OMAP730_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800) 74#define OMAP7XX_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800)
75#define OMAP730_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000) 75#define OMAP7XX_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000)
76#define OMAP730_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800) 76#define OMAP7XX_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800)
77#define OMAP730_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000) 77#define OMAP7XX_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000)
78#define OMAP730_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800) 78#define OMAP7XX_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800)
79#define OMAP730_GPIO_DATA_INPUT 0x00 79#define OMAP7XX_GPIO_DATA_INPUT 0x00
80#define OMAP730_GPIO_DATA_OUTPUT 0x04 80#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
81#define OMAP730_GPIO_DIR_CONTROL 0x08 81#define OMAP7XX_GPIO_DIR_CONTROL 0x08
82#define OMAP730_GPIO_INT_CONTROL 0x0c 82#define OMAP7XX_GPIO_INT_CONTROL 0x0c
83#define OMAP730_GPIO_INT_MASK 0x10 83#define OMAP7XX_GPIO_INT_MASK 0x10
84#define OMAP730_GPIO_INT_STATUS 0x14 84#define OMAP7XX_GPIO_INT_STATUS 0x14
85
86/*
87 * OMAP850 specific GPIO registers
88 */
89#define OMAP850_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000)
90#define OMAP850_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800)
91#define OMAP850_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000)
92#define OMAP850_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800)
93#define OMAP850_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000)
94#define OMAP850_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800)
95#define OMAP850_GPIO_DATA_INPUT 0x00
96#define OMAP850_GPIO_DATA_OUTPUT 0x04
97#define OMAP850_GPIO_DIR_CONTROL 0x08
98#define OMAP850_GPIO_INT_CONTROL 0x0c
99#define OMAP850_GPIO_INT_MASK 0x10
100#define OMAP850_GPIO_INT_STATUS 0x14
101 85
102#define OMAP1_MPUIO_VBASE OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE) 86#define OMAP1_MPUIO_VBASE OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE)
103 87
@@ -215,8 +199,7 @@ struct gpio_bank {
215#define METHOD_MPUIO 0 199#define METHOD_MPUIO 0
216#define METHOD_GPIO_1510 1 200#define METHOD_GPIO_1510 1
217#define METHOD_GPIO_1610 2 201#define METHOD_GPIO_1610 2
218#define METHOD_GPIO_730 3 202#define METHOD_GPIO_7XX 3
219#define METHOD_GPIO_850 4
220#define METHOD_GPIO_24XX 5 203#define METHOD_GPIO_24XX 5
221 204
222#ifdef CONFIG_ARCH_OMAP16XX 205#ifdef CONFIG_ARCH_OMAP16XX
@@ -236,31 +219,18 @@ static struct gpio_bank gpio_bank_1510[2] = {
236}; 219};
237#endif 220#endif
238 221
239#ifdef CONFIG_ARCH_OMAP730 222#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
240static struct gpio_bank gpio_bank_730[7] = { 223static struct gpio_bank gpio_bank_7xx[7] = {
241 { OMAP1_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, 224 { OMAP1_MPUIO_VBASE, INT_7XX_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
242 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 }, 225 { OMAP7XX_GPIO1_BASE, INT_7XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_7XX },
243 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 }, 226 { OMAP7XX_GPIO2_BASE, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_7XX },
244 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 }, 227 { OMAP7XX_GPIO3_BASE, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_7XX },
245 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 }, 228 { OMAP7XX_GPIO4_BASE, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_7XX },
246 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 }, 229 { OMAP7XX_GPIO5_BASE, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_7XX },
247 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 }, 230 { OMAP7XX_GPIO6_BASE, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_7XX },
248}; 231};
249#endif 232#endif
250 233
251#ifdef CONFIG_ARCH_OMAP850
252static struct gpio_bank gpio_bank_850[7] = {
253 { OMAP1_MPUIO_VBASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
254 { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 },
255 { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 },
256 { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 },
257 { OMAP850_GPIO4_BASE, INT_850_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_850 },
258 { OMAP850_GPIO5_BASE, INT_850_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_850 },
259 { OMAP850_GPIO6_BASE, INT_850_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_850 },
260};
261#endif
262
263
264#ifdef CONFIG_ARCH_OMAP24XX 234#ifdef CONFIG_ARCH_OMAP24XX
265 235
266static struct gpio_bank gpio_bank_242x[4] = { 236static struct gpio_bank gpio_bank_242x[4] = {
@@ -402,14 +372,9 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
402 reg += OMAP1610_GPIO_DIRECTION; 372 reg += OMAP1610_GPIO_DIRECTION;
403 break; 373 break;
404#endif 374#endif
405#ifdef CONFIG_ARCH_OMAP730 375#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
406 case METHOD_GPIO_730: 376 case METHOD_GPIO_7XX:
407 reg += OMAP730_GPIO_DIR_CONTROL; 377 reg += OMAP7XX_GPIO_DIR_CONTROL;
408 break;
409#endif
410#ifdef CONFIG_ARCH_OMAP850
411 case METHOD_GPIO_850:
412 reg += OMAP850_GPIO_DIR_CONTROL;
413 break; 378 break;
414#endif 379#endif
415#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 380#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
@@ -469,19 +434,9 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
469 l = 1 << gpio; 434 l = 1 << gpio;
470 break; 435 break;
471#endif 436#endif
472#ifdef CONFIG_ARCH_OMAP730 437#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
473 case METHOD_GPIO_730: 438 case METHOD_GPIO_7XX:
474 reg += OMAP730_GPIO_DATA_OUTPUT; 439 reg += OMAP7XX_GPIO_DATA_OUTPUT;
475 l = __raw_readl(reg);
476 if (enable)
477 l |= 1 << gpio;
478 else
479 l &= ~(1 << gpio);
480 break;
481#endif
482#ifdef CONFIG_ARCH_OMAP850
483 case METHOD_GPIO_850:
484 reg += OMAP850_GPIO_DATA_OUTPUT;
485 l = __raw_readl(reg); 440 l = __raw_readl(reg);
486 if (enable) 441 if (enable)
487 l |= 1 << gpio; 442 l |= 1 << gpio;
@@ -537,14 +492,9 @@ static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
537 reg += OMAP1610_GPIO_DATAIN; 492 reg += OMAP1610_GPIO_DATAIN;
538 break; 493 break;
539#endif 494#endif
540#ifdef CONFIG_ARCH_OMAP730 495#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
541 case METHOD_GPIO_730: 496 case METHOD_GPIO_7XX:
542 reg += OMAP730_GPIO_DATA_INPUT; 497 reg += OMAP7XX_GPIO_DATA_INPUT;
543 break;
544#endif
545#ifdef CONFIG_ARCH_OMAP850
546 case METHOD_GPIO_850:
547 reg += OMAP850_GPIO_DATA_INPUT;
548 break; 498 break;
549#endif 499#endif
550#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 500#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
@@ -588,14 +538,9 @@ static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
588 reg += OMAP1610_GPIO_DATAOUT; 538 reg += OMAP1610_GPIO_DATAOUT;
589 break; 539 break;
590#endif 540#endif
591#ifdef CONFIG_ARCH_OMAP730 541#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
592 case METHOD_GPIO_730: 542 case METHOD_GPIO_7XX:
593 reg += OMAP730_GPIO_DATA_OUTPUT; 543 reg += OMAP7XX_GPIO_DATA_OUTPUT;
594 break;
595#endif
596#ifdef CONFIG_ARCH_OMAP850
597 case METHOD_GPIO_850:
598 reg += OMAP850_GPIO_DATA_OUTPUT;
599 break; 544 break;
600#endif 545#endif
601#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 546#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
@@ -797,21 +742,9 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
797 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); 742 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
798 break; 743 break;
799#endif 744#endif
800#ifdef CONFIG_ARCH_OMAP730 745#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
801 case METHOD_GPIO_730: 746 case METHOD_GPIO_7XX:
802 reg += OMAP730_GPIO_INT_CONTROL; 747 reg += OMAP7XX_GPIO_INT_CONTROL;
803 l = __raw_readl(reg);
804 if (trigger & IRQ_TYPE_EDGE_RISING)
805 l |= 1 << gpio;
806 else if (trigger & IRQ_TYPE_EDGE_FALLING)
807 l &= ~(1 << gpio);
808 else
809 goto bad;
810 break;
811#endif
812#ifdef CONFIG_ARCH_OMAP850
813 case METHOD_GPIO_850:
814 reg += OMAP850_GPIO_INT_CONTROL;
815 l = __raw_readl(reg); 748 l = __raw_readl(reg);
816 if (trigger & IRQ_TYPE_EDGE_RISING) 749 if (trigger & IRQ_TYPE_EDGE_RISING)
817 l |= 1 << gpio; 750 l |= 1 << gpio;
@@ -897,14 +830,9 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
897 reg += OMAP1610_GPIO_IRQSTATUS1; 830 reg += OMAP1610_GPIO_IRQSTATUS1;
898 break; 831 break;
899#endif 832#endif
900#ifdef CONFIG_ARCH_OMAP730 833#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
901 case METHOD_GPIO_730: 834 case METHOD_GPIO_7XX:
902 reg += OMAP730_GPIO_INT_STATUS; 835 reg += OMAP7XX_GPIO_INT_STATUS;
903 break;
904#endif
905#ifdef CONFIG_ARCH_OMAP850
906 case METHOD_GPIO_850:
907 reg += OMAP850_GPIO_INT_STATUS;
908 break; 836 break;
909#endif 837#endif
910#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 838#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
@@ -971,16 +899,9 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
971 mask = 0xffff; 899 mask = 0xffff;
972 break; 900 break;
973#endif 901#endif
974#ifdef CONFIG_ARCH_OMAP730 902#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
975 case METHOD_GPIO_730: 903 case METHOD_GPIO_7XX:
976 reg += OMAP730_GPIO_INT_MASK; 904 reg += OMAP7XX_GPIO_INT_MASK;
977 mask = 0xffffffff;
978 inv = 1;
979 break;
980#endif
981#ifdef CONFIG_ARCH_OMAP850
982 case METHOD_GPIO_850:
983 reg += OMAP850_GPIO_INT_MASK;
984 mask = 0xffffffff; 905 mask = 0xffffffff;
985 inv = 1; 906 inv = 1;
986 break; 907 break;
@@ -1044,19 +965,9 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
1044 l = gpio_mask; 965 l = gpio_mask;
1045 break; 966 break;
1046#endif 967#endif
1047#ifdef CONFIG_ARCH_OMAP730 968#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1048 case METHOD_GPIO_730: 969 case METHOD_GPIO_7XX:
1049 reg += OMAP730_GPIO_INT_MASK; 970 reg += OMAP7XX_GPIO_INT_MASK;
1050 l = __raw_readl(reg);
1051 if (enable)
1052 l &= ~(gpio_mask);
1053 else
1054 l |= gpio_mask;
1055 break;
1056#endif
1057#ifdef CONFIG_ARCH_OMAP850
1058 case METHOD_GPIO_850:
1059 reg += OMAP850_GPIO_INT_MASK;
1060 l = __raw_readl(reg); 971 l = __raw_readl(reg);
1061 if (enable) 972 if (enable)
1062 l &= ~(gpio_mask); 973 l &= ~(gpio_mask);
@@ -1249,13 +1160,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1249 if (bank->method == METHOD_GPIO_1610) 1160 if (bank->method == METHOD_GPIO_1610)
1250 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; 1161 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1251#endif 1162#endif
1252#ifdef CONFIG_ARCH_OMAP730 1163#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1253 if (bank->method == METHOD_GPIO_730) 1164 if (bank->method == METHOD_GPIO_7XX)
1254 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; 1165 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1255#endif
1256#ifdef CONFIG_ARCH_OMAP850
1257 if (bank->method == METHOD_GPIO_850)
1258 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
1259#endif 1166#endif
1260#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 1167#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1261 if (bank->method == METHOD_GPIO_24XX) 1168 if (bank->method == METHOD_GPIO_24XX)
@@ -1524,11 +1431,8 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
1524 case METHOD_GPIO_1610: 1431 case METHOD_GPIO_1610:
1525 reg += OMAP1610_GPIO_DIRECTION; 1432 reg += OMAP1610_GPIO_DIRECTION;
1526 break; 1433 break;
1527 case METHOD_GPIO_730: 1434 case METHOD_GPIO_7XX:
1528 reg += OMAP730_GPIO_DIR_CONTROL; 1435 reg += OMAP7XX_GPIO_DIR_CONTROL;
1529 break;
1530 case METHOD_GPIO_850:
1531 reg += OMAP850_GPIO_DIR_CONTROL;
1532 break; 1436 break;
1533 case METHOD_GPIO_24XX: 1437 case METHOD_GPIO_24XX:
1534 reg += OMAP24XX_GPIO_OE; 1438 reg += OMAP24XX_GPIO_OE;
@@ -1695,21 +1599,13 @@ static int __init _omap_gpio_init(void)
1695 (rev >> 4) & 0x0f, rev & 0x0f); 1599 (rev >> 4) & 0x0f, rev & 0x0f);
1696 } 1600 }
1697#endif 1601#endif
1698#ifdef CONFIG_ARCH_OMAP730 1602#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1699 if (cpu_is_omap730()) { 1603 if (cpu_is_omap7xx()) {
1700 printk(KERN_INFO "OMAP730 GPIO hardware\n"); 1604 printk(KERN_INFO "OMAP7XX GPIO hardware\n");
1701 gpio_bank_count = 7;
1702 gpio_bank = gpio_bank_730;
1703 }
1704#endif
1705#ifdef CONFIG_ARCH_OMAP850
1706 if (cpu_is_omap850()) {
1707 printk(KERN_INFO "OMAP850 GPIO hardware\n");
1708 gpio_bank_count = 7; 1605 gpio_bank_count = 7;
1709 gpio_bank = gpio_bank_850; 1606 gpio_bank = gpio_bank_7xx;
1710 } 1607 }
1711#endif 1608#endif
1712
1713#ifdef CONFIG_ARCH_OMAP24XX 1609#ifdef CONFIG_ARCH_OMAP24XX
1714 if (cpu_is_omap242x()) { 1610 if (cpu_is_omap242x()) {
1715 int rev; 1611 int rev;
@@ -1768,11 +1664,11 @@ static int __init _omap_gpio_init(void)
1768 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); 1664 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1769 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); 1665 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1770 } 1666 }
1771 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) { 1667 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1772 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); 1668 __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
1773 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); 1669 __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
1774 1670
1775 gpio_count = 32; /* 730 has 32-bit GPIOs */ 1671 gpio_count = 32; /* 7xx has 32-bit GPIOs */
1776 } 1672 }
1777 1673
1778#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1674#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
@@ -2160,8 +2056,7 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
2160 2056
2161 if (bank_is_mpuio(bank)) 2057 if (bank_is_mpuio(bank))
2162 gpio = OMAP_MPUIO(0); 2058 gpio = OMAP_MPUIO(0);
2163 else if (cpu_class_is_omap2() || cpu_is_omap730() || 2059 else if (cpu_class_is_omap2() || cpu_is_omap7xx())
2164 cpu_is_omap850())
2165 bankwidth = 32; 2060 bankwidth = 32;
2166 2061
2167 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { 2062 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S
index a5592991634d..abe086416e19 100644
--- a/arch/arm/plat-omap/include/mach/entry-macro.S
+++ b/arch/arm/plat-omap/include/mach/entry-macro.S
@@ -17,11 +17,11 @@
17 17
18#if defined(CONFIG_ARCH_OMAP1) 18#if defined(CONFIG_ARCH_OMAP1)
19 19
20#if defined(CONFIG_ARCH_OMAP730) && \ 20#if (defined(CONFIG_ARCH_OMAP730)||defined(CONFIG_ARCH_OMAP850)) && \
21 (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)) 21 (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
22#error "FIXME: OMAP730 doesn't support multiple-OMAP" 22#error "FIXME: OMAP7XX doesn't support multiple-OMAP"
23#elif defined(CONFIG_ARCH_OMAP730) 23#elif defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
24#define INT_IH2_IRQ INT_730_IH2_IRQ 24#define INT_IH2_IRQ INT_7XX_IH2_IRQ
25#elif defined(CONFIG_ARCH_OMAP15XX) 25#elif defined(CONFIG_ARCH_OMAP15XX)
26#define INT_IH2_IRQ INT_1510_IH2_IRQ 26#define INT_IH2_IRQ INT_1510_IH2_IRQ
27#elif defined(CONFIG_ARCH_OMAP16XX) 27#elif defined(CONFIG_ARCH_OMAP16XX)
diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/mach/hardware.h
index 26c1fbff08aa..99c42412c0a1 100644
--- a/arch/arm/plat-omap/include/mach/hardware.h
+++ b/arch/arm/plat-omap/include/mach/hardware.h
@@ -280,7 +280,7 @@
280 * --------------------------------------------------------------------------- 280 * ---------------------------------------------------------------------------
281 */ 281 */
282 282
283#include "omap730.h" 283#include "omap7xx.h"
284#include "omap1510.h" 284#include "omap1510.h"
285#include "omap16xx.h" 285#include "omap16xx.h"
286#include "omap24xx.h" 286#include "omap24xx.h"
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
index 28a165058b61..6a6d0281e1d5 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -86,49 +86,26 @@
86#define INT_1610_SSR_FIFO_0 29 86#define INT_1610_SSR_FIFO_0 29
87 87
88/* 88/*
89 * OMAP-730 specific IRQ numbers for interrupt handler 1 89 * OMAP-7xx specific IRQ numbers for interrupt handler 1
90 */ 90 */
91#define INT_730_IH2_FIQ 0 91#define INT_7XX_IH2_FIQ 0
92#define INT_730_IH2_IRQ 1 92#define INT_7XX_IH2_IRQ 1
93#define INT_730_USB_NON_ISO 2 93#define INT_7XX_USB_NON_ISO 2
94#define INT_730_USB_ISO 3 94#define INT_7XX_USB_ISO 3
95#define INT_730_ICR 4 95#define INT_7XX_ICR 4
96#define INT_730_EAC 5 96#define INT_7XX_EAC 5
97#define INT_730_GPIO_BANK1 6 97#define INT_7XX_GPIO_BANK1 6
98#define INT_730_GPIO_BANK2 7 98#define INT_7XX_GPIO_BANK2 7
99#define INT_730_GPIO_BANK3 8 99#define INT_7XX_GPIO_BANK3 8
100#define INT_730_McBSP2TX 10 100#define INT_7XX_McBSP2TX 10
101#define INT_730_McBSP2RX 11 101#define INT_7XX_McBSP2RX 11
102#define INT_730_McBSP2RX_OVF 12 102#define INT_7XX_McBSP2RX_OVF 12
103#define INT_730_LCD_LINE 14 103#define INT_7XX_LCD_LINE 14
104#define INT_730_GSM_PROTECT 15 104#define INT_7XX_GSM_PROTECT 15
105#define INT_730_TIMER3 16 105#define INT_7XX_TIMER3 16
106#define INT_730_GPIO_BANK5 17 106#define INT_7XX_GPIO_BANK5 17
107#define INT_730_GPIO_BANK6 18 107#define INT_7XX_GPIO_BANK6 18
108#define INT_730_SPGIO_WR 29 108#define INT_7XX_SPGIO_WR 29
109
110/*
111 * OMAP-850 specific IRQ numbers for interrupt handler 1
112 */
113#define INT_850_IH2_FIQ 0
114#define INT_850_IH2_IRQ 1
115#define INT_850_USB_NON_ISO 2
116#define INT_850_USB_ISO 3
117#define INT_850_ICR 4
118#define INT_850_EAC 5
119#define INT_850_GPIO_BANK1 6
120#define INT_850_GPIO_BANK2 7
121#define INT_850_GPIO_BANK3 8
122#define INT_850_McBSP2TX 10
123#define INT_850_McBSP2RX 11
124#define INT_850_McBSP2RX_OVF 12
125#define INT_850_LCD_LINE 14
126#define INT_850_GSM_PROTECT 15
127#define INT_850_TIMER3 16
128#define INT_850_GPIO_BANK5 17
129#define INT_850_GPIO_BANK6 18
130#define INT_850_SPGIO_WR 29
131
132 109
133/* 110/*
134 * IRQ numbers for interrupt handler 2 111 * IRQ numbers for interrupt handler 2
@@ -206,120 +183,62 @@
206#define INT_1610_SHA1MD5 (91 + IH2_BASE) 183#define INT_1610_SHA1MD5 (91 + IH2_BASE)
207 184
208/* 185/*
209 * OMAP-730 specific IRQ numbers for interrupt handler 2 186 * OMAP-7xx specific IRQ numbers for interrupt handler 2
210 */
211#define INT_730_HW_ERRORS (0 + IH2_BASE)
212#define INT_730_NFIQ_PWR_FAIL (1 + IH2_BASE)
213#define INT_730_CFCD (2 + IH2_BASE)
214#define INT_730_CFIREQ (3 + IH2_BASE)
215#define INT_730_I2C (4 + IH2_BASE)
216#define INT_730_PCC (5 + IH2_BASE)
217#define INT_730_MPU_EXT_NIRQ (6 + IH2_BASE)
218#define INT_730_SPI_100K_1 (7 + IH2_BASE)
219#define INT_730_SYREN_SPI (8 + IH2_BASE)
220#define INT_730_VLYNQ (9 + IH2_BASE)
221#define INT_730_GPIO_BANK4 (10 + IH2_BASE)
222#define INT_730_McBSP1TX (11 + IH2_BASE)
223#define INT_730_McBSP1RX (12 + IH2_BASE)
224#define INT_730_McBSP1RX_OF (13 + IH2_BASE)
225#define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE)
226#define INT_730_UART_MODEM_1 (15 + IH2_BASE)
227#define INT_730_MCSI (16 + IH2_BASE)
228#define INT_730_uWireTX (17 + IH2_BASE)
229#define INT_730_uWireRX (18 + IH2_BASE)
230#define INT_730_SMC_CD (19 + IH2_BASE)
231#define INT_730_SMC_IREQ (20 + IH2_BASE)
232#define INT_730_HDQ_1WIRE (21 + IH2_BASE)
233#define INT_730_TIMER32K (22 + IH2_BASE)
234#define INT_730_MMC_SDIO (23 + IH2_BASE)
235#define INT_730_UPLD (24 + IH2_BASE)
236#define INT_730_USB_HHC_1 (27 + IH2_BASE)
237#define INT_730_USB_HHC_2 (28 + IH2_BASE)
238#define INT_730_USB_GENI (29 + IH2_BASE)
239#define INT_730_USB_OTG (30 + IH2_BASE)
240#define INT_730_CAMERA_IF (31 + IH2_BASE)
241#define INT_730_RNG (32 + IH2_BASE)
242#define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE)
243#define INT_730_DBB_RF_EN (34 + IH2_BASE)
244#define INT_730_MPUIO_KEYPAD (35 + IH2_BASE)
245#define INT_730_SHA1_MD5 (36 + IH2_BASE)
246#define INT_730_SPI_100K_2 (37 + IH2_BASE)
247#define INT_730_RNG_IDLE (38 + IH2_BASE)
248#define INT_730_MPUIO (39 + IH2_BASE)
249#define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
250#define INT_730_LLPC_OE_FALLING (41 + IH2_BASE)
251#define INT_730_LLPC_OE_RISING (42 + IH2_BASE)
252#define INT_730_LLPC_VSYNC (43 + IH2_BASE)
253#define INT_730_WAKE_UP_REQ (46 + IH2_BASE)
254#define INT_730_DMA_CH6 (53 + IH2_BASE)
255#define INT_730_DMA_CH7 (54 + IH2_BASE)
256#define INT_730_DMA_CH8 (55 + IH2_BASE)
257#define INT_730_DMA_CH9 (56 + IH2_BASE)
258#define INT_730_DMA_CH10 (57 + IH2_BASE)
259#define INT_730_DMA_CH11 (58 + IH2_BASE)
260#define INT_730_DMA_CH12 (59 + IH2_BASE)
261#define INT_730_DMA_CH13 (60 + IH2_BASE)
262#define INT_730_DMA_CH14 (61 + IH2_BASE)
263#define INT_730_DMA_CH15 (62 + IH2_BASE)
264#define INT_730_NAND (63 + IH2_BASE)
265
266/*
267 * OMAP-850 specific IRQ numbers for interrupt handler 2
268 */ 187 */
269#define INT_850_HW_ERRORS (0 + IH2_BASE) 188#define INT_7XX_HW_ERRORS (0 + IH2_BASE)
270#define INT_850_NFIQ_PWR_FAIL (1 + IH2_BASE) 189#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE)
271#define INT_850_CFCD (2 + IH2_BASE) 190#define INT_7XX_CFCD (2 + IH2_BASE)
272#define INT_850_CFIREQ (3 + IH2_BASE) 191#define INT_7XX_CFIREQ (3 + IH2_BASE)
273#define INT_850_I2C (4 + IH2_BASE) 192#define INT_7XX_I2C (4 + IH2_BASE)
274#define INT_850_PCC (5 + IH2_BASE) 193#define INT_7XX_PCC (5 + IH2_BASE)
275#define INT_850_MPU_EXT_NIRQ (6 + IH2_BASE) 194#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE)
276#define INT_850_SPI_100K_1 (7 + IH2_BASE) 195#define INT_7XX_SPI_100K_1 (7 + IH2_BASE)
277#define INT_850_SYREN_SPI (8 + IH2_BASE) 196#define INT_7XX_SYREN_SPI (8 + IH2_BASE)
278#define INT_850_VLYNQ (9 + IH2_BASE) 197#define INT_7XX_VLYNQ (9 + IH2_BASE)
279#define INT_850_GPIO_BANK4 (10 + IH2_BASE) 198#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE)
280#define INT_850_McBSP1TX (11 + IH2_BASE) 199#define INT_7XX_McBSP1TX (11 + IH2_BASE)
281#define INT_850_McBSP1RX (12 + IH2_BASE) 200#define INT_7XX_McBSP1RX (12 + IH2_BASE)
282#define INT_850_McBSP1RX_OF (13 + IH2_BASE) 201#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
283#define INT_850_UART_MODEM_IRDA_2 (14 + IH2_BASE) 202#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
284#define INT_850_UART_MODEM_1 (15 + IH2_BASE) 203#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE)
285#define INT_850_MCSI (16 + IH2_BASE) 204#define INT_7XX_MCSI (16 + IH2_BASE)
286#define INT_850_uWireTX (17 + IH2_BASE) 205#define INT_7XX_uWireTX (17 + IH2_BASE)
287#define INT_850_uWireRX (18 + IH2_BASE) 206#define INT_7XX_uWireRX (18 + IH2_BASE)
288#define INT_850_SMC_CD (19 + IH2_BASE) 207#define INT_7XX_SMC_CD (19 + IH2_BASE)
289#define INT_850_SMC_IREQ (20 + IH2_BASE) 208#define INT_7XX_SMC_IREQ (20 + IH2_BASE)
290#define INT_850_HDQ_1WIRE (21 + IH2_BASE) 209#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE)
291#define INT_850_TIMER32K (22 + IH2_BASE) 210#define INT_7XX_TIMER32K (22 + IH2_BASE)
292#define INT_850_MMC_SDIO (23 + IH2_BASE) 211#define INT_7XX_MMC_SDIO (23 + IH2_BASE)
293#define INT_850_UPLD (24 + IH2_BASE) 212#define INT_7XX_UPLD (24 + IH2_BASE)
294#define INT_850_USB_HHC_1 (27 + IH2_BASE) 213#define INT_7XX_USB_HHC_1 (27 + IH2_BASE)
295#define INT_850_USB_HHC_2 (28 + IH2_BASE) 214#define INT_7XX_USB_HHC_2 (28 + IH2_BASE)
296#define INT_850_USB_GENI (29 + IH2_BASE) 215#define INT_7XX_USB_GENI (29 + IH2_BASE)
297#define INT_850_USB_OTG (30 + IH2_BASE) 216#define INT_7XX_USB_OTG (30 + IH2_BASE)
298#define INT_850_CAMERA_IF (31 + IH2_BASE) 217#define INT_7XX_CAMERA_IF (31 + IH2_BASE)
299#define INT_850_RNG (32 + IH2_BASE) 218#define INT_7XX_RNG (32 + IH2_BASE)
300#define INT_850_DUAL_MODE_TIMER (33 + IH2_BASE) 219#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
301#define INT_850_DBB_RF_EN (34 + IH2_BASE) 220#define INT_7XX_DBB_RF_EN (34 + IH2_BASE)
302#define INT_850_MPUIO_KEYPAD (35 + IH2_BASE) 221#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE)
303#define INT_850_SHA1_MD5 (36 + IH2_BASE) 222#define INT_7XX_SHA1_MD5 (36 + IH2_BASE)
304#define INT_850_SPI_100K_2 (37 + IH2_BASE) 223#define INT_7XX_SPI_100K_2 (37 + IH2_BASE)
305#define INT_850_RNG_IDLE (38 + IH2_BASE) 224#define INT_7XX_RNG_IDLE (38 + IH2_BASE)
306#define INT_850_MPUIO (39 + IH2_BASE) 225#define INT_7XX_MPUIO (39 + IH2_BASE)
307#define INT_850_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) 226#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
308#define INT_850_LLPC_OE_FALLING (41 + IH2_BASE) 227#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
309#define INT_850_LLPC_OE_RISING (42 + IH2_BASE) 228#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
310#define INT_850_LLPC_VSYNC (43 + IH2_BASE) 229#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE)
311#define INT_850_WAKE_UP_REQ (46 + IH2_BASE) 230#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
312#define INT_850_DMA_CH6 (53 + IH2_BASE) 231#define INT_7XX_DMA_CH6 (53 + IH2_BASE)
313#define INT_850_DMA_CH7 (54 + IH2_BASE) 232#define INT_7XX_DMA_CH7 (54 + IH2_BASE)
314#define INT_850_DMA_CH8 (55 + IH2_BASE) 233#define INT_7XX_DMA_CH8 (55 + IH2_BASE)
315#define INT_850_DMA_CH9 (56 + IH2_BASE) 234#define INT_7XX_DMA_CH9 (56 + IH2_BASE)
316#define INT_850_DMA_CH10 (57 + IH2_BASE) 235#define INT_7XX_DMA_CH10 (57 + IH2_BASE)
317#define INT_850_DMA_CH11 (58 + IH2_BASE) 236#define INT_7XX_DMA_CH11 (58 + IH2_BASE)
318#define INT_850_DMA_CH12 (59 + IH2_BASE) 237#define INT_7XX_DMA_CH12 (59 + IH2_BASE)
319#define INT_850_DMA_CH13 (60 + IH2_BASE) 238#define INT_7XX_DMA_CH13 (60 + IH2_BASE)
320#define INT_850_DMA_CH14 (61 + IH2_BASE) 239#define INT_7XX_DMA_CH14 (61 + IH2_BASE)
321#define INT_850_DMA_CH15 (62 + IH2_BASE) 240#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
322#define INT_850_NAND (63 + IH2_BASE) 241#define INT_7XX_NAND (63 + IH2_BASE)
323 242
324#define INT_24XX_SYS_NIRQ 7 243#define INT_24XX_SYS_NIRQ 7
325#define INT_24XX_SDMA_IRQ0 12 244#define INT_24XX_SDMA_IRQ0 12
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h
index e0d6eca222cc..7e9cae3e3d15 100644
--- a/arch/arm/plat-omap/include/mach/mcbsp.h
+++ b/arch/arm/plat-omap/include/mach/mcbsp.h
@@ -30,8 +30,8 @@
30#include <mach/hardware.h> 30#include <mach/hardware.h>
31#include <mach/clock.h> 31#include <mach/clock.h>
32 32
33#define OMAP730_MCBSP1_BASE 0xfffb1000 33#define OMAP7XX_MCBSP1_BASE 0xfffb1000
34#define OMAP730_MCBSP2_BASE 0xfffb1800 34#define OMAP7XX_MCBSP2_BASE 0xfffb1800
35 35
36#define OMAP1510_MCBSP1_BASE 0xe1011800 36#define OMAP1510_MCBSP1_BASE 0xe1011800
37#define OMAP1510_MCBSP2_BASE 0xfffb1000 37#define OMAP1510_MCBSP2_BASE 0xfffb1000
@@ -58,7 +58,7 @@
58#define OMAP44XX_MCBSP3_BASE 0x49026000 58#define OMAP44XX_MCBSP3_BASE 0x49026000
59#define OMAP44XX_MCBSP4_BASE 0x48074000 59#define OMAP44XX_MCBSP4_BASE 0x48074000
60 60
61#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) 61#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
62 62
63#define OMAP_MCBSP_REG_DRR2 0x00 63#define OMAP_MCBSP_REG_DRR2 0x00
64#define OMAP_MCBSP_REG_DRR1 0x02 64#define OMAP_MCBSP_REG_DRR1 0x02
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h
index 0f49d2d563d9..f3c1d8a90456 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -51,23 +51,13 @@
51 .pu_pd_reg = PU_PD_SEL_##reg, \ 51 .pu_pd_reg = PU_PD_SEL_##reg, \
52 .pu_pd_val = status, 52 .pu_pd_val = status,
53 53
54#define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \ 54#define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
55 .mux_reg = OMAP730_IO_CONF_##reg, \ 55 .mux_reg = OMAP7XX_IO_CONF_##reg, \
56 .mask_offset = mode_offset, \ 56 .mask_offset = mode_offset, \
57 .mask = mode, 57 .mask = mode,
58 58
59#define PULL_REG_730(reg, bit, status) .pull_name = "OMAP730_IO_CONF_"#reg, \ 59#define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \
60 .pull_reg = OMAP730_IO_CONF_##reg, \ 60 .pull_reg = OMAP7XX_IO_CONF_##reg, \
61 .pull_bit = bit, \
62 .pull_val = status,
63
64#define MUX_REG_850(reg, mode_offset, mode) .mux_reg_name = "OMAP850_IO_CONF_"#reg, \
65 .mux_reg = OMAP850_IO_CONF_##reg, \
66 .mask_offset = mode_offset, \
67 .mask = mode,
68
69#define PULL_REG_850(reg, bit, status) .pull_name = "OMAP850_IO_CONF_"#reg, \
70 .pull_reg = OMAP850_IO_CONF_##reg, \
71 .pull_bit = bit, \ 61 .pull_bit = bit, \
72 .pull_val = status, 62 .pull_val = status,
73 63
@@ -84,21 +74,12 @@
84#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \ 74#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
85 .pu_pd_val = status, 75 .pu_pd_val = status,
86 76
87#define MUX_REG_730(reg, mode_offset, mode) \ 77#define MUX_REG_7XX(reg, mode_offset, mode) \
88 .mux_reg = OMAP730_IO_CONF_##reg, \ 78 .mux_reg = OMAP7XX_IO_CONF_##reg, \
89 .mask_offset = mode_offset, \ 79 .mask_offset = mode_offset, \
90 .mask = mode, 80 .mask = mode,
91 81
92#define PULL_REG_730(reg, bit, status) .pull_reg = OMAP730_IO_CONF_##reg, \ 82#define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \
93 .pull_bit = bit, \
94 .pull_val = status,
95
96#define MUX_REG_850(reg, mode_offset, mode) \
97 .mux_reg = OMAP850_IO_CONF_##reg, \
98 .mask_offset = mode_offset, \
99 .mask = mode,
100
101#define PULL_REG_850(reg, bit, status) .pull_reg = OMAP850_IO_CONF_##reg, \
102 .pull_bit = bit, \ 83 .pull_bit = bit, \
103 .pull_val = status, 84 .pull_val = status,
104 85
@@ -118,32 +99,21 @@
118 99
119/* 100/*
120 * OMAP730/850 has a slightly different config for the pin mux. 101 * OMAP730/850 has a slightly different config for the pin mux.
121 * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and 102 * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
122 * not the FUNC_MUX_CTRL_x regs from hardware.h 103 * not the FUNC_MUX_CTRL_x regs from hardware.h
123 * - for pull-up/down, only has one enable bit which is is in the same register 104 * - for pull-up/down, only has one enable bit which is is in the same register
124 * as mux config 105 * as mux config
125 */ 106 */
126#define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \ 107#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \
127 pull_bit, pull_status, debug_status)\ 108 pull_bit, pull_status, debug_status)\
128{ \ 109{ \
129 .name = desc, \ 110 .name = desc, \
130 .debug = debug_status, \ 111 .debug = debug_status, \
131 MUX_REG_730(mux_reg, mode_offset, mode) \ 112 MUX_REG_7XX(mux_reg, mode_offset, mode) \
132 PULL_REG_730(mux_reg, pull_bit, pull_status) \ 113 PULL_REG_7XX(mux_reg, pull_bit, pull_status) \
133 PU_PD_REG(NA, 0) \ 114 PU_PD_REG(NA, 0) \
134}, 115},
135 116
136#define MUX_CFG_850(desc, mux_reg, mode_offset, mode, \
137 pull_bit, pull_status, debug_status)\
138{ \
139 .name = desc, \
140 .debug = debug_status, \
141 MUX_REG_850(mux_reg, mode_offset, mode) \
142 PULL_REG_850(mux_reg, pull_bit, pull_status) \
143 PU_PD_REG(NA, 0) \
144},
145
146
147#define MUX_CFG_24XX(desc, reg_offset, mode, \ 117#define MUX_CFG_24XX(desc, reg_offset, mode, \
148 pull_en, pull_mode, dbg) \ 118 pull_en, pull_mode, dbg) \
149{ \ 119{ \
@@ -232,45 +202,25 @@ struct pin_config {
232 202
233}; 203};
234 204
235enum omap730_index { 205enum omap7xx_index {
236 /* OMAP 730 keyboard */ 206 /* OMAP 730 keyboard */
237 E2_730_KBR0, 207 E2_7XX_KBR0,
238 J7_730_KBR1, 208 J7_7XX_KBR1,
239 E1_730_KBR2, 209 E1_7XX_KBR2,
240 F3_730_KBR3, 210 F3_7XX_KBR3,
241 D2_730_KBR4, 211 D2_7XX_KBR4,
242 C2_730_KBC0, 212 C2_7XX_KBC0,
243 D3_730_KBC1, 213 D3_7XX_KBC1,
244 E4_730_KBC2, 214 E4_7XX_KBC2,
245 F4_730_KBC3, 215 F4_7XX_KBC3,
246 E3_730_KBC4, 216 E3_7XX_KBC4,
247
248 /* USB */
249 AA17_730_USB_DM,
250 W16_730_USB_PU_EN,
251 W17_730_USB_VBUSI,
252};
253
254enum omap850_index {
255 /* OMAP 850 keyboard */
256 E2_850_KBR0,
257 J7_850_KBR1,
258 E1_850_KBR2,
259 F3_850_KBR3,
260 D2_850_KBR4,
261 C2_850_KBC0,
262 D3_850_KBC1,
263 E4_850_KBC2,
264 F4_850_KBC3,
265 E3_850_KBC4,
266 217
267 /* USB */ 218 /* USB */
268 AA17_850_USB_DM, 219 AA17_7XX_USB_DM,
269 W16_850_USB_PU_EN, 220 W16_7XX_USB_PU_EN,
270 W17_850_USB_VBUSI, 221 W17_7XX_USB_VBUSI,
271}; 222};
272 223
273
274enum omap1xxx_index { 224enum omap1xxx_index {
275 /* UART1 (BT_UART_GATING)*/ 225 /* UART1 (BT_UART_GATING)*/
276 UART1_TX = 0, 226 UART1_TX = 0,
diff --git a/arch/arm/plat-omap/include/mach/omap7xx.h b/arch/arm/plat-omap/include/mach/omap7xx.h
new file mode 100644
index 000000000000..53f52414b0e9
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/omap7xx.h
@@ -0,0 +1,104 @@
1/* arch/arm/plat-omap/include/mach/omap7xx.h
2 *
3 * Hardware definitions for TI OMAP7XX processor.
4 *
5 * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
6 * Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net>
7 * Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#ifndef __ASM_ARCH_OMAP7XX_H
31#define __ASM_ARCH_OMAP7XX_H
32
33/*
34 * ----------------------------------------------------------------------------
35 * Base addresses
36 * ----------------------------------------------------------------------------
37 */
38
39/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
40
41#define OMAP7XX_DSP_BASE 0xE0000000
42#define OMAP7XX_DSP_SIZE 0x50000
43#define OMAP7XX_DSP_START 0xE0000000
44
45#define OMAP7XX_DSPREG_BASE 0xE1000000
46#define OMAP7XX_DSPREG_SIZE SZ_128K
47#define OMAP7XX_DSPREG_START 0xE1000000
48
49/*
50 * ----------------------------------------------------------------------------
51 * OMAP7XX specific configuration registers
52 * ----------------------------------------------------------------------------
53 */
54#define OMAP7XX_CONFIG_BASE 0xfffe1000
55#define OMAP7XX_IO_CONF_0 0xfffe1070
56#define OMAP7XX_IO_CONF_1 0xfffe1074
57#define OMAP7XX_IO_CONF_2 0xfffe1078
58#define OMAP7XX_IO_CONF_3 0xfffe107c
59#define OMAP7XX_IO_CONF_4 0xfffe1080
60#define OMAP7XX_IO_CONF_5 0xfffe1084
61#define OMAP7XX_IO_CONF_6 0xfffe1088
62#define OMAP7XX_IO_CONF_7 0xfffe108c
63#define OMAP7XX_IO_CONF_8 0xfffe1090
64#define OMAP7XX_IO_CONF_9 0xfffe1094
65#define OMAP7XX_IO_CONF_10 0xfffe1098
66#define OMAP7XX_IO_CONF_11 0xfffe109c
67#define OMAP7XX_IO_CONF_12 0xfffe10a0
68#define OMAP7XX_IO_CONF_13 0xfffe10a4
69
70#define OMAP7XX_MODE_1 0xfffe1010
71#define OMAP7XX_MODE_2 0xfffe1014
72
73/* CSMI specials: in terms of base + offset */
74#define OMAP7XX_MODE2_OFFSET 0x14
75
76/*
77 * ----------------------------------------------------------------------------
78 * OMAP7XX traffic controller configuration registers
79 * ----------------------------------------------------------------------------
80 */
81#define OMAP7XX_FLASH_CFG_0 0xfffecc10
82#define OMAP7XX_FLASH_ACFG_0 0xfffecc50
83#define OMAP7XX_FLASH_CFG_1 0xfffecc14
84#define OMAP7XX_FLASH_ACFG_1 0xfffecc54
85
86/*
87 * ----------------------------------------------------------------------------
88 * OMAP7XX DSP control registers
89 * ----------------------------------------------------------------------------
90 */
91#define OMAP7XX_ICR_BASE 0xfffbb800
92#define OMAP7XX_DSP_M_CTL 0xfffbb804
93#define OMAP7XX_DSP_MMU_BASE 0xfffed200
94
95/*
96 * ----------------------------------------------------------------------------
97 * OMAP7XX PCC_UPLD configuration registers
98 * ----------------------------------------------------------------------------
99 */
100#define OMAP7XX_PCC_UPLD_CTRL_BASE (0xfffe0900)
101#define OMAP7XX_PCC_UPLD_CTRL (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00)
102
103#endif /* __ASM_ARCH_OMAP7XX_H */
104
diff --git a/arch/arm/plat-omap/include/mach/uncompress.h b/arch/arm/plat-omap/include/mach/uncompress.h
index 0814c5f210c3..ddf7b88dec4d 100644
--- a/arch/arm/plat-omap/include/mach/uncompress.h
+++ b/arch/arm/plat-omap/include/mach/uncompress.h
@@ -25,6 +25,7 @@ unsigned int system_rev;
25 25
26#define UART_OMAP_MDR1 0x08 /* mode definition register */ 26#define UART_OMAP_MDR1 0x08 /* mode definition register */
27#define OMAP_ID_730 0x355F 27#define OMAP_ID_730 0x355F
28#define OMAP_ID_850 0x362C
28#define ID_MASK 0x7fff 29#define ID_MASK 0x7fff
29#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0) 30#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
30#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK 31#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
@@ -53,7 +54,7 @@ static void putc(int c)
53 /* MMU is not on, so cpu_is_omapXXXX() won't work here */ 54 /* MMU is not on, so cpu_is_omapXXXX() won't work here */
54 unsigned int omap_id = omap_get_id(); 55 unsigned int omap_id = omap_get_id();
55 56
56 if (omap_id == OMAP_ID_730) 57 if (omap_id == OMAP_ID_730 || omap_id == OMAP_ID_850)
57 shift = 0; 58 shift = 0;
58 59
59 if (check_port(uart, shift)) 60 if (check_port(uart, shift))
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index b6defa23e77e..23a205f4a2b1 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -13,7 +13,7 @@
13#include <linux/io.h> 13#include <linux/io.h>
14#include <linux/mm.h> 14#include <linux/mm.h>
15 15
16#include <mach/omap730.h> 16#include <mach/omap7xx.h>
17#include <mach/omap1510.h> 17#include <mach/omap1510.h>
18#include <mach/omap16xx.h> 18#include <mach/omap16xx.h>
19#include <mach/omap24xx.h> 19#include <mach/omap24xx.h>
@@ -33,13 +33,13 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
33 if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE)) 33 if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE))
34 return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT); 34 return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT);
35 } 35 }
36 if (cpu_is_omap730()) { 36 if (cpu_is_omap7xx()) {
37 if (BETWEEN(p, OMAP730_DSP_BASE, OMAP730_DSP_SIZE)) 37 if (BETWEEN(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_SIZE))
38 return XLATE(p, OMAP730_DSP_BASE, OMAP730_DSP_START); 38 return XLATE(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_START);
39 39
40 if (BETWEEN(p, OMAP730_DSPREG_BASE, OMAP730_DSPREG_SIZE)) 40 if (BETWEEN(p, OMAP7XX_DSPREG_BASE, OMAP7XX_DSPREG_SIZE))
41 return XLATE(p, OMAP730_DSPREG_BASE, 41 return XLATE(p, OMAP7XX_DSPREG_BASE,
42 OMAP730_DSPREG_START); 42 OMAP7XX_DSPREG_START);
43 } 43 }
44 if (cpu_is_omap15xx()) { 44 if (cpu_is_omap15xx()) {
45 if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE)) 45 if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE))
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index 509f2ed99e21..3c40b8525df6 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -614,8 +614,8 @@ omap_otg_init(struct omap_usb_config *config)
614 if (config->otg || config->register_host) { 614 if (config->otg || config->register_host) {
615 syscon &= ~HST_IDLE_EN; 615 syscon &= ~HST_IDLE_EN;
616 ohci_device.dev.platform_data = config; 616 ohci_device.dev.platform_data = config;
617 if (cpu_is_omap730()) 617 if (cpu_is_omap7xx())
618 ohci_resources[1].start = INT_730_USB_HHC_1; 618 ohci_resources[1].start = INT_7XX_USB_HHC_1;
619 status = platform_device_register(&ohci_device); 619 status = platform_device_register(&ohci_device);
620 if (status) 620 if (status)
621 pr_debug("can't register OHCI device, %d\n", status); 621 pr_debug("can't register OHCI device, %d\n", status);
@@ -626,8 +626,8 @@ omap_otg_init(struct omap_usb_config *config)
626 if (config->otg) { 626 if (config->otg) {
627 syscon &= ~OTG_IDLE_EN; 627 syscon &= ~OTG_IDLE_EN;
628 otg_device.dev.platform_data = config; 628 otg_device.dev.platform_data = config;
629 if (cpu_is_omap730()) 629 if (cpu_is_omap7xx())
630 otg_resources[1].start = INT_730_USB_OTG; 630 otg_resources[1].start = INT_7XX_USB_OTG;
631 status = platform_device_register(&otg_device); 631 status = platform_device_register(&otg_device);
632 if (status) 632 if (status)
633 pr_debug("can't register OTG device, %d\n", status); 633 pr_debug("can't register OTG device, %d\n", status);
@@ -731,7 +731,7 @@ static inline void omap_1510_usb_init(struct omap_usb_config *config) {}
731 731
732void __init omap_usb_init(struct omap_usb_config *pdata) 732void __init omap_usb_init(struct omap_usb_config *pdata)
733{ 733{
734 if (cpu_is_omap730() || cpu_is_omap16xx() || cpu_is_omap24xx()) 734 if (cpu_is_omap7xx() || cpu_is_omap16xx() || cpu_is_omap24xx())
735 omap_otg_init(pdata); 735 omap_otg_init(pdata);
736 else if (cpu_is_omap15xx()) 736 else if (cpu_is_omap15xx())
737 omap_1510_usb_init(pdata); 737 omap_1510_usb_init(pdata);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 17:57:21 -0500