Merge commit '4cb38750d49010ae72e718d46605ac9ba5a851b4' into stable/for-linus-3.6

* commit '4cb38750d49010ae72e718d46605ac9ba5a851b4': (6849 commits)
  bcma: fix invalid PMU chip control masks
  [libata] pata_cmd64x: whitespace cleanup
  libata-acpi: fix up for acpi_pm_device_sleep_state API
  sata_dwc_460ex: device tree may specify dma_channel
  ahci, trivial: fixed coding style issues related to braces
  ahci_platform: add hibernation callbacks
  libata-eh.c: local functions should not be exposed globally
  libata-transport.c: local functions should not be exposed globally
  sata_dwc_460ex: support hardreset
  ata: use module_pci_driver
  drivers/ata/pata_pcmcia.c: adjust suspicious bit operation
  pata_imx: Convert to clk_prepare_enable/clk_disable_unprepare
  ahci: Enable SB600 64bit DMA on MSI K9AGM2 (MS-7327) v2
  [libata] Prevent interface errors with Seagate FreeAgent GoFlex
  drivers/acpi/glue: revert accidental license-related 6b66d95895c bits
  libata-acpi: add missing inlines in libata.h
  i2c-omap: Add support for I2C_M_STOP message flag
  i2c: Fall back to emulated SMBus if the operation isn't supported natively
  i2c: Add SCCB support
  i2c-tiny-usb: Add support for the Robofuzz OSIF USB/I2C converter
  ...

30 files changed, 350 insertions, 797 deletions

diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index ad95c7a5d009..dd36eba9506c 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -29,7 +29,7 @@ config ARCH_OMAP2PLUS
         select USE_OF
         select PROC_DEVICETREE if PROC_FS
         help
-          "Systems based on OMAP2, OMAP3 or OMAP4"
+          "Systems based on OMAP2, OMAP3, OMAP4 or OMAP5"
 
 endchoice
 
@@ -45,31 +45,30 @@ config OMAP_DEBUG_LEDS
         depends on OMAP_DEBUG_DEVICES
         default y if LEDS_CLASS
 
-config OMAP_SMARTREFLEX
-        bool "SmartReflex support"
-        depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM
+config POWER_AVS_OMAP
+        bool "AVS(Adaptive Voltage Scaling) support for OMAP IP versions 1&2"
+        depends on POWER_AVS && (ARCH_OMAP3 || ARCH_OMAP4) && PM
         help
-          Say Y if you want to enable SmartReflex.
-
-          SmartReflex can perform continuous dynamic voltage
-          scaling around the nominal operating point voltage
-          according to silicon characteristics and operating
-          conditions. Enabling SmartReflex reduces power
-          consumption.
+          Say Y to enable AVS(Adaptive Voltage Scaling)
+          support on OMAP containing the version 1 or
+          version 2 of the SmartReflex IP.
+          V1 is the 65nm version used in OMAP3430.
+          V2 is the update for the 45nm version of the IP used in OMAP3630
+          and OMAP4430
 
           Please note, that by default SmartReflex is only
-          initialized. To enable the automatic voltage
-          compensation for vdd mpu  and vdd core from user space,
+          initialized and not enabled. To enable the automatic voltage
+          compensation for vdd mpu and vdd core from user space,
           user must write 1 to
-                /debug/voltage/vdd_<X>/smartreflex/autocomp,
-          where X is mpu or core for OMAP3.
+                /debug/smartreflex/sr_<X>/autocomp,
+          where X is mpu_iva or core for OMAP3.
           Optionally autocompensation can be enabled in the kernel
           by default during system init via the enable_on_init flag
           which an be passed as platform data to the smartreflex driver.
 
-config OMAP_SMARTREFLEX_CLASS3
+config POWER_AVS_OMAP_CLASS3
         bool "Class 3 mode of Smartreflex Implementation"
-        depends on OMAP_SMARTREFLEX && TWL4030_CORE
+        depends on POWER_AVS_OMAP && TWL4030_CORE
         help
           Say Y to enable Class 3 implementation of Smartreflex
 
@@ -150,7 +149,7 @@ config OMAP_32K_TIMER
           This timer saves power compared to the OMAP_MPU_TIMER, and has
           support for no tick during idle. The 32KHz timer provides less
           intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
-          currently only available for OMAP16XX, 24XX, 34XX and OMAP4.
+          currently only available for OMAP16XX, 24XX, 34XX and OMAP4/5.
 
 config OMAP3_L2_AUX_SECURE_SAVE_RESTORE
         bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index ed8605f01155..961bf859bc0c 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -4,15 +4,13 @@
 
 # Common support
 obj-y := common.o sram.o clock.o devices.o dma.o mux.o \
-         usb.o fb.o counter_32k.o
+         fb.o counter_32k.o
 obj-m :=
 obj-n :=
 obj-  :=
 
 # omap_device support (OMAP2+ only at the moment)
-obj-$(CONFIG_ARCH_OMAP2) += omap_device.o
-obj-$(CONFIG_ARCH_OMAP3) += omap_device.o
-obj-$(CONFIG_ARCH_OMAP4) += omap_device.o
+obj-$(CONFIG_ARCH_OMAP2PLUS) += omap_device.o
 
 obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
 obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 62ec5c452792..706b7e29397f 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -461,6 +461,7 @@ static int clk_dbg_show_summary(struct seq_file *s, void *unused)
         struct clk *c;
         struct clk *pa;
 
+        mutex_lock(&clocks_mutex);
         seq_printf(s, "%-30s %-30s %-10s %s\n",
                 "clock-name", "parent-name", "rate", "use-count");
 
@@ -469,6 +470,7 @@ static int clk_dbg_show_summary(struct seq_file *s, void *unused)
                 seq_printf(s, "%-30s %-30s %-10lu %d\n",
                         c->name, pa ? pa->name : "none", c->rate, c->usecount);
         }
+        mutex_unlock(&clocks_mutex);
 
         return 0;
 }
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 0a9b9a970113..89a3723b3538 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -77,3 +77,12 @@ void __init omap_init_consistent_dma_size(void)
         init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20);
 #endif
 }
+
+/*
+ * Stub function for OMAP2 so that common files
+ * continue to build when custom builds are used
+ */
+int __weak omap_secure_ram_reserve_memblock(void)
+{
+        return 0;
+}
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 2132c4f389e1..dbf1e03029a5 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -29,7 +29,10 @@
 #include <plat/clock.h>
 
 /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
-#define OMAP2_32KSYNCNT_CR_OFF          0x10
+#define OMAP2_32KSYNCNT_REV_OFF         0x0
+#define OMAP2_32KSYNCNT_REV_SCHEME      (0x3 << 30)
+#define OMAP2_32KSYNCNT_CR_OFF_LOW      0x10
+#define OMAP2_32KSYNCNT_CR_OFF_HIGH     0x30
 
 /*
  * 32KHz clocksource ... always available, on pretty most chips except
@@ -84,9 +87,16 @@ int __init omap_init_clocksource_32k(void __iomem *vbase)
         int ret;
 
         /*
-         * 32k sync Counter register offset is at 0x10
+         * 32k sync Counter IP register offsets vary between the
+         * highlander version and the legacy ones.
+         * The 'SCHEME' bits(30-31) of the revision register is used
+         * to identify the version.
          */
-        sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF;
+        if (__raw_readl(vbase + OMAP2_32KSYNCNT_REV_OFF) &
+                                                OMAP2_32KSYNCNT_REV_SCHEME)
+                sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;
+        else
+                sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW;
 
         /*
          * 120000 rough estimate from the calculations in
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index cb16ade437cb..7fe626761e53 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -573,22 +573,25 @@ EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 
 static inline void omap_enable_channel_irq(int lch)
 {
-        u32 status;
-
         /* Clear CSR */
         if (cpu_class_is_omap1())
-                status = p->dma_read(CSR, lch);
-        else if (cpu_class_is_omap2())
+                p->dma_read(CSR, lch);
+        else
                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 
         /* Enable some nice interrupts. */
         p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
 }
 
-static void omap_disable_channel_irq(int lch)
+static inline void omap_disable_channel_irq(int lch)
 {
-        if (cpu_class_is_omap2())
-                p->dma_write(0, CICR, lch);
+        /* disable channel interrupts */
+        p->dma_write(0, CICR, lch);
+        /* Clear CSR */
+        if (cpu_class_is_omap1())
+                p->dma_read(CSR, lch);
+        else
+                p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 }
 
 void omap_enable_dma_irq(int lch, u16 bits)
@@ -632,14 +635,14 @@ static inline void disable_lnk(int lch)
         l = p->dma_read(CLNK_CTRL, lch);
 
         /* Disable interrupts */
+        omap_disable_channel_irq(lch);
+
         if (cpu_class_is_omap1()) {
-                p->dma_write(0, CICR, lch);
                 /* Set the STOP_LNK bit */
                 l |= 1 << 14;
         }
 
         if (cpu_class_is_omap2()) {
-                omap_disable_channel_irq(lch);
                 /* Clear the ENABLE_LNK bit */
                 l &= ~(1 << 15);
         }
@@ -657,6 +660,9 @@ static inline void omap2_enable_irq_lch(int lch)
                 return;
 
         spin_lock_irqsave(&dma_chan_lock, flags);
+        /* clear IRQ STATUS */
+        p->dma_write(1 << lch, IRQSTATUS_L0, lch);
+        /* Enable interrupt */
         val = p->dma_read(IRQENABLE_L0, lch);
         val |= 1 << lch;
         p->dma_write(val, IRQENABLE_L0, lch);
@@ -672,9 +678,12 @@ static inline void omap2_disable_irq_lch(int lch)
                 return;
 
         spin_lock_irqsave(&dma_chan_lock, flags);
+        /* Disable interrupt */
         val = p->dma_read(IRQENABLE_L0, lch);
         val &= ~(1 << lch);
         p->dma_write(val, IRQENABLE_L0, lch);
+        /* clear IRQ STATUS */
+        p->dma_write(1 << lch, IRQSTATUS_L0, lch);
         spin_unlock_irqrestore(&dma_chan_lock, flags);
 }
 
@@ -745,11 +754,8 @@ int omap_request_dma(int dev_id, const char *dev_name,
         }
 
         if (cpu_class_is_omap2()) {
-                omap2_enable_irq_lch(free_ch);
                 omap_enable_channel_irq(free_ch);
-                /* Clear the CSR register and IRQ status register */
-                p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch);
-                p->dma_write(1 << free_ch, IRQSTATUS_L0, 0);
+                omap2_enable_irq_lch(free_ch);
         }
 
         *dma_ch_out = free_ch;
@@ -768,27 +774,19 @@ void omap_free_dma(int lch)
                 return;
         }
 
-        if (cpu_class_is_omap1()) {
-                /* Disable all DMA interrupts for the channel. */
-                p->dma_write(0, CICR, lch);
-                /* Make sure the DMA transfer is stopped. */
-                p->dma_write(0, CCR, lch);
-        }
-
-        if (cpu_class_is_omap2()) {
+        /* Disable interrupt for logical channel */
+        if (cpu_class_is_omap2())
                 omap2_disable_irq_lch(lch);
 
-                /* Clear the CSR register and IRQ status register */
-                p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
-                p->dma_write(1 << lch, IRQSTATUS_L0, lch);
+        /* Disable all DMA interrupts for the channel. */
+        omap_disable_channel_irq(lch);
 
-                /* Disable all DMA interrupts for the channel. */
-                p->dma_write(0, CICR, lch);
+        /* Make sure the DMA transfer is stopped. */
+        p->dma_write(0, CCR, lch);
 
-                /* Make sure the DMA transfer is stopped. */
-                p->dma_write(0, CCR, lch);
+        /* Clear registers */
+        if (cpu_class_is_omap2())
                 omap_clear_dma(lch);
-        }
 
         spin_lock_irqsave(&dma_chan_lock, flags);
         dma_chan[lch].dev_id = -1;
@@ -943,8 +941,7 @@ void omap_stop_dma(int lch)
         u32 l;
 
         /* Disable all interrupts on the channel */
-        if (cpu_class_is_omap1())
-                p->dma_write(0, CICR, lch);
+        omap_disable_channel_irq(lch);
 
         l = p->dma_read(CCR, lch);
         if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 3b0cfeb33d05..626ad8cad7a9 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -37,14 +37,16 @@
 
 #include <linux/module.h>
 #include <linux/io.h>
-#include <linux/slab.h>
+#include <linux/device.h>
 #include <linux/err.h>
 #include <linux/pm_runtime.h>
 
 #include <plat/dmtimer.h>
+#include <plat/omap-pm.h>
 
 #include <mach/hardware.h>
 
+static u32 omap_reserved_systimers;
 static LIST_HEAD(omap_timer_list);
 static DEFINE_SPINLOCK(dm_timer_lock);
 
@@ -133,17 +135,22 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
 
 int omap_dm_timer_prepare(struct omap_dm_timer *timer)
 {
-        struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
         int ret;
 
-        timer->fclk = clk_get(&timer->pdev->dev, "fck");
-        if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) {
-                timer->fclk = NULL;
-                dev_err(&timer->pdev->dev, ": No fclk handle.\n");
-                return -EINVAL;
+        /*
+         * FIXME: OMAP1 devices do not use the clock framework for dmtimers so
+         * do not call clk_get() for these devices.
+         */
+        if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
+                timer->fclk = clk_get(&timer->pdev->dev, "fck");
+                if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) {
+                        timer->fclk = NULL;
+                        dev_err(&timer->pdev->dev, ": No fclk handle.\n");
+                        return -EINVAL;
+                }
         }
 
-        if (pdata->needs_manual_reset)
+        if (timer->capability & OMAP_TIMER_NEEDS_RESET)
                 omap_dm_timer_reset(timer);
 
         ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
@@ -152,6 +159,21 @@ int omap_dm_timer_prepare(struct omap_dm_timer *timer)
         return ret;
 }
 
+static inline u32 omap_dm_timer_reserved_systimer(int id)
+{
+        return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0;
+}
+
+int omap_dm_timer_reserve_systimer(int id)
+{
+        if (omap_dm_timer_reserved_systimer(id))
+                return -ENODEV;
+
+        omap_reserved_systimers |= (1 << (id - 1));
+
+        return 0;
+}
+
 struct omap_dm_timer *omap_dm_timer_request(void)
 {
         struct omap_dm_timer *timer = NULL, *t;
@@ -325,10 +347,9 @@ int omap_dm_timer_start(struct omap_dm_timer *timer)
 
         omap_dm_timer_enable(timer);
 
-        if (timer->loses_context) {
-                u32 ctx_loss_cnt_after =
-                        timer->get_context_loss_count(&timer->pdev->dev);
-                if (ctx_loss_cnt_after != timer->ctx_loss_count)
+        if (!(timer->capability & OMAP_TIMER_ALWON)) {
+                if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) !=
+                                timer->ctx_loss_count)
                         omap_timer_restore_context(timer);
         }
 
@@ -347,20 +368,18 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_start);
 int omap_dm_timer_stop(struct omap_dm_timer *timer)
 {
         unsigned long rate = 0;
-        struct dmtimer_platform_data *pdata;
 
         if (unlikely(!timer))
                 return -EINVAL;
 
-        pdata = timer->pdev->dev.platform_data;
-        if (!pdata->needs_manual_reset)
+        if (!(timer->capability & OMAP_TIMER_NEEDS_RESET))
                 rate = clk_get_rate(timer->fclk);
 
         __omap_dm_timer_stop(timer, timer->posted, rate);
 
-        if (timer->loses_context && timer->get_context_loss_count)
+        if (!(timer->capability & OMAP_TIMER_ALWON))
                 timer->ctx_loss_count =
-                        timer->get_context_loss_count(&timer->pdev->dev);
+                        omap_pm_get_dev_context_loss_count(&timer->pdev->dev);
 
         /*
          * Since the register values are computed and written within
@@ -378,6 +397,8 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 {
         int ret;
+        char *parent_name = NULL;
+        struct clk *fclk, *parent;
         struct dmtimer_platform_data *pdata;
 
         if (unlikely(!timer))
@@ -388,7 +409,49 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
         if (source < 0 || source >= 3)
                 return -EINVAL;
 
-        ret = pdata->set_timer_src(timer->pdev, source);
+        /*
+         * FIXME: Used for OMAP1 devices only because they do not currently
+         * use the clock framework to set the parent clock. To be removed
+         * once OMAP1 migrated to using clock framework for dmtimers
+         */
+        if (pdata->set_timer_src)
+                return pdata->set_timer_src(timer->pdev, source);
+
+        fclk = clk_get(&timer->pdev->dev, "fck");
+        if (IS_ERR_OR_NULL(fclk)) {
+                pr_err("%s: fck not found\n", __func__);
+                return -EINVAL;
+        }
+
+        switch (source) {
+        case OMAP_TIMER_SRC_SYS_CLK:
+                parent_name = "timer_sys_ck";
+                break;
+
+        case OMAP_TIMER_SRC_32_KHZ:
+                parent_name = "timer_32k_ck";
+                break;
+
+        case OMAP_TIMER_SRC_EXT_CLK:
+                parent_name = "timer_ext_ck";
+                break;
+        }
+
+        parent = clk_get(&timer->pdev->dev, parent_name);
+        if (IS_ERR_OR_NULL(parent)) {
+                pr_err("%s: %s not found\n", __func__, parent_name);
+                ret = -EINVAL;
+                goto out;
+        }
+
+        ret = clk_set_parent(fclk, parent);
+        if (IS_ERR_VALUE(ret))
+                pr_err("%s: failed to set %s as parent\n", __func__,
+                        parent_name);
+
+        clk_put(parent);
+out:
+        clk_put(fclk);
 
         return ret;
 }
@@ -431,10 +494,9 @@ int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
 
         omap_dm_timer_enable(timer);
 
-        if (timer->loses_context) {
-                u32 ctx_loss_cnt_after =
-                        timer->get_context_loss_count(&timer->pdev->dev);
-                if (ctx_loss_cnt_after != timer->ctx_loss_count)
+        if (!(timer->capability & OMAP_TIMER_ALWON)) {
+                if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) !=
+                                timer->ctx_loss_count)
                         omap_timer_restore_context(timer);
         }
 
@@ -627,68 +689,57 @@ EXPORT_SYMBOL_GPL(omap_dm_timers_active);
  */
 static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
 {
-        int ret;
         unsigned long flags;
         struct omap_dm_timer *timer;
-        struct resource *mem, *irq, *ioarea;
+        struct resource *mem, *irq;
+        struct device *dev = &pdev->dev;
         struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
 
         if (!pdata) {
-                dev_err(&pdev->dev, "%s: no platform data.\n", __func__);
+                dev_err(dev, "%s: no platform data.\n", __func__);
                 return -ENODEV;
         }
 
         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
         if (unlikely(!irq)) {
-                dev_err(&pdev->dev, "%s: no IRQ resource.\n", __func__);
+                dev_err(dev, "%s: no IRQ resource.\n", __func__);
                 return -ENODEV;
         }
 
         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         if (unlikely(!mem)) {
-                dev_err(&pdev->dev, "%s: no memory resource.\n", __func__);
+                dev_err(dev, "%s: no memory resource.\n", __func__);
                 return -ENODEV;
         }
 
-        ioarea = request_mem_region(mem->start, resource_size(mem),
-                        pdev->name);
-        if (!ioarea) {
-                dev_err(&pdev->dev, "%s: region already claimed.\n", __func__);
-                return -EBUSY;
-        }
-
-        timer = kzalloc(sizeof(struct omap_dm_timer), GFP_KERNEL);
+        timer = devm_kzalloc(dev, sizeof(struct omap_dm_timer), GFP_KERNEL);
         if (!timer) {
-                dev_err(&pdev->dev, "%s: no memory for omap_dm_timer.\n",
-                        __func__);
-                ret = -ENOMEM;
-                goto err_free_ioregion;
+                dev_err(dev, "%s: memory alloc failed!\n", __func__);
+                return  -ENOMEM;
         }
 
-        timer->io_base = ioremap(mem->start, resource_size(mem));
+        timer->io_base = devm_request_and_ioremap(dev, mem);
         if (!timer->io_base) {
-                dev_err(&pdev->dev, "%s: ioremap failed.\n", __func__);
-                ret = -ENOMEM;
-                goto err_free_mem;
+                dev_err(dev, "%s: region already claimed.\n", __func__);
+                return -ENOMEM;
         }
 
         timer->id = pdev->id;
         timer->irq = irq->start;
-        timer->reserved = pdata->reserved;
+        timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
         timer->pdev = pdev;
-        timer->loses_context = pdata->loses_context;
-        timer->get_context_loss_count = pdata->get_context_loss_count;
+        timer->capability = pdata->timer_capability;
 
         /* Skip pm_runtime_enable for OMAP1 */
-        if (!pdata->needs_manual_reset) {
-                pm_runtime_enable(&pdev->dev);
-                pm_runtime_irq_safe(&pdev->dev);
+        if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
+                pm_runtime_enable(dev);
+                pm_runtime_irq_safe(dev);
         }
 
         if (!timer->reserved) {
-                pm_runtime_get_sync(&pdev->dev);
+                pm_runtime_get_sync(dev);
                 __omap_dm_timer_init_regs(timer);
-                pm_runtime_put(&pdev->dev);
+                pm_runtime_put(dev);
         }
 
         /* add the timer element to the list */
@@ -696,17 +747,9 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
         list_add_tail(&timer->node, &omap_timer_list);
         spin_unlock_irqrestore(&dm_timer_lock, flags);
 
-        dev_dbg(&pdev->dev, "Device Probed.\n");
+        dev_dbg(dev, "Device Probed.\n");
 
         return 0;
-
-err_free_mem:
-        kfree(timer);
-
-err_free_ioregion:
-        release_mem_region(mem->start, resource_size(mem));
-
-        return ret;
 }
 
 /**
@@ -727,7 +770,6 @@ static int __devexit omap_dm_timer_remove(struct platform_device *pdev)
         list_for_each_entry(timer, &omap_timer_list, node)
                 if (timer->pdev->id == pdev->id) {
                         list_del(&timer->node);
-                        kfree(timer);
                         ret = 0;
                         break;
                 }
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index 4814c5b65306..e62f20a5c0af 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -57,44 +57,6 @@ struct omap_camera_sensor_config {
         int (*power_off)(void * data);
 };
 
-struct omap_usb_config {
-        /* Configure drivers according to the connectors on your board:
-         *  - "A" connector (rectagular)
-         *      ... for host/OHCI use, set "register_host".
-         *  - "B" connector (squarish) or "Mini-B"
-         *      ... for device/gadget use, set "register_dev".
-         *  - "Mini-AB" connector (very similar to Mini-B)
-         *      ... for OTG use as device OR host, initialize "otg"
-         */
-        unsigned        register_host:1;
-        unsigned        register_dev:1;
-        u8              otg;    /* port number, 1-based:  usb1 == 2 */
-
-        u8              hmc_mode;
-
-        /* implicitly true if otg:  host supports remote wakeup? */
-        u8              rwc;
-
-        /* signaling pins used to talk to transceiver on usbN:
-         *  0 == usbN unused
-         *  2 == usb0-only, using internal transceiver
-         *  3 == 3 wire bidirectional
-         *  4 == 4 wire bidirectional
-         *  6 == 6 wire unidirectional (or TLL)
-         */
-        u8              pins[3];
-
-        struct platform_device *udc_device;
-        struct platform_device *ohci_device;
-        struct platform_device *otg_device;
-
-        u32 (*usb0_init)(unsigned nwires, unsigned is_device);
-        u32 (*usb1_init)(unsigned nwires);
-        u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup);
-
-        int (*ocpi_enable)(void);
-};
-
 struct omap_lcd_config {
         char panel_name[16];
         char ctrl_name[16];
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index d0ed8c443a63..025d85a3ee86 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -39,6 +39,7 @@ struct omap_clk {
 #define CK_443X         (1 << 11)
 #define CK_TI816X       (1 << 12)
 #define CK_446X         (1 << 13)
+#define CK_AM33XX       (1 << 14)       /* AM33xx specific clocks */
 #define CK_1710         (1 << 15)       /* 1710 extra for rate selection */
 
 
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index d0ef57c1d71b..656b9862279e 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -156,7 +156,6 @@ struct dpll_data {
         u8                      min_divider;
         u16                     max_divider;
         u8                      modes;
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
         void __iomem            *autoidle_reg;
         void __iomem            *idlest_reg;
         u32                     autoidle_mask;
@@ -167,7 +166,6 @@ struct dpll_data {
         u8                      auto_recal_bit;
         u8                      recal_en_bit;
         u8                      recal_st_bit;
-#  endif
         u8                      flags;
 };
 
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 297245dba66e..68b180edcfff 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -9,7 +9,7 @@
  *
  * Written by Tony Lindgren <tony.lindgren@nokia.com>
  *
- * Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
+ * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -70,6 +70,7 @@ unsigned int omap_rev(void);
  * cpu_is_omap443x():   True for OMAP4430
  * cpu_is_omap446x():   True for OMAP4460
  * cpu_is_omap447x():   True for OMAP4470
+ * soc_is_omap543x():   True for OMAP5430, OMAP5432
  */
 #define GET_OMAP_CLASS  (omap_rev() & 0xff)
 
@@ -122,6 +123,7 @@ IS_OMAP_CLASS(24xx, 0x24)
 IS_OMAP_CLASS(34xx, 0x34)
 IS_OMAP_CLASS(44xx, 0x44)
 IS_AM_CLASS(35xx, 0x35)
+IS_OMAP_CLASS(54xx, 0x54)
 IS_AM_CLASS(33xx, 0x33)
 
 IS_TI_CLASS(81xx, 0x81)
@@ -133,6 +135,7 @@ IS_OMAP_SUBCLASS(363x, 0x363)
 IS_OMAP_SUBCLASS(443x, 0x443)
 IS_OMAP_SUBCLASS(446x, 0x446)
 IS_OMAP_SUBCLASS(447x, 0x447)
+IS_OMAP_SUBCLASS(543x, 0x543)
 
 IS_TI_SUBCLASS(816x, 0x816)
 IS_TI_SUBCLASS(814x, 0x814)
@@ -150,12 +153,14 @@ IS_AM_SUBCLASS(335x, 0x335)
 #define cpu_is_ti816x()                 0
 #define cpu_is_ti814x()                 0
 #define soc_is_am35xx()                 0
-#define cpu_is_am33xx()                 0
-#define cpu_is_am335x()                 0
+#define soc_is_am33xx()                 0
+#define soc_is_am335x()                 0
 #define cpu_is_omap44xx()               0
 #define cpu_is_omap443x()               0
 #define cpu_is_omap446x()               0
 #define cpu_is_omap447x()               0
+#define soc_is_omap54xx()               0
+#define soc_is_omap543x()               0
 
 #if defined(MULTI_OMAP1)
 # if defined(CONFIG_ARCH_OMAP730)
@@ -238,9 +243,7 @@ IS_AM_SUBCLASS(335x, 0x335)
 /*
  * Macros to detect individual cpu types.
  * These are only rarely needed.
- * cpu_is_omap330():    True for OMAP330
- * cpu_is_omap730():    True for OMAP730
- * cpu_is_omap850():    True for OMAP850
+ * cpu_is_omap310():    True for OMAP310
  * cpu_is_omap1510():   True for OMAP1510
  * cpu_is_omap1610():   True for OMAP1610
  * cpu_is_omap1611():   True for OMAP1611
@@ -252,8 +255,6 @@ IS_AM_SUBCLASS(335x, 0x335)
  * cpu_is_omap2423():   True for OMAP2423
  * cpu_is_omap2430():   True for OMAP2430
  * cpu_is_omap3430():   True for OMAP3430
- * cpu_is_omap3505():   True for OMAP3505
- * cpu_is_omap3517():   True for OMAP3517
  */
 #define GET_OMAP_TYPE   ((omap_rev() >> 16) & 0xffff)
 
@@ -264,8 +265,6 @@ static inline int is_omap ##type (void)			\
 }
 
 IS_OMAP_TYPE(310, 0x0310)
-IS_OMAP_TYPE(730, 0x0730)
-IS_OMAP_TYPE(850, 0x0850)
 IS_OMAP_TYPE(1510, 0x1510)
 IS_OMAP_TYPE(1610, 0x1610)
 IS_OMAP_TYPE(1611, 0x1611)
@@ -277,12 +276,8 @@ IS_OMAP_TYPE(2422, 0x2422)
 IS_OMAP_TYPE(2423, 0x2423)
 IS_OMAP_TYPE(2430, 0x2430)
 IS_OMAP_TYPE(3430, 0x3430)
-IS_OMAP_TYPE(3505, 0x3517)
-IS_OMAP_TYPE(3517, 0x3517)
 
 #define cpu_is_omap310()                0
-#define cpu_is_omap730()                0
-#define cpu_is_omap850()                0
 #define cpu_is_omap1510()               0
 #define cpu_is_omap1610()               0
 #define cpu_is_omap5912()               0
@@ -293,30 +288,15 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define cpu_is_omap2422()               0
 #define cpu_is_omap2423()               0
 #define cpu_is_omap2430()               0
-#define cpu_is_omap3503()               0
-#define cpu_is_omap3515()               0
-#define cpu_is_omap3525()               0
-#define cpu_is_omap3530()               0
-#define cpu_is_omap3505()               0
-#define cpu_is_omap3517()               0
 #define cpu_is_omap3430()               0
 #define cpu_is_omap3630()               0
+#define soc_is_omap5430()               0
 
 /*
  * Whether we have MULTI_OMAP1 or not, we still need to distinguish
- * between 730 vs 850, 330 vs. 1510 and 1611B/5912 vs. 1710.
+ * between 310 vs. 1510 and 1611B/5912 vs. 1710.
  */
 
-#if defined(CONFIG_ARCH_OMAP730)
-# undef  cpu_is_omap730
-# define cpu_is_omap730()               is_omap730()
-#endif
-
-#if defined(CONFIG_ARCH_OMAP850)
-# undef  cpu_is_omap850
-# define cpu_is_omap850()               is_omap850()
-#endif
-
 #if defined(CONFIG_ARCH_OMAP15XX)
 # undef  cpu_is_omap310
 # undef  cpu_is_omap1510
@@ -350,40 +330,24 @@ IS_OMAP_TYPE(3517, 0x3517)
 
 #if defined(CONFIG_ARCH_OMAP3)
 # undef cpu_is_omap3430
-# undef cpu_is_omap3503
-# undef cpu_is_omap3515
-# undef cpu_is_omap3525
-# undef cpu_is_omap3530
-# undef cpu_is_omap3505
-# undef cpu_is_omap3517
 # undef cpu_is_ti81xx
 # undef cpu_is_ti816x
 # undef cpu_is_ti814x
 # undef soc_is_am35xx
-# undef cpu_is_am33xx
-# undef cpu_is_am335x
 # define cpu_is_omap3430()              is_omap3430()
-# define cpu_is_omap3503()              (cpu_is_omap3430() &&           \
-                                                (!omap3_has_iva()) &&   \
-                                                (!omap3_has_sgx()))
-# define cpu_is_omap3515()              (cpu_is_omap3430() &&           \
-                                                (!omap3_has_iva()) &&   \
-                                                (omap3_has_sgx()))
-# define cpu_is_omap3525()              (cpu_is_omap3430() &&           \
-                                                (!omap3_has_sgx()) &&   \
-                                                (omap3_has_iva()))
-# define cpu_is_omap3530()              (cpu_is_omap3430())
-# define cpu_is_omap3517()              is_omap3517()
-# define cpu_is_omap3505()              (cpu_is_omap3517() &&           \
-                                                !omap3_has_sgx())
 # undef cpu_is_omap3630
 # define cpu_is_omap3630()              is_omap363x()
 # define cpu_is_ti81xx()                is_ti81xx()
 # define cpu_is_ti816x()                is_ti816x()
 # define cpu_is_ti814x()                is_ti814x()
 # define soc_is_am35xx()                is_am35xx()
-# define cpu_is_am33xx()                is_am33xx()
-# define cpu_is_am335x()                is_am335x()
+#endif
+
+# if defined(CONFIG_SOC_AM33XX)
+# undef soc_is_am33xx
+# undef soc_is_am335x
+# define soc_is_am33xx()                is_am33xx()
+# define soc_is_am335x()                is_am335x()
 #endif
 
 # if defined(CONFIG_ARCH_OMAP4)
@@ -397,11 +361,18 @@ IS_OMAP_TYPE(3517, 0x3517)
 # define cpu_is_omap447x()              is_omap447x()
 # endif
 
+# if defined(CONFIG_SOC_OMAP5)
+# undef soc_is_omap54xx
+# undef soc_is_omap543x
+# define soc_is_omap54xx()              is_omap54xx()
+# define soc_is_omap543x()              is_omap543x()
+#endif
+
 /* Macros to detect if we have OMAP1 or OMAP2 */
 #define cpu_class_is_omap1()    (cpu_is_omap7xx() || cpu_is_omap15xx() || \
                                 cpu_is_omap16xx())
 #define cpu_class_is_omap2()    (cpu_is_omap24xx() || cpu_is_omap34xx() || \
-                                cpu_is_omap44xx())
+                                cpu_is_omap44xx() || soc_is_omap54xx())
 
 /* Various silicon revisions for omap2 */
 #define OMAP242X_CLASS          0x24200024
@@ -424,10 +395,6 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define OMAP3630_REV_ES1_1      (OMAP363X_CLASS | (0x1 << 8))
 #define OMAP3630_REV_ES1_2      (OMAP363X_CLASS | (0x2 << 8))
 
-#define OMAP3517_CLASS          0x35170034
-#define OMAP3517_REV_ES1_0      OMAP3517_CLASS
-#define OMAP3517_REV_ES1_1      (OMAP3517_CLASS | (0x1 << 8))
-
 #define TI816X_CLASS            0x81600034
 #define TI8168_REV_ES1_0        TI816X_CLASS
 #define TI8168_REV_ES1_1        (TI816X_CLASS | (0x1 << 8))
@@ -441,7 +408,7 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define AM35XX_REV_ES1_0        AM35XX_CLASS
 #define AM35XX_REV_ES1_1        (AM35XX_CLASS | (0x1 << 8))
 
-#define AM335X_CLASS            0x33500034
+#define AM335X_CLASS            0x33500033
 #define AM335X_REV_ES1_0        AM335X_CLASS
 
 #define OMAP443X_CLASS          0x44300044
@@ -458,9 +425,14 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define OMAP447X_CLASS          0x44700044
 #define OMAP4470_REV_ES1_0      (OMAP447X_CLASS | (0x10 << 8))
 
+#define OMAP54XX_CLASS          0x54000054
+#define OMAP5430_REV_ES1_0      (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8))
+#define OMAP5432_REV_ES1_0      (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
+
 void omap2xxx_check_revision(void);
 void omap3xxx_check_revision(void);
 void omap4xxx_check_revision(void);
+void omap5xxx_check_revision(void);
 void omap3xxx_check_features(void);
 void ti81xx_check_features(void);
 void omap4xxx_check_features(void);
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 5da73562e486..19e7fa577bd0 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -55,23 +55,17 @@
 #define OMAP_TIMER_TRIGGER_OVERFLOW             0x01
 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
 
-/*
- * IP revision identifier so that Highlander IP
- * in OMAP4 can be distinguished.
- */
-#define OMAP_TIMER_IP_VERSION_1                        0x1
-
 /* timer capabilities used in hwmod database */
 #define OMAP_TIMER_SECURE                               0x80000000
 #define OMAP_TIMER_ALWON                                0x40000000
 #define OMAP_TIMER_HAS_PWM                              0x20000000
+#define OMAP_TIMER_NEEDS_RESET                          0x10000000
 
 struct omap_timer_capability_dev_attr {
         u32 timer_capability;
 };
 
 struct omap_dm_timer;
-struct clk;
 
 struct timer_regs {
         u32 tidr;
@@ -96,16 +90,12 @@ struct timer_regs {
 };
 
 struct dmtimer_platform_data {
+        /* set_timer_src - Only used for OMAP1 devices */
         int (*set_timer_src)(struct platform_device *pdev, int source);
-        int timer_ip_version;
-        u32 needs_manual_reset:1;
-        bool reserved;
-
-        bool loses_context;
-
-        int (*get_context_loss_count)(struct device *dev);
+        u32 timer_capability;
 };
 
+int omap_dm_timer_reserve_systimer(int id);
 struct omap_dm_timer *omap_dm_timer_request(void);
 struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
 int omap_dm_timer_free(struct omap_dm_timer *timer);
@@ -272,13 +262,11 @@ struct omap_dm_timer {
         unsigned reserved:1;
         unsigned posted:1;
         struct timer_regs context;
-        bool loses_context;
         int ctx_loss_count;
         int revision;
+        u32 capability;
         struct platform_device *pdev;
         struct list_head node;
-
-        int (*get_context_loss_count)(struct device *dev);
 };
 
 int omap_dm_timer_prepare(struct omap_dm_timer *timer);
diff --git a/arch/arm/plat-omap/include/plat/dsp.h b/arch/arm/plat-omap/include/plat/dsp.h
index 9c604b390f9f..5927709b1908 100644
--- a/arch/arm/plat-omap/include/plat/dsp.h
+++ b/arch/arm/plat-omap/include/plat/dsp.h
@@ -18,6 +18,9 @@ struct omap_dsp_platform_data {
         u32 (*dsp_cm_read)(s16 , u16);
         u32 (*dsp_cm_rmw_bits)(u32, u32, s16, s16);
 
+        void (*set_bootaddr)(u32);
+        void (*set_bootmode)(u8);
+
         phys_addr_t phys_mempool_base;
         phys_addr_t phys_mempool_size;
 };
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index e897978371c2..ddbde38e1e33 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -288,5 +288,6 @@
 #include <plat/omap44xx.h>
 #include <plat/ti81xx.h>
 #include <plat/am33xx.h>
+#include <plat/omap54xx.h>
 
 #endif  /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index a7754a886d42..5493bd95da5e 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -172,8 +172,7 @@ struct omap_mmc_platform_data {
 extern void omap_mmc_notify_cover_event(struct device *dev, int slot,
                                         int is_closed);
 
-#if     defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
-        defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
+#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
 void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
                                 int nr_controllers);
 void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data);
@@ -185,7 +184,6 @@ static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
 static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
 {
 }
-
 #endif
 
 extern int omap_msdi_reset(struct omap_hwmod *oh);
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
index 999ffba2690c..045e320f1067 100644
--- a/arch/arm/plat-omap/include/plat/multi.h
+++ b/arch/arm/plat-omap/include/plat/multi.h
@@ -99,4 +99,13 @@
 # endif
 #endif
 
+#ifdef CONFIG_SOC_OMAP5
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap5
+# endif
+#endif
+
 #endif  /* __PLAT_OMAP_MULTI_H */
diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h
index aeba71796ad9..323948959200 100644
--- a/arch/arm/plat-omap/include/plat/mux.h
+++ b/arch/arm/plat-omap/include/plat/mux.h
@@ -99,7 +99,7 @@
 
 /*
  * OMAP730/850 has a slightly different config for the pin mux.
- * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
+ * - config regs are the OMAP7XX_IO_CONF_x regs (see omap7xx.h) regs and
  *   not the FUNC_MUX_CTRL_x regs from hardware.h
  * - for pull-up/down, only has one enable bit which is is in the same register
  *   as mux config
diff --git a/arch/arm/plat-omap/include/plat/omap-secure.h b/arch/arm/plat-omap/include/plat/omap-secure.h
index 8c7994ce9869..0e4acd2d2deb 100644
--- a/arch/arm/plat-omap/include/plat/omap-secure.h
+++ b/arch/arm/plat-omap/include/plat/omap-secure.h
@@ -3,12 +3,7 @@
 
 #include <linux/types.h>
 
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 extern int omap_secure_ram_reserve_memblock(void);
-#else
-static inline void omap_secure_ram_reserve_memblock(void)
-{ }
-#endif
 
 #ifdef CONFIG_OMAP4_ERRATA_I688
 extern int omap_barrier_reserve_memblock(void);
diff --git a/arch/arm/plat-omap/include/plat/omap54xx.h b/arch/arm/plat-omap/include/plat/omap54xx.h
new file mode 100644
index 000000000000..a2582bb3cab3
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap54xx.h
@@ -0,0 +1,32 @@
+/*:
+ * Address mappings and base address for OMAP5 interconnects
+ * and peripherals.
+ *
+ * Copyright (C) 2012 Texas Instruments
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *      Sricharan <r.sricharan@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_SOC_OMAP54XX_H
+#define __ASM_SOC_OMAP54XX_H
+
+/*
+ * Please place only base defines here and put the rest in device
+ * specific headers.
+ */
+#define L4_54XX_BASE                    0x4a000000
+#define L4_WK_54XX_BASE                 0x4ae00000
+#define L4_PER_54XX_BASE                0x48000000
+#define L3_54XX_BASE                    0x44000000
+#define OMAP54XX_32KSYNCT_BASE          0x4ae04000
+#define OMAP54XX_CM_CORE_AON_BASE       0x4a004000
+#define OMAP54XX_CM_CORE_BASE           0x4a008000
+#define OMAP54XX_PRM_BASE               0x4ae06000
+#define OMAP54XX_PRCM_MPU_BASE          0x48243000
+#define OMAP54XX_SCM_BASE               0x4a002000
+#define OMAP54XX_CTRL_BASE              0x4a002800
+
+#endif /* __ASM_SOC_OMAP555554XX_H */
diff --git a/arch/arm/plat-omap/include/plat/omap730.h b/arch/arm/plat-omap/include/plat/omap730.h
deleted file mode 100644
index 14272bc1a6fd..000000000000
--- a/arch/arm/plat-omap/include/plat/omap730.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* arch/arm/plat-omap/include/mach/omap730.h
- *
- * Hardware definitions for TI OMAP730 processor.
- *
- * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP730_H
-#define __ASM_ARCH_OMAP730_H
-
-/*
- * ----------------------------------------------------------------------------
- * Base addresses
- * ----------------------------------------------------------------------------
- */
-
-/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
-
-#define OMAP730_DSP_BASE        0xE0000000
-#define OMAP730_DSP_SIZE        0x50000
-#define OMAP730_DSP_START       0xE0000000
-
-#define OMAP730_DSPREG_BASE     0xE1000000
-#define OMAP730_DSPREG_SIZE     SZ_128K
-#define OMAP730_DSPREG_START    0xE1000000
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP730 specific configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP730_CONFIG_BASE     0xfffe1000
-#define OMAP730_IO_CONF_0       0xfffe1070
-#define OMAP730_IO_CONF_1       0xfffe1074
-#define OMAP730_IO_CONF_2       0xfffe1078
-#define OMAP730_IO_CONF_3       0xfffe107c
-#define OMAP730_IO_CONF_4       0xfffe1080
-#define OMAP730_IO_CONF_5       0xfffe1084
-#define OMAP730_IO_CONF_6       0xfffe1088
-#define OMAP730_IO_CONF_7       0xfffe108c
-#define OMAP730_IO_CONF_8       0xfffe1090
-#define OMAP730_IO_CONF_9       0xfffe1094
-#define OMAP730_IO_CONF_10      0xfffe1098
-#define OMAP730_IO_CONF_11      0xfffe109c
-#define OMAP730_IO_CONF_12      0xfffe10a0
-#define OMAP730_IO_CONF_13      0xfffe10a4
-
-#define OMAP730_MODE_1          0xfffe1010
-#define OMAP730_MODE_2          0xfffe1014
-
-/* CSMI specials: in terms of base + offset */
-#define OMAP730_MODE2_OFFSET    0x14
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP730 traffic controller configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP730_FLASH_CFG_0     0xfffecc10
-#define OMAP730_FLASH_ACFG_0    0xfffecc50
-#define OMAP730_FLASH_CFG_1     0xfffecc14
-#define OMAP730_FLASH_ACFG_1    0xfffecc54
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP730 DSP control registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP730_ICR_BASE        0xfffbb800
-#define OMAP730_DSP_M_CTL       0xfffbb804
-#define OMAP730_DSP_MMU_BASE    0xfffed200
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP730 PCC_UPLD configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP730_PCC_UPLD_CTRL_BASE      (0xfffe0900)
-#define OMAP730_PCC_UPLD_CTRL           (OMAP730_PCC_UPLD_CTRL_BASE + 0x00)
-
-#endif /*  __ASM_ARCH_OMAP730_H */
-
diff --git a/arch/arm/plat-omap/include/plat/omap850.h b/arch/arm/plat-omap/include/plat/omap850.h
deleted file mode 100644
index c33f67981712..000000000000
--- a/arch/arm/plat-omap/include/plat/omap850.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* arch/arm/plat-omap/include/mach/omap850.h
- *
- * Hardware definitions for TI OMAP850 processor.
- *
- * Derived from omap730.h by Zebediah C. McClure <zmc@lurian.net>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP850_H
-#define __ASM_ARCH_OMAP850_H
-
-/*
- * ----------------------------------------------------------------------------
- * Base addresses
- * ----------------------------------------------------------------------------
- */
-
-/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
-
-#define OMAP850_DSP_BASE        0xE0000000
-#define OMAP850_DSP_SIZE        0x50000
-#define OMAP850_DSP_START       0xE0000000
-
-#define OMAP850_DSPREG_BASE     0xE1000000
-#define OMAP850_DSPREG_SIZE     SZ_128K
-#define OMAP850_DSPREG_START    0xE1000000
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP850 specific configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP850_CONFIG_BASE     0xfffe1000
-#define OMAP850_IO_CONF_0       0xfffe1070
-#define OMAP850_IO_CONF_1       0xfffe1074
-#define OMAP850_IO_CONF_2       0xfffe1078
-#define OMAP850_IO_CONF_3       0xfffe107c
-#define OMAP850_IO_CONF_4       0xfffe1080
-#define OMAP850_IO_CONF_5       0xfffe1084
-#define OMAP850_IO_CONF_6       0xfffe1088
-#define OMAP850_IO_CONF_7       0xfffe108c
-#define OMAP850_IO_CONF_8       0xfffe1090
-#define OMAP850_IO_CONF_9       0xfffe1094
-#define OMAP850_IO_CONF_10      0xfffe1098
-#define OMAP850_IO_CONF_11      0xfffe109c
-#define OMAP850_IO_CONF_12      0xfffe10a0
-#define OMAP850_IO_CONF_13      0xfffe10a4
-
-#define OMAP850_MODE_1          0xfffe1010
-#define OMAP850_MODE_2          0xfffe1014
-
-/* CSMI specials: in terms of base + offset */
-#define OMAP850_MODE2_OFFSET    0x14
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP850 traffic controller configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP850_FLASH_CFG_0     0xfffecc10
-#define OMAP850_FLASH_ACFG_0    0xfffecc50
-#define OMAP850_FLASH_CFG_1     0xfffecc14
-#define OMAP850_FLASH_ACFG_1    0xfffecc54
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP850 DSP control registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP850_ICR_BASE        0xfffbb800
-#define OMAP850_DSP_M_CTL       0xfffbb804
-#define OMAP850_DSP_MMU_BASE    0xfffed200
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP850 PCC_UPLD configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP850_PCC_UPLD_CTRL_BASE      (0xfffe0900)
-#define OMAP850_PCC_UPLD_CTRL           (OMAP850_PCC_UPLD_CTRL_BASE + 0x00)
-
-#endif /*  __ASM_ARCH_OMAP850_H */
-
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index c835b7194ff5..6132972aff37 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -41,6 +41,7 @@ struct omap_device;
 
 extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1;
 extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
+extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3;
 
 /*
  * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant
@@ -69,6 +70,17 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
 #define SYSC_TYPE2_SIDLEMODE_MASK       (0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT)
 #define SYSC_TYPE2_MIDLEMODE_SHIFT      4
 #define SYSC_TYPE2_MIDLEMODE_MASK       (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT)
+#define SYSC_TYPE2_DMADISABLE_SHIFT     16
+#define SYSC_TYPE2_DMADISABLE_MASK      (0x1 << SYSC_TYPE2_DMADISABLE_SHIFT)
+
+/*
+ * OCP SYSCONFIG bit shifts/masks TYPE3.
+ * This is applicable for some IPs present in AM33XX
+ */
+#define SYSC_TYPE3_SIDLEMODE_SHIFT      0
+#define SYSC_TYPE3_SIDLEMODE_MASK       (0x3 << SYSC_TYPE3_SIDLEMODE_SHIFT)
+#define SYSC_TYPE3_MIDLEMODE_SHIFT      2
+#define SYSC_TYPE3_MIDLEMODE_MASK       (0x3 << SYSC_TYPE3_MIDLEMODE_SHIFT)
 
 /* OCP SYSSTATUS bit shifts/masks */
 #define SYSS_RESETDONE_SHIFT            0
@@ -283,6 +295,7 @@ struct omap_hwmod_ocp_if {
 #define SYSS_HAS_RESET_STATUS   (1 << 7)
 #define SYSC_NO_CACHE           (1 << 8)  /* XXX SW flag, belongs elsewhere */
 #define SYSC_HAS_RESET_STATUS   (1 << 9)
+#define SYSC_HAS_DMADISABLE     (1 << 10)
 
 /* omap_hwmod_sysconfig.clockact flags */
 #define CLOCKACT_TEST_BOTH      0x0
@@ -298,6 +311,7 @@ struct omap_hwmod_ocp_if {
  * @enwkup_shift: Offset of the enawakeup bit
  * @srst_shift: Offset of the softreset bit
  * @autoidle_shift: Offset of the autoidle bit
+ * @dmadisable_shift: Offset of the dmadisable bit
  */
 struct omap_hwmod_sysc_fields {
         u8 midle_shift;
@@ -306,6 +320,7 @@ struct omap_hwmod_sysc_fields {
         u8 enwkup_shift;
         u8 srst_shift;
         u8 autoidle_shift;
+        u8 dmadisable_shift;
 };
 
 /**
@@ -374,11 +389,13 @@ struct omap_hwmod_omap2_prcm {
  * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
  * @clkctrl_reg: PRCM address of the clock control register
  * @rstctrl_reg: address of the XXX_RSTCTRL register located in the PRM
+ * @rstst_reg: (AM33XX only) address of the XXX_RSTST register in the PRM
  * @submodule_wkdep_bit: bit shift of the WKDEP range
  */
 struct omap_hwmod_omap4_prcm {
         u16             clkctrl_offs;
         u16             rstctrl_offs;
+        u16             rstst_offs;
         u16             context_offs;
         u8              submodule_wkdep_bit;
         u8              modulemode;
@@ -629,6 +646,10 @@ int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);
 
 int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx);
 
+extern void __init omap_hwmod_init(void);
+
+const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh);
+
 /*
  * Chip variant-specific hwmod init routines - XXX should be converted
  * to use initcalls once the initial boot ordering is straightened out
diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
index 9bb978ecd884..36d6a7666216 100644
--- a/arch/arm/plat-omap/include/plat/sdrc.h
+++ b/arch/arm/plat-omap/include/plat/sdrc.h
@@ -123,7 +123,7 @@ struct omap_sdrc_params {
         u32 mr;
 };
 
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+#ifdef CONFIG_SOC_HAS_OMAP2_SDRC
 void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                             struct omap_sdrc_params *sdrc_cs1);
 #else
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index b073e5f2b190..65fce44dce34 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -60,6 +60,17 @@
 /* AM3505/3517 UART4 */
 #define AM35XX_UART4_BASE       0x4809E000      /* Only on AM3505/3517 */
 
+/* AM33XX serial port */
+#define AM33XX_UART1_BASE       0x44E09000
+
+/* OMAP5 serial ports */
+#define OMAP5_UART1_BASE        OMAP2_UART1_BASE
+#define OMAP5_UART2_BASE        OMAP2_UART2_BASE
+#define OMAP5_UART3_BASE        OMAP4_UART3_BASE
+#define OMAP5_UART4_BASE        OMAP4_UART4_BASE
+#define OMAP5_UART5_BASE        0x48066000
+#define OMAP5_UART6_BASE        0x48068000
+
 /* External port on Zoom2/3 */
 #define ZOOM_UART_BASE          0x10000000
 #define ZOOM_UART_VIRT          0xfa400000
@@ -93,6 +104,9 @@
 #define TI81XXUART1             81
 #define TI81XXUART2             82
 #define TI81XXUART3             83
+#define AM33XXUART1             84
+#define OMAP5UART3              OMAP4UART3
+#define OMAP5UART4              OMAP4UART4
 #define ZOOM_UART               95              /* Only on zoom2/3 */
 
 /* This is only used by 8250.c for omap1510 */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index cc3f11ba7a99..b8d19a136781 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -95,6 +95,9 @@ static inline void flush(void)
         _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT,    \
                 OMAP4UART##p)
 
+#define DEBUG_LL_OMAP5(p, mach)                                         \
+        _DEBUG_LL_ENTRY(mach, OMAP5_UART##p##_BASE, OMAP_PORT_SHIFT,    \
+                OMAP5UART##p)
 /* Zoom2/3 shift is different for UART1 and external port */
 #define DEBUG_LL_ZOOM(mach)                                             \
         _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
@@ -103,6 +106,10 @@ static inline void flush(void)
         _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT,   \
                 TI81XXUART##p)
 
+#define DEBUG_LL_AM33XX(p, mach)                                        \
+        _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT,   \
+                AM33XXUART##p)
+
 static inline void __arch_decomp_setup(unsigned long arch_id)
 {
         int port = 0;
@@ -173,6 +180,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                 DEBUG_LL_OMAP4(3, omap_4430sdp);
                 DEBUG_LL_OMAP4(3, omap4_panda);
 
+                /* omap5 based boards using UART3 */
+                DEBUG_LL_OMAP5(3, omap5_sevm);
+
                 /* zoom2/3 external uart */
                 DEBUG_LL_ZOOM(omap_zoom2);
                 DEBUG_LL_ZOOM(omap_zoom3);
@@ -183,6 +193,8 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                 /* TI8148 base boards using UART1 */
                 DEBUG_LL_TI81XX(1, ti8148evm);
 
+                /* AM33XX base boards using UART1 */
+                DEBUG_LL_AM33XX(1, am335xevm);
         } while (0);
 }
 
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 762eeb0626c1..548a4c8d63df 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -44,6 +44,8 @@ struct usbhs_omap_board_data {
         struct regulator                *regulator[OMAP3_HS_USB_PORTS];
 };
 
+#ifdef CONFIG_ARCH_OMAP2PLUS
+
 struct ehci_hcd_omap_platform_data {
         enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
         int                             reset_gpio_port[OMAP3_HS_USB_PORTS];
@@ -64,26 +66,6 @@ struct usbhs_omap_platform_data {
 };
 /*-------------------------------------------------------------------------*/
 
-#define OMAP1_OTG_BASE                  0xfffb0400
-#define OMAP1_UDC_BASE                  0xfffb4000
-#define OMAP1_OHCI_BASE                 0xfffba000
-
-#define OMAP2_OHCI_BASE                 0x4805e000
-#define OMAP2_UDC_BASE                  0x4805e200
-#define OMAP2_OTG_BASE                  0x4805e300
-
-#ifdef CONFIG_ARCH_OMAP1
-
-#define OTG_BASE                        OMAP1_OTG_BASE
-#define UDC_BASE                        OMAP1_UDC_BASE
-#define OMAP_OHCI_BASE                  OMAP1_OHCI_BASE
-
-#else
-
-#define OTG_BASE                        OMAP2_OTG_BASE
-#define UDC_BASE                        OMAP2_UDC_BASE
-#define OMAP_OHCI_BASE                  OMAP2_OHCI_BASE
-
 struct omap_musb_board_data {
         u8      interface_type;
         u8      mode;
@@ -107,44 +89,6 @@ extern int omap4430_phy_init(struct device *dev);
 extern int omap4430_phy_exit(struct device *dev);
 extern int omap4430_phy_suspend(struct device *dev, int suspend);
 
-/*
- * NOTE: Please update omap USB drivers to use ioremap + read/write
- */
-
-#define OMAP2_L4_IO_OFFSET      0xb2000000
-#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET)
-
-static inline u8 omap_readb(u32 pa)
-{
-        return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
-}
-
-static inline u16 omap_readw(u32 pa)
-{
-        return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
-}
-
-static inline u32 omap_readl(u32 pa)
-{
-        return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
-}
-
-static inline void omap_writeb(u8 v, u32 pa)
-{
-        __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-
-
-static inline void omap_writew(u16 v, u32 pa)
-{
-        __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-
-static inline void omap_writel(u32 v, u32 pa)
-{
-        __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-
 #endif
 
 extern void am35x_musb_reset(void);
@@ -153,142 +97,6 @@ extern void am35x_musb_clear_irq(void);
 extern void am35x_set_mode(u8 musb_mode);
 extern void ti81xx_musb_phy_power(u8 on);
 
-/*
- * FIXME correct answer depends on hmc_mode,
- * as does (on omap1) any nonzero value for config->otg port number
- */
-#ifdef  CONFIG_USB_GADGET_OMAP
-#define is_usb0_device(config)  1
-#else
-#define is_usb0_device(config)  0
-#endif
-
-void omap_otg_init(struct omap_usb_config *config);
-
-#if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
-void omap1_usb_init(struct omap_usb_config *pdata);
-#else
-static inline void omap1_usb_init(struct omap_usb_config *pdata)
-{
-}
-#endif
-
-#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
-void omap2_usbfs_init(struct omap_usb_config *pdata);
-#else
-static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
-{
-}
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * OTG and transceiver registers, for OMAPs starting with ARM926
- */
-#define OTG_REV                         (OTG_BASE + 0x00)
-#define OTG_SYSCON_1                    (OTG_BASE + 0x04)
-#       define   USB2_TRX_MODE(w)       (((w)>>24)&0x07)
-#       define   USB1_TRX_MODE(w)       (((w)>>20)&0x07)
-#       define   USB0_TRX_MODE(w)       (((w)>>16)&0x07)
-#       define   OTG_IDLE_EN            (1 << 15)
-#       define   HST_IDLE_EN            (1 << 14)
-#       define   DEV_IDLE_EN            (1 << 13)
-#       define   OTG_RESET_DONE         (1 << 2)
-#       define   OTG_SOFT_RESET         (1 << 1)
-#define OTG_SYSCON_2                    (OTG_BASE + 0x08)
-#       define   OTG_EN                 (1 << 31)
-#       define   USBX_SYNCHRO           (1 << 30)
-#       define   OTG_MST16              (1 << 29)
-#       define   SRP_GPDATA             (1 << 28)
-#       define   SRP_GPDVBUS            (1 << 27)
-#       define   SRP_GPUVBUS(w)         (((w)>>24)&0x07)
-#       define   A_WAIT_VRISE(w)        (((w)>>20)&0x07)
-#       define   B_ASE_BRST(w)          (((w)>>16)&0x07)
-#       define   SRP_DPW                (1 << 14)
-#       define   SRP_DATA               (1 << 13)
-#       define   SRP_VBUS               (1 << 12)
-#       define   OTG_PADEN              (1 << 10)
-#       define   HMC_PADEN              (1 << 9)
-#       define   UHOST_EN               (1 << 8)
-#       define   HMC_TLLSPEED           (1 << 7)
-#       define   HMC_TLLATTACH          (1 << 6)
-#       define   OTG_HMC(w)             (((w)>>0)&0x3f)
-#define OTG_CTRL                        (OTG_BASE + 0x0c)
-#       define   OTG_USB2_EN            (1 << 29)
-#       define   OTG_USB2_DP            (1 << 28)
-#       define   OTG_USB2_DM            (1 << 27)
-#       define   OTG_USB1_EN            (1 << 26)
-#       define   OTG_USB1_DP            (1 << 25)
-#       define   OTG_USB1_DM            (1 << 24)
-#       define   OTG_USB0_EN            (1 << 23)
-#       define   OTG_USB0_DP            (1 << 22)
-#       define   OTG_USB0_DM            (1 << 21)
-#       define   OTG_ASESSVLD           (1 << 20)
-#       define   OTG_BSESSEND           (1 << 19)
-#       define   OTG_BSESSVLD           (1 << 18)
-#       define   OTG_VBUSVLD            (1 << 17)
-#       define   OTG_ID                 (1 << 16)
-#       define   OTG_DRIVER_SEL         (1 << 15)
-#       define   OTG_A_SETB_HNPEN       (1 << 12)
-#       define   OTG_A_BUSREQ           (1 << 11)
-#       define   OTG_B_HNPEN            (1 << 9)
-#       define   OTG_B_BUSREQ           (1 << 8)
-#       define   OTG_BUSDROP            (1 << 7)
-#       define   OTG_PULLDOWN           (1 << 5)
-#       define   OTG_PULLUP             (1 << 4)
-#       define   OTG_DRV_VBUS           (1 << 3)
-#       define   OTG_PD_VBUS            (1 << 2)
-#       define   OTG_PU_VBUS            (1 << 1)
-#       define   OTG_PU_ID              (1 << 0)
-#define OTG_IRQ_EN                      (OTG_BASE + 0x10)       /* 16-bit */
-#       define   DRIVER_SWITCH          (1 << 15)
-#       define   A_VBUS_ERR             (1 << 13)
-#       define   A_REQ_TMROUT           (1 << 12)
-#       define   A_SRP_DETECT           (1 << 11)
-#       define   B_HNP_FAIL             (1 << 10)
-#       define   B_SRP_TMROUT           (1 << 9)
-#       define   B_SRP_DONE             (1 << 8)
-#       define   B_SRP_STARTED          (1 << 7)
-#       define   OPRT_CHG               (1 << 0)
-#define OTG_IRQ_SRC                     (OTG_BASE + 0x14)       /* 16-bit */
-        // same bits as in IRQ_EN
-#define OTG_OUTCTRL                     (OTG_BASE + 0x18)       /* 16-bit */
-#       define   OTGVPD                 (1 << 14)
-#       define   OTGVPU                 (1 << 13)
-#       define   OTGPUID                (1 << 12)
-#       define   USB2VDR                (1 << 10)
-#       define   USB2PDEN               (1 << 9)
-#       define   USB2PUEN               (1 << 8)
-#       define   USB1VDR                (1 << 6)
-#       define   USB1PDEN               (1 << 5)
-#       define   USB1PUEN               (1 << 4)
-#       define   USB0VDR                (1 << 2)
-#       define   USB0PDEN               (1 << 1)
-#       define   USB0PUEN               (1 << 0)
-#define OTG_TEST                        (OTG_BASE + 0x20)       /* 16-bit */
-#define OTG_VENDOR_CODE                 (OTG_BASE + 0xfc)       /* 16-bit */
-
-/*-------------------------------------------------------------------------*/
-
-/* OMAP1 */
-#define USB_TRANSCEIVER_CTRL            (0xfffe1000 + 0x0064)
-#       define  CONF_USB2_UNI_R         (1 << 8)
-#       define  CONF_USB1_UNI_R         (1 << 7)
-#       define  CONF_USB_PORT0_R(x)     (((x)>>4)&0x7)
-#       define  CONF_USB0_ISOLATE_R     (1 << 3)
-#       define  CONF_USB_PWRDN_DM_R     (1 << 2)
-#       define  CONF_USB_PWRDN_DP_R     (1 << 1)
-
-/* OMAP2 */
-#       define  USB_UNIDIR                      0x0
-#       define  USB_UNIDIR_TLL                  0x1
-#       define  USB_BIDIR                       0x2
-#       define  USB_BIDIR_TLL                   0x3
-#       define  USBTXWRMODEI(port, x)   ((x) << (22 - (port * 2)))
-#       define  USBT2TLL5PI             (1 << 17)
-#       define  USB0PUENACTLOI          (1 << 16)
-#       define  USBSTANDBYCTRL          (1 << 15)
 /* AM35x */
 /* USB 2.0 PHY Control */
 #define CONF2_PHY_GPIOMODE      (1 << 23)
diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
index 0a6a482ec014..5be4d5def427 100644
--- a/arch/arm/plat-omap/include/plat/voltage.h
+++ b/arch/arm/plat-omap/include/plat/voltage.h
@@ -11,10 +11,29 @@
 #ifndef __ARCH_ARM_OMAP_VOLTAGE_H
 #define __ARCH_ARM_OMAP_VOLTAGE_H
 
+/**
+ * struct omap_volt_data - Omap voltage specific data.
+ * @voltage_nominal:    The possible voltage value in uV
+ * @sr_efuse_offs:      The offset of the efuse register(from system
+ *                      control module base address) from where to read
+ *                      the n-target value for the smartreflex module.
+ * @sr_errminlimit:     Error min limit value for smartreflex. This value
+ *                      differs at differnet opp and thus is linked
+ *                      with voltage.
+ * @vp_errorgain:       Error gain value for the voltage processor. This
+ *                      field also differs according to the voltage/opp.
+ */
+struct omap_volt_data {
+        u32     volt_nominal;
+        u32     sr_efuse_offs;
+        u8      sr_errminlimit;
+        u8      vp_errgain;
+};
 struct voltagedomain;
 
 struct voltagedomain *voltdm_lookup(const char *name);
 int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
 unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
-
+struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
+                unsigned long volt);
 #endif
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index ad32621aa52e..5e13c3884aa4 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -282,6 +282,8 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
                 }
                 mbox->rxq = mq;
                 mq->mbox = mbox;
+
+                omap_mbox_enable_irq(mbox, IRQ_RX);
         }
         mutex_unlock(&mbox_configured_lock);
         return 0;
@@ -305,6 +307,7 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
         mutex_lock(&mbox_configured_lock);
 
         if (!--mbox->use_count) {
+                omap_mbox_disable_irq(mbox, IRQ_RX);
                 free_irq(mbox->irq, mbox);
                 tasklet_kill(&mbox->txq->tasklet);
                 flush_work_sync(&mbox->rxq->work);
@@ -338,13 +341,15 @@ struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb)
         if (!mbox)
                 return ERR_PTR(-ENOENT);
 
-        ret = omap_mbox_startup(mbox);
-        if (ret)
-                return ERR_PTR(-ENODEV);
-
         if (nb)
                 blocking_notifier_chain_register(&mbox->notifier, nb);
 
+        ret = omap_mbox_startup(mbox);
+        if (ret) {
+                blocking_notifier_chain_unregister(&mbox->notifier, nb);
+                return ERR_PTR(-ENODEV);
+        }
+
         return mbox;
 }
 EXPORT_SYMBOL(omap_mbox_get);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 477363c163ec..766181cb5c95 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -6,8 +6,8 @@
  * Copyright (C) 2005 Nokia Corporation
  * Written by Tony Lindgren <tony@atomide.com>
  *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ * Copyright (C) 2009-2012 Texas Instruments
+ * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -44,6 +44,7 @@
 #else
 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
 #endif
+#define OMAP5_SRAM_PA           0x40300000
 
 #if defined(CONFIG_ARCH_OMAP2PLUS)
 #define SRAM_BOOTLOADER_SZ      0x00
@@ -85,7 +86,7 @@ static int is_sram_locked(void)
                         __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
                         __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
                 }
-                if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
+                if (cpu_is_omap34xx()) {
                         __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
                         __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
                         __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
@@ -118,12 +119,15 @@ static void __init omap_detect_sram(void)
                         } else if (cpu_is_omap44xx()) {
                                 omap_sram_start = OMAP4_SRAM_PUB_PA;
                                 omap_sram_size = 0xa000; /* 40K */
+                        } else if (soc_is_omap54xx()) {
+                                omap_sram_start = OMAP5_SRAM_PA;
+                                omap_sram_size = SZ_128K; /* 128KB */
                         } else {
                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
                                 omap_sram_size = 0x800; /* 2K */
                         }
                 } else {
-                        if (cpu_is_am33xx()) {
+                        if (soc_is_am33xx()) {
                                 omap_sram_start = AM33XX_SRAM_PA;
                                 omap_sram_size = 0x10000; /* 64K */
                         } else if (cpu_is_omap34xx()) {
@@ -132,6 +136,9 @@ static void __init omap_detect_sram(void)
                         } else if (cpu_is_omap44xx()) {
                                 omap_sram_start = OMAP4_SRAM_PA;
                                 omap_sram_size = 0xe000; /* 56K */
+                        } else if (soc_is_omap54xx()) {
+                                omap_sram_start = OMAP5_SRAM_PA;
+                                omap_sram_size = SZ_128K; /* 128KB */
                         } else {
                                 omap_sram_start = OMAP2_SRAM_PA;
                                 if (cpu_is_omap242x())
@@ -386,7 +393,7 @@ int __init omap_sram_init(void)
                 omap242x_sram_init();
         else if (cpu_is_omap2430())
                 omap243x_sram_init();
-        else if (cpu_is_am33xx())
+        else if (soc_is_am33xx())
                 am33xx_sram_init();
         else if (cpu_is_omap34xx())
                 omap34xx_sram_init();
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
deleted file mode 100644
index daa0327381b5..000000000000
--- a/arch/arm/plat-omap/usb.c
+++ /dev/null
@@ -1,145 +0,0 @@
- /*
- * arch/arm/plat-omap/usb.c -- platform level USB initialization
- *
- * Copyright (C) 2004 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#undef  DEBUG
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include <plat/usb.h>
-#include <plat/board.h>
-
-#include <mach/hardware.h>
-
-#ifdef  CONFIG_ARCH_OMAP_OTG
-
-void __init
-omap_otg_init(struct omap_usb_config *config)
-{
-        u32             syscon;
-        int             alt_pingroup = 0;
-
-        /* NOTE:  no bus or clock setup (yet?) */
-
-        syscon = omap_readl(OTG_SYSCON_1) & 0xffff;
-        if (!(syscon & OTG_RESET_DONE))
-                pr_debug("USB resets not complete?\n");
-
-        //omap_writew(0, OTG_IRQ_EN);
-
-        /* pin muxing and transceiver pinouts */
-        if (config->pins[0] > 2)        /* alt pingroup 2 */
-                alt_pingroup = 1;
-        syscon |= config->usb0_init(config->pins[0], is_usb0_device(config));
-        syscon |= config->usb1_init(config->pins[1]);
-        syscon |= config->usb2_init(config->pins[2], alt_pingroup);
-        pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
-        omap_writel(syscon, OTG_SYSCON_1);
-
-        syscon = config->hmc_mode;
-        syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */;
-#ifdef  CONFIG_USB_OTG
-        if (config->otg)
-                syscon |= OTG_EN;
-#endif
-        if (cpu_class_is_omap1())
-                pr_debug("USB_TRANSCEIVER_CTRL = %03x\n",
-                         omap_readl(USB_TRANSCEIVER_CTRL));
-        pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2));
-        omap_writel(syscon, OTG_SYSCON_2);
-
-        printk("USB: hmc %d", config->hmc_mode);
-        if (!alt_pingroup)
-                printk(", usb2 alt %d wires", config->pins[2]);
-        else if (config->pins[0])
-                printk(", usb0 %d wires%s", config->pins[0],
-                        is_usb0_device(config) ? " (dev)" : "");
-        if (config->pins[1])
-                printk(", usb1 %d wires", config->pins[1]);
-        if (!alt_pingroup && config->pins[2])
-                printk(", usb2 %d wires", config->pins[2]);
-        if (config->otg)
-                printk(", Mini-AB on usb%d", config->otg - 1);
-        printk("\n");
-
-        if (cpu_class_is_omap1()) {
-                u16 w;
-
-                /* leave USB clocks/controllers off until needed */
-                w = omap_readw(ULPD_SOFT_REQ);
-                w &= ~SOFT_USB_CLK_REQ;
-                omap_writew(w, ULPD_SOFT_REQ);
-
-                w = omap_readw(ULPD_CLOCK_CTRL);
-                w &= ~USB_MCLK_EN;
-                w |= DIS_USB_PVCI_CLK;
-                omap_writew(w, ULPD_CLOCK_CTRL);
-        }
-        syscon = omap_readl(OTG_SYSCON_1);
-        syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
-
-#ifdef  CONFIG_USB_GADGET_OMAP
-        if (config->otg || config->register_dev) {
-                struct platform_device *udc_device = config->udc_device;
-                int status;
-
-                syscon &= ~DEV_IDLE_EN;
-                udc_device->dev.platform_data = config;
-                status = platform_device_register(udc_device);
-                if (status)
-                        pr_debug("can't register UDC device, %d\n", status);
-        }
-#endif
-
-#if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-        if (config->otg || config->register_host) {
-                struct platform_device *ohci_device = config->ohci_device;
-                int status;
-
-                syscon &= ~HST_IDLE_EN;
-                ohci_device->dev.platform_data = config;
-                status = platform_device_register(ohci_device);
-                if (status)
-                        pr_debug("can't register OHCI device, %d\n", status);
-        }
-#endif
-
-#ifdef  CONFIG_USB_OTG
-        if (config->otg) {
-                struct platform_device *otg_device = config->otg_device;
-                int status;
-
-                syscon &= ~OTG_IDLE_EN;
-                otg_device->dev.platform_data = config;
-                status = platform_device_register(otg_device);
-                if (status)
-                        pr_debug("can't register OTG device, %d\n", status);
-        }
-#endif
-        pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
-        omap_writel(syscon, OTG_SYSCON_1);
-}
-
-#else
-void omap_otg_init(struct omap_usb_config *config) {}
-#endif