Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp

Conflicts: litmus/sched_cedf.c
author: Glenn Elliott <gelliott@cs.unc.edu> 2012-03-04 19:47:13 -0500
committer: Glenn Elliott <gelliott@cs.unc.edu> 2012-03-04 19:47:13 -0500
commit: c71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
tree: ecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /arch/arm/plat-omap
parent: ea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent: 6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
79 files changed, 2660 insertions, 5492 deletions
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index a92cb499313f..49a4c75243fc 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -11,15 +11,18 @@ choice
 config ARCH_OMAP1
        bool "TI OMAP1"
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
        help
          "Systems based on omap7xx, omap15xx or omap16xx"
 config ARCH_OMAP2PLUS
        bool "TI OMAP2/3/4"
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
+        select GENERIC_IRQ_CHIP
+        select OMAP_DM_TIMER
        help
-          "Systems based on omap24xx, omap34xx or omap44xx"
+          "Systems based on OMAP2, OMAP3 or OMAP4"
 endchoice
@@ -35,6 +38,37 @@ config OMAP_DEBUG_LEDS
        depends on OMAP_DEBUG_DEVICES
        default y if LEDS_CLASS
+config OMAP_SMARTREFLEX
+        bool "SmartReflex support"
+        depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM
+        help
+          Say Y if you want to enable SmartReflex.
+          SmartReflex can perform continuous dynamic voltage
+          scaling around the nominal operating point voltage
+          according to silicon characteristics and operating
+          conditions. Enabling SmartReflex reduces power
+          consumption.
+          Please note, that by default SmartReflex is only
+          initialized. To enable the automatic voltage
+          compensation for vdd mpu  and vdd core from user space,
+          user must write 1 to
+                /debug/voltage/vdd_<X>/smartreflex/autocomp,
+          where X is mpu or core for OMAP3.
+          Optionally autocompensation can be enabled in the kernel
+          by default during system init via the enable_on_init flag
+          which an be passed as platform data to the smartreflex driver.
+config OMAP_SMARTREFLEX_CLASS3
+        bool "Class 3 mode of Smartreflex Implementation"
+        depends on OMAP_SMARTREFLEX && TWL4030_CORE
+        help
+          Say Y to enable Class 3 implementation of Smartreflex
+          Class 3 implementation of Smartreflex employs continuous hardware
+          voltage calibration.
 config OMAP_RESET_CLOCKS
        bool "Reset unused clocks during boot"
        depends on ARCH_OMAP
@@ -109,12 +143,12 @@ config OMAP_IOMMU_DEBUG
         Say N unless you know you need this.
-choice
+config OMAP_IOMMU_IVA2
-        prompt "System timer"
+        bool
-        default OMAP_32K_TIMER if !ARCH_OMAP15XX
 config OMAP_MPU_TIMER
        bool "Use mpu timer"
+        depends on ARCH_OMAP1
        help
          Select this option if you want to use the OMAP mpu timer. This
          timer provides more intra-tick resolution than the 32KHz timer,
@@ -123,6 +157,7 @@ config OMAP_MPU_TIMER
 config OMAP_32K_TIMER
        bool "Use 32KHz timer"
        depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS
+        default y if (ARCH_OMAP16XX || ARCH_OMAP2PLUS)
        help
          Select this option if you want to enable the OMAP 32KHz timer.
          This timer saves power compared to the OMAP_MPU_TIMER, and has
@@ -130,8 +165,6 @@ config OMAP_32K_TIMER
          intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
          currently only available for OMAP16XX, 24XX, 34XX and OMAP4.
-endchoice
 config OMAP3_L2_AUX_SECURE_SAVE_RESTORE
        bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
        depends on ARCH_OMAP3 && PM
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 9405831b746a..f0233e6abcdf 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -3,8 +3,8 @@
 #
 # Common support
-obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \
+obj-y := common.o sram.o clock.o devices.o dma.o mux.o \
-         usb.o fb.o io.o
+         usb.o fb.o io.o counter_32k.o
 obj-m :=
 obj-n :=
 obj-  :=
@@ -31,4 +31,4 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y)
 # OMAP mailbox framework
 obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o
-obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
-\ No newline at end of file
+obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 7190cbd92620..c9122dd6ee8d 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -37,14 +37,16 @@ static struct clk_functions *arch_clock;
 int clk_enable(struct clk *clk)
 {
        unsigned long flags;
-        int ret = 0;
+        int ret;
        if (clk == NULL || IS_ERR(clk))
                return -EINVAL;
+        if (!arch_clock || !arch_clock->clk_enable)
+                return -EINVAL;
        spin_lock_irqsave(&clockfw_lock, flags);
-        if (arch_clock->clk_enable)
+        ret = arch_clock->clk_enable(clk);
-                ret = arch_clock->clk_enable(clk);
        spin_unlock_irqrestore(&clockfw_lock, flags);
        return ret;
@@ -58,16 +60,18 @@ void clk_disable(struct clk *clk)
        if (clk == NULL || IS_ERR(clk))
                return;
+        if (!arch_clock || !arch_clock->clk_disable)
+                return;
        spin_lock_irqsave(&clockfw_lock, flags);
        if (clk->usecount == 0) {
-                printk(KERN_ERR "Trying disable clock %s with 0 usecount\n",
+                pr_err("Trying disable clock %s with 0 usecount\n",
                       clk->name);
                WARN_ON(1);
                goto out;
        }
-        if (arch_clock->clk_disable)
+        arch_clock->clk_disable(clk);
-                arch_clock->clk_disable(clk);
 out:
        spin_unlock_irqrestore(&clockfw_lock, flags);
@@ -77,7 +81,7 @@ EXPORT_SYMBOL(clk_disable);
 unsigned long clk_get_rate(struct clk *clk)
 {
        unsigned long flags;
-        unsigned long ret = 0;
+        unsigned long ret;
        if (clk == NULL || IS_ERR(clk))
                return 0;
@@ -97,14 +101,16 @@ EXPORT_SYMBOL(clk_get_rate);
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
        unsigned long flags;
-        long ret = 0;
+        long ret;
        if (clk == NULL || IS_ERR(clk))
-                return ret;
+                return 0;
+        if (!arch_clock || !arch_clock->clk_round_rate)
+                return 0;
        spin_lock_irqsave(&clockfw_lock, flags);
-        if (arch_clock->clk_round_rate)
+        ret = arch_clock->clk_round_rate(clk, rate);
-                ret = arch_clock->clk_round_rate(clk, rate);
        spin_unlock_irqrestore(&clockfw_lock, flags);
        return ret;
@@ -119,14 +125,13 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
        if (clk == NULL || IS_ERR(clk))
                return ret;
+        if (!arch_clock || !arch_clock->clk_set_rate)
+                return ret;
        spin_lock_irqsave(&clockfw_lock, flags);
-        if (arch_clock->clk_set_rate)
+        ret = arch_clock->clk_set_rate(clk, rate);
-                ret = arch_clock->clk_set_rate(clk, rate);
+        if (ret == 0)
-        if (ret == 0) {
-                if (clk->recalc)
-                        clk->rate = clk->recalc(clk);
                propagate_rate(clk);
-        }
        spin_unlock_irqrestore(&clockfw_lock, flags);
        return ret;
@@ -141,15 +146,14 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
        if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
                return ret;
+        if (!arch_clock || !arch_clock->clk_set_parent)
+                return ret;
        spin_lock_irqsave(&clockfw_lock, flags);
        if (clk->usecount == 0) {
-                if (arch_clock->clk_set_parent)
+                ret = arch_clock->clk_set_parent(clk, parent);
-                        ret = arch_clock->clk_set_parent(clk, parent);
+                if (ret == 0)
-                if (ret == 0) {
-                        if (clk->recalc)
-                                clk->rate = clk->recalc(clk);
                        propagate_rate(clk);
-                }
        } else
                ret = -EBUSY;
        spin_unlock_irqrestore(&clockfw_lock, flags);
@@ -335,6 +339,38 @@ struct clk *omap_clk_get_by_name(const char *name)
        return ret;
 }
+int omap_clk_enable_autoidle_all(void)
+{
+        struct clk *c;
+        unsigned long flags;
+        spin_lock_irqsave(&clockfw_lock, flags);
+        list_for_each_entry(c, &clocks, node)
+                if (c->ops->allow_idle)
+                        c->ops->allow_idle(c);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+        return 0;
+}
+int omap_clk_disable_autoidle_all(void)
+{
+        struct clk *c;
+        unsigned long flags;
+        spin_lock_irqsave(&clockfw_lock, flags);
+        list_for_each_entry(c, &clocks, node)
+                if (c->ops->deny_idle)
+                        c->ops->deny_idle(c);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+        return 0;
+}
 /*
 * Low level helpers
 */
@@ -367,9 +403,11 @@ void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
 {
        unsigned long flags;
+        if (!arch_clock || !arch_clock->clk_init_cpufreq_table)
+                return;
        spin_lock_irqsave(&clockfw_lock, flags);
-        if (arch_clock->clk_init_cpufreq_table)
+        arch_clock->clk_init_cpufreq_table(table);
-                arch_clock->clk_init_cpufreq_table(table);
        spin_unlock_irqrestore(&clockfw_lock, flags);
 }
@@ -377,9 +415,11 @@ void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
 {
        unsigned long flags;
+        if (!arch_clock || !arch_clock->clk_exit_cpufreq_table)
+                return;
        spin_lock_irqsave(&clockfw_lock, flags);
-        if (arch_clock->clk_exit_cpufreq_table)
+        arch_clock->clk_exit_cpufreq_table(table);
-                arch_clock->clk_exit_cpufreq_table(table);
        spin_unlock_irqrestore(&clockfw_lock, flags);
 }
 #endif
@@ -397,6 +437,10 @@ static int __init clk_disable_unused(void)
        struct clk *ck;
        unsigned long flags;
+        if (!arch_clock || !arch_clock->clk_disable_unused)
+                return 0;
+        pr_info("clock: disabling unused clocks to save power\n");
        list_for_each_entry(ck, &clocks, node) {
                if (ck->ops == &clkops_null)
                        continue;
@@ -405,20 +449,20 @@ static int __init clk_disable_unused(void)
                        continue;
                spin_lock_irqsave(&clockfw_lock, flags);
-                if (arch_clock->clk_disable_unused)
+                arch_clock->clk_disable_unused(ck);
-                        arch_clock->clk_disable_unused(ck);
                spin_unlock_irqrestore(&clockfw_lock, flags);
        }
        return 0;
 }
 late_initcall(clk_disable_unused);
+late_initcall(omap_clk_enable_autoidle_all);
 #endif
 int __init clk_init(struct clk_functions * custom_clocks)
 {
        if (!custom_clocks) {
-                printk(KERN_ERR "No custom clock functions registered\n");
+                pr_err("No custom clock functions registered\n");
                BUG();
        }
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 3008e7104487..d9f10a31e604 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -11,45 +11,24 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-#include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/console.h>
-#include <linux/serial.h>
-#include <linux/tty.h>
-#include <linux/serial_8250.h>
-#include <linux/serial_reg.h>
-#include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/omapfb.h>
-#include <mach/hardware.h>
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-#include <asm/setup.h>
 #include <plat/common.h>
 #include <plat/board.h>
-#include <plat/control.h>
-#include <plat/mux.h>
-#include <plat/fpga.h>
-#include <plat/serial.h>
 #include <plat/vram.h>
+#include <plat/dsp.h>
-#include <plat/clock.h>
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-# include "../mach-omap2/sdrc.h"
-#endif
 #define NO_LENGTH_CHECK 0xffffffff
-struct omap_board_config_kernel *omap_board_config;
+struct omap_board_config_kernel *omap_board_config __initdata;
 int omap_board_config_size;
-static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
+static const void *__init get_config(u16 tag, size_t len,
+                int skip, size_t *len_out)
 {
        struct omap_board_config_kernel *kinfo = NULL;
        int i;
@@ -71,287 +50,19 @@ static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out)
        return kinfo->data;
 }
-const void *__omap_get_config(u16 tag, size_t len, int nr)
+const void *__init __omap_get_config(u16 tag, size_t len, int nr)
 {
        return get_config(tag, len, nr, NULL);
 }
-EXPORT_SYMBOL(__omap_get_config);
-const void *omap_get_var_config(u16 tag, size_t *len)
+const void *__init omap_get_var_config(u16 tag, size_t *len)
 {
        return get_config(tag, NO_LENGTH_CHECK, 0, len);
 }
-EXPORT_SYMBOL(omap_get_var_config);
 void __init omap_reserve(void)
 {
        omapfb_reserve_sdram_memblock();
        omap_vram_reserve_sdram_memblock();
+        omap_dsp_reserve_sdram_memblock();
 }
-/*
- * 32KHz clocksource ... always available, on pretty most chips except
- * OMAP 730 and 1510.  Other timers could be used as clocksources, with
- * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
- * but systems won't necessarily want to spend resources that way.
- */
-#define OMAP16XX_TIMER_32K_SYNCHRONIZED         0xfffbc410
-#if !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX))
-#include <linux/clocksource.h>
-/*
- * offset_32k holds the init time counter value. It is then subtracted
- * from every counter read to achieve a counter that counts time from the
- * kernel boot (needed for sched_clock()).
- */
-static u32 offset_32k __read_mostly;
-#ifdef CONFIG_ARCH_OMAP16XX
-static cycle_t omap16xx_32k_read(struct clocksource *cs)
-{
-        return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k;
-}
-#else
-#define omap16xx_32k_read       NULL
-#endif
-#ifdef CONFIG_ARCH_OMAP2420
-static cycle_t omap2420_32k_read(struct clocksource *cs)
-{
-        return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k;
-}
-#else
-#define omap2420_32k_read       NULL
-#endif
-#ifdef CONFIG_ARCH_OMAP2430
-static cycle_t omap2430_32k_read(struct clocksource *cs)
-{
-        return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k;
-}
-#else
-#define omap2430_32k_read       NULL
-#endif
-#ifdef CONFIG_ARCH_OMAP3
-static cycle_t omap34xx_32k_read(struct clocksource *cs)
-{
-        return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k;
-}
-#else
-#define omap34xx_32k_read       NULL
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-static cycle_t omap44xx_32k_read(struct clocksource *cs)
-{
-        return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k;
-}
-#else
-#define omap44xx_32k_read       NULL
-#endif
-/*
- * Kernel assumes that sched_clock can be called early but may not have
- * things ready yet.
- */
-static cycle_t omap_32k_read_dummy(struct clocksource *cs)
-{
-        return 0;
-}
-static struct clocksource clocksource_32k = {
-        .name           = "32k_counter",
-        .rating         = 250,
-        .read           = omap_32k_read_dummy,
-        .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 10,
-        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-/*
- * Returns current time from boot in nsecs. It's OK for this to wrap
- * around for now, as it's just a relative time stamp.
- */
-unsigned long long sched_clock(void)
-{
-        return clocksource_cyc2ns(clocksource_32k.read(&clocksource_32k),
-                                  clocksource_32k.mult, clocksource_32k.shift);
-}
-/**
- * read_persistent_clock -  Return time from a persistent clock.
- *
- * Reads the time from a source which isn't disabled during PM, the
- * 32k sync timer.  Convert the cycles elapsed since last read into
- * nsecs and adds to a monotonically increasing timespec.
- */
-static struct timespec persistent_ts;
-static cycles_t cycles, last_cycles;
-void read_persistent_clock(struct timespec *ts)
-{
-        unsigned long long nsecs;
-        cycles_t delta;
-        struct timespec *tsp = &persistent_ts;
-        last_cycles = cycles;
-        cycles = clocksource_32k.read(&clocksource_32k);
-        delta = cycles - last_cycles;
-        nsecs = clocksource_cyc2ns(delta,
-                                   clocksource_32k.mult, clocksource_32k.shift);
-        timespec_add_ns(tsp, nsecs);
-        *ts = *tsp;
-}
-static int __init omap_init_clocksource_32k(void)
-{
-        static char err[] __initdata = KERN_ERR
-                        "%s: can't register clocksource!\n";
-        if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
-                struct clk *sync_32k_ick;
-                if (cpu_is_omap16xx())
-                        clocksource_32k.read = omap16xx_32k_read;
-                else if (cpu_is_omap2420())
-                        clocksource_32k.read = omap2420_32k_read;
-                else if (cpu_is_omap2430())
-                        clocksource_32k.read = omap2430_32k_read;
-                else if (cpu_is_omap34xx())
-                        clocksource_32k.read = omap34xx_32k_read;
-                else if (cpu_is_omap44xx())
-                        clocksource_32k.read = omap44xx_32k_read;
-                else
-                        return -ENODEV;
-                sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
-                if (sync_32k_ick)
-                        clk_enable(sync_32k_ick);
-                clocksource_32k.mult = clocksource_hz2mult(32768,
-                                            clocksource_32k.shift);
-                offset_32k = clocksource_32k.read(&clocksource_32k);
-                if (clocksource_register(&clocksource_32k))
-                        printk(err, clocksource_32k.name);
-        }
-        return 0;
-}
-arch_initcall(omap_init_clocksource_32k);
-#endif  /* !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) */
-/* Global address base setup code */
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
-{
-        omap2_set_globals_tap(omap2_globals);
-        omap2_set_globals_sdrc(omap2_globals);
-        omap2_set_globals_control(omap2_globals);
-        omap2_set_globals_prcm(omap2_globals);
-        omap2_set_globals_uart(omap2_globals);
-}
-#endif
-#if defined(CONFIG_ARCH_OMAP2420)
-static struct omap_globals omap242x_globals = {
-        .class  = OMAP242X_CLASS,
-        .tap    = OMAP2_L4_IO_ADDRESS(0x48014000),
-        .sdrc   = OMAP2420_SDRC_BASE,
-        .sms    = OMAP2420_SMS_BASE,
-        .ctrl   = OMAP2420_CTRL_BASE,
-        .prm    = OMAP2420_PRM_BASE,
-        .cm     = OMAP2420_CM_BASE,
-        .uart1_phys     = OMAP2_UART1_BASE,
-        .uart2_phys     = OMAP2_UART2_BASE,
-        .uart3_phys     = OMAP2_UART3_BASE,
-};
-void __init omap2_set_globals_242x(void)
-{
-        __omap2_set_globals(&omap242x_globals);
-}
-#endif
-#if defined(CONFIG_ARCH_OMAP2430)
-static struct omap_globals omap243x_globals = {
-        .class  = OMAP243X_CLASS,
-        .tap    = OMAP2_L4_IO_ADDRESS(0x4900a000),
-        .sdrc   = OMAP243X_SDRC_BASE,
-        .sms    = OMAP243X_SMS_BASE,
-        .ctrl   = OMAP243X_CTRL_BASE,
-        .prm    = OMAP2430_PRM_BASE,
-        .cm     = OMAP2430_CM_BASE,
-        .uart1_phys     = OMAP2_UART1_BASE,
-        .uart2_phys     = OMAP2_UART2_BASE,
-        .uart3_phys     = OMAP2_UART3_BASE,
-};
-void __init omap2_set_globals_243x(void)
-{
-        __omap2_set_globals(&omap243x_globals);
-}
-#endif
-#if defined(CONFIG_ARCH_OMAP3)
-static struct omap_globals omap3_globals = {
-        .class  = OMAP343X_CLASS,
-        .tap    = OMAP2_L4_IO_ADDRESS(0x4830A000),
-        .sdrc   = OMAP343X_SDRC_BASE,
-        .sms    = OMAP343X_SMS_BASE,
-        .ctrl   = OMAP343X_CTRL_BASE,
-        .prm    = OMAP3430_PRM_BASE,
-        .cm     = OMAP3430_CM_BASE,
-        .uart1_phys     = OMAP3_UART1_BASE,
-        .uart2_phys     = OMAP3_UART2_BASE,
-        .uart3_phys     = OMAP3_UART3_BASE,
-        .uart4_phys     = OMAP3_UART4_BASE,     /* Only on 3630 */
-};
-void __init omap2_set_globals_3xxx(void)
-{
-        __omap2_set_globals(&omap3_globals);
-}
-void __init omap3_map_io(void)
-{
-        omap2_set_globals_3xxx();
-        omap34xx_map_common_io();
-}
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
-static struct omap_globals omap4_globals = {
-        .class  = OMAP443X_CLASS,
-        .tap    = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
-        .ctrl   = OMAP443X_CTRL_BASE,
-        .prm    = OMAP4430_PRM_BASE,
-        .cm     = OMAP4430_CM_BASE,
-        .cm2    = OMAP4430_CM2_BASE,
-        .uart1_phys     = OMAP4_UART1_BASE,
-        .uart2_phys     = OMAP4_UART2_BASE,
-        .uart3_phys     = OMAP4_UART3_BASE,
-        .uart4_phys     = OMAP4_UART4_BASE,
-};
-void __init omap2_set_globals_443x(void)
-{
-        omap2_set_globals_tap(&omap4_globals);
-        omap2_set_globals_control(&omap4_globals);
-        omap2_set_globals_prcm(&omap4_globals);
-        omap2_set_globals_uart(&omap4_globals);
-}
-#endif
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
new file mode 100644
index 000000000000..f7fed6080190
--- /dev/null
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -0,0 +1,207 @@
+/*
+ * OMAP 32ksynctimer/counter_32k-related code
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Copyright (C) 2010 Nokia Corporation
+ * Tony Lindgren <tony@atomide.com>
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * NOTE: This timer is not the same timer as the old OMAP1 MPU timer.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sched.h>
+#include <asm/sched_clock.h>
+#include <plat/common.h>
+#include <plat/board.h>
+#include <plat/clock.h>
+/*
+ * 32KHz clocksource ... always available, on pretty most chips except
+ * OMAP 730 and 1510.  Other timers could be used as clocksources, with
+ * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
+ * but systems won't necessarily want to spend resources that way.
+ */
+#define OMAP16XX_TIMER_32K_SYNCHRONIZED         0xfffbc410
+#include <linux/clocksource.h>
+/*
+ * offset_32k holds the init time counter value. It is then subtracted
+ * from every counter read to achieve a counter that counts time from the
+ * kernel boot (needed for sched_clock()).
+ */
+static u32 offset_32k __read_mostly;
+#ifdef CONFIG_ARCH_OMAP16XX
+static cycle_t notrace omap16xx_32k_read(struct clocksource *cs)
+{
+        return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k;
+}
+#else
+#define omap16xx_32k_read       NULL
+#endif
+#ifdef CONFIG_SOC_OMAP2420
+static cycle_t notrace omap2420_32k_read(struct clocksource *cs)
+{
+        return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k;
+}
+#else
+#define omap2420_32k_read       NULL
+#endif
+#ifdef CONFIG_SOC_OMAP2430
+static cycle_t notrace omap2430_32k_read(struct clocksource *cs)
+{
+        return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k;
+}
+#else
+#define omap2430_32k_read       NULL
+#endif
+#ifdef CONFIG_ARCH_OMAP3
+static cycle_t notrace omap34xx_32k_read(struct clocksource *cs)
+{
+        return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k;
+}
+#else
+#define omap34xx_32k_read       NULL
+#endif
+#ifdef CONFIG_ARCH_OMAP4
+static cycle_t notrace omap44xx_32k_read(struct clocksource *cs)
+{
+        return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k;
+}
+#else
+#define omap44xx_32k_read       NULL
+#endif
+/*
+ * Kernel assumes that sched_clock can be called early but may not have
+ * things ready yet.
+ */
+static cycle_t notrace omap_32k_read_dummy(struct clocksource *cs)
+{
+        return 0;
+}
+static struct clocksource clocksource_32k = {
+        .name           = "32k_counter",
+        .rating         = 250,
+        .read           = omap_32k_read_dummy,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+/*
+ * Returns current time from boot in nsecs. It's OK for this to wrap
+ * around for now, as it's just a relative time stamp.
+ */
+static DEFINE_CLOCK_DATA(cd);
+/*
+ * Constants generated by clocks_calc_mult_shift(m, s, 32768, NSEC_PER_SEC, 60).
+ * This gives a resolution of about 30us and a wrap period of about 36hrs.
+ */
+#define SC_MULT         4000000000u
+#define SC_SHIFT        17
+static inline unsigned long long notrace _omap_32k_sched_clock(void)
+{
+        u32 cyc = clocksource_32k.read(&clocksource_32k);
+        return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
+}
+#ifndef CONFIG_OMAP_MPU_TIMER
+unsigned long long notrace sched_clock(void)
+{
+        return _omap_32k_sched_clock();
+}
+#else
+unsigned long long notrace omap_32k_sched_clock(void)
+{
+        return _omap_32k_sched_clock();
+}
+#endif
+static void notrace omap_update_sched_clock(void)
+{
+        u32 cyc = clocksource_32k.read(&clocksource_32k);
+        update_sched_clock(&cd, cyc, (u32)~0);
+}
+/**
+ * read_persistent_clock -  Return time from a persistent clock.
+ *
+ * Reads the time from a source which isn't disabled during PM, the
+ * 32k sync timer.  Convert the cycles elapsed since last read into
+ * nsecs and adds to a monotonically increasing timespec.
+ */
+static struct timespec persistent_ts;
+static cycles_t cycles, last_cycles;
+void read_persistent_clock(struct timespec *ts)
+{
+        unsigned long long nsecs;
+        cycles_t delta;
+        struct timespec *tsp = &persistent_ts;
+        last_cycles = cycles;
+        cycles = clocksource_32k.read(&clocksource_32k);
+        delta = cycles - last_cycles;
+        nsecs = clocksource_cyc2ns(delta,
+                                   clocksource_32k.mult, clocksource_32k.shift);
+        timespec_add_ns(tsp, nsecs);
+        *ts = *tsp;
+}
+int __init omap_init_clocksource_32k(void)
+{
+        static char err[] __initdata = KERN_ERR
+                        "%s: can't register clocksource!\n";
+        if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
+                struct clk *sync_32k_ick;
+                if (cpu_is_omap16xx())
+                        clocksource_32k.read = omap16xx_32k_read;
+                else if (cpu_is_omap2420())
+                        clocksource_32k.read = omap2420_32k_read;
+                else if (cpu_is_omap2430())
+                        clocksource_32k.read = omap2430_32k_read;
+                else if (cpu_is_omap34xx())
+                        clocksource_32k.read = omap34xx_32k_read;
+                else if (cpu_is_omap44xx())
+                        clocksource_32k.read = omap44xx_32k_read;
+                else
+                        return -ENODEV;
+                sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
+                if (!IS_ERR(sync_32k_ick))
+                        clk_enable(sync_32k_ick);
+                offset_32k = clocksource_32k.read(&clocksource_32k);
+                if (clocksource_register_hz(&clocksource_32k, 32768))
+                        printk(err, clocksource_32k.name);
+                init_fixed_sched_clock(&cd, omap_update_sched_clock, 32,
+                                       32768, SC_MULT, SC_SHIFT);
+        }
+        return 0;
+}
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
index 6d3d33360056..da4f68dbba1d 100644
--- a/arch/arm/plat-omap/cpu-omap.c
+++ b/arch/arm/plat-omap/cpu-omap.c
@@ -40,7 +40,7 @@ static struct clk *mpu_clk;
 /* TODO: Add support for SDRAM timing changes */
-int omap_verify_speed(struct cpufreq_policy *policy)
+static int omap_verify_speed(struct cpufreq_policy *policy)
 {
        if (freq_table)
                return cpufreq_frequency_table_verify(policy, freq_table);
@@ -58,7 +58,7 @@ int omap_verify_speed(struct cpufreq_policy *policy)
        return 0;
 }
-unsigned int omap_getspeed(unsigned int cpu)
+static unsigned int omap_getspeed(unsigned int cpu)
 {
        unsigned long rate;
@@ -101,7 +101,7 @@ static int omap_target(struct cpufreq_policy *policy,
        return ret;
 }
-static int __init omap_cpu_init(struct cpufreq_policy *policy)
+static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy)
 {
        int result = 0;
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index d1920be7833b..ea28f98d5d6a 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -15,13 +15,13 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/memblock.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 #include <plat/tc.h>
-#include <plat/control.h>
 #include <plat/board.h>
 #include <plat/mmc.h>
 #include <mach/gpio.h>
@@ -35,8 +35,8 @@
 static struct platform_device **omap_mcbsp_devices;
-void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
+void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
-                                        int size)
+                        struct omap_mcbsp_platform_data *config, int size)
 {
        int i;
@@ -54,6 +54,8 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
                new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1);
                if (!new_mcbsp)
                        continue;
+                platform_device_add_resources(new_mcbsp, &res[i * res_count],
+                                        res_count);
                new_mcbsp->dev.platform_data = &config[i];
                ret = platform_device_add(new_mcbsp);
                if (ret) {
@@ -65,8 +67,8 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
 }
 #else
-void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
+void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
-                                        int size)
+                        struct omap_mcbsp_platform_data *config, int size)
 {  }
 #endif
@@ -232,44 +234,35 @@ static void omap_init_uwire(void)
 static inline void omap_init_uwire(void) {}
 #endif
-/*-------------------------------------------------------------------------*/
+#if defined(CONFIG_TIDSPBRIDGE) || defined(CONFIG_TIDSPBRIDGE_MODULE)
-#if     defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
+static phys_addr_t omap_dsp_phys_mempool_base;
-static struct resource wdt_resources[] = {
+void __init omap_dsp_reserve_sdram_memblock(void)
-        {
+{
-                .flags          = IORESOURCE_MEM,
+        phys_addr_t size = CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE;
-        },
+        phys_addr_t paddr;
-};
-static struct platform_device omap_wdt_device = {
+        if (!size)
-        .name      = "omap_wdt",
+                return;
-        .id          = -1,
-        .num_resources  = ARRAY_SIZE(wdt_resources),
-        .resource       = wdt_resources,
-};
-static void omap_init_wdt(void)
+        paddr = memblock_alloc(size, SZ_1M);
-{
+        if (!paddr) {
-        if (cpu_is_omap16xx())
+                pr_err("%s: failed to reserve %x bytes\n",
-                wdt_resources[0].start = 0xfffeb000;
+                                __func__, size);
-        else if (cpu_is_omap2420())
-                wdt_resources[0].start = 0x48022000; /* WDT2 */
-        else if (cpu_is_omap2430())
-                wdt_resources[0].start = 0x49016000; /* WDT2 */
-        else if (cpu_is_omap343x())
-                wdt_resources[0].start = 0x48314000; /* WDT2 */
-        else if (cpu_is_omap44xx())
-                wdt_resources[0].start = 0x4a314000;
-        else
                return;
+        }
+        memblock_free(paddr, size);
+        memblock_remove(paddr, size);
-        wdt_resources[0].end = wdt_resources[0].start + 0x4f;
+        omap_dsp_phys_mempool_base = paddr;
+}
-        (void) platform_device_register(&omap_wdt_device);
+phys_addr_t omap_dsp_get_mempool_base(void)
+{
+        return omap_dsp_phys_mempool_base;
 }
-#else
+EXPORT_SYMBOL(omap_dsp_get_mempool_base);
-static inline void omap_init_wdt(void) {}
 #endif
 /*
@@ -287,7 +280,7 @@ static inline void omap_init_wdt(void) {}
 * Claiming GPIOs, and setting their direction and initial values, is the
 * responsibility of the device drivers.  So is responding to probe().
 *
- * Board-specific knowlege like creating devices or pin setup is to be
+ * Board-specific knowledge like creating devices or pin setup is to be
 * kept out of drivers as much as possible.  In particular, pin setup
 * may be handled by the boot loader, and drivers should expect it will
 * normally have been done by the time they're probed.
@@ -300,7 +293,6 @@ static int __init omap_init_devices(void)
        omap_init_rng();
        omap_init_mcpdm();
        omap_init_uwire();
-        omap_init_wdt();
        return 0;
 }
 arch_initcall(omap_init_devices);
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index ec7eddf9e525..c22217c2ee5f 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -15,6 +15,10 @@
 *
 * Support functions for the OMAP internal DMA channels.
 *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Converted DMA library into DMA platform driver.
+ *      - G, Manjunath Kondaiah <manjugk@ti.com>
+ *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
@@ -30,6 +34,7 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/delay.h>
 #include <asm/system.h>
 #include <mach/hardware.h>
@@ -48,11 +53,15 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
 #endif
 #define OMAP_DMA_ACTIVE                 0x01
-#define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
+#define OMAP2_DMA_CSR_CLEAR_MASK        0xffffffff
 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
+static struct omap_system_dma_plat_info *p;
+static struct omap_dma_dev_attr *d;
 static int enable_1510_mode;
+static u32 errata;
 static struct omap_dma_global_context_registers {
        u32 dma_irqenable_l0;
@@ -60,27 +69,6 @@ static struct omap_dma_global_context_registers {
        u32 dma_gcr;
 } omap_dma_global_context;
-struct omap_dma_lch {
-        int next_lch;
-        int dev_id;
-        u16 saved_csr;
-        u16 enabled_irqs;
-        const char *dev_name;
-        void (*callback)(int lch, u16 ch_status, void *data);
-        void *data;
-#ifndef CONFIG_ARCH_OMAP1
-        /* required for Dynamic chaining */
-        int prev_linked_ch;
-        int next_linked_ch;
-        int state;
-        int chain_id;
-        int status;
-#endif
-        long flags;
-};
 struct dma_link_info {
        int *linked_dmach_q;
        int no_of_lchs_linked;
@@ -136,15 +124,6 @@ static int omap_dma_reserve_channels;
 static spinlock_t dma_chan_lock;
 static struct omap_dma_lch *dma_chan;
-static void __iomem *omap_dma_base;
-static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
-        INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
-        INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
-        INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
-        INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
-        INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
-};
 static inline void disable_lnk(int lch);
 static void omap_disable_channel_irq(int lch);
@@ -153,27 +132,9 @@ static inline void omap_enable_channel_irq(int lch);
 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
                                                __func__);
-#define dma_read(reg)                                                   \
-({                                                                      \
-        u32 __val;                                                      \
-        if (cpu_class_is_omap1())                                       \
-                __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg);   \
-        else                                                            \
-                __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg);   \
-        __val;                                                          \
-})
-#define dma_write(val, reg)                                             \
-({                                                                      \
-        if (cpu_class_is_omap1())                                       \
-                __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
-        else                                                            \
-                __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg);   \
-})
 #ifdef CONFIG_ARCH_OMAP15XX
 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
-int omap_dma_in_1510_mode(void)
+static int omap_dma_in_1510_mode(void)
 {
        return enable_1510_mode;
 }
@@ -205,16 +166,6 @@ static inline void set_gdma_dev(int req, int dev)
 #define set_gdma_dev(req, dev)  do {} while (0)
 #endif
-/* Omap1 only */
-static void clear_lch_regs(int lch)
-{
-        int i;
-        void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
-        for (i = 0; i < 0x2c; i += 2)
-                __raw_writew(0, lch_base + i);
-}
 void omap_set_dma_priority(int lch, int dst_port, int priority)
 {
        unsigned long reg;
@@ -247,12 +198,12 @@ void omap_set_dma_priority(int lch, int dst_port, int priority)
        if (cpu_class_is_omap2()) {
                u32 ccr;
-                ccr = dma_read(CCR(lch));
+                ccr = p->dma_read(CCR, lch);
                if (priority)
                        ccr |= (1 << 6);
                else
                        ccr &= ~(1 << 6);
-                dma_write(ccr, CCR(lch));
+                p->dma_write(ccr, CCR, lch);
        }
 }
 EXPORT_SYMBOL(omap_set_dma_priority);
@@ -263,31 +214,31 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 {
        u32 l;
-        l = dma_read(CSDP(lch));
+        l = p->dma_read(CSDP, lch);
        l &= ~0x03;
        l |= data_type;
-        dma_write(l, CSDP(lch));
+        p->dma_write(l, CSDP, lch);
        if (cpu_class_is_omap1()) {
                u16 ccr;
-                ccr = dma_read(CCR(lch));
+                ccr = p->dma_read(CCR, lch);
                ccr &= ~(1 << 5);
                if (sync_mode == OMAP_DMA_SYNC_FRAME)
                        ccr |= 1 << 5;
-                dma_write(ccr, CCR(lch));
+                p->dma_write(ccr, CCR, lch);
-                ccr = dma_read(CCR2(lch));
+                ccr = p->dma_read(CCR2, lch);
                ccr &= ~(1 << 2);
                if (sync_mode == OMAP_DMA_SYNC_BLOCK)
                        ccr |= 1 << 2;
-                dma_write(ccr, CCR2(lch));
+                p->dma_write(ccr, CCR2, lch);
        }
        if (cpu_class_is_omap2() && dma_trigger) {
                u32 val;
-                val = dma_read(CCR(lch));
+                val = p->dma_read(CCR, lch);
                /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
                val &= ~((1 << 23) | (3 << 19) | 0x1f);
@@ -312,11 +263,11 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
                } else {
                        val &= ~(1 << 24);      /* dest synch */
                }
-                dma_write(val, CCR(lch));
+                p->dma_write(val, CCR, lch);
        }
-        dma_write(elem_count, CEN(lch));
+        p->dma_write(elem_count, CEN, lch);
-        dma_write(frame_count, CFN(lch));
+        p->dma_write(frame_count, CFN, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_transfer_params);
@@ -327,7 +278,7 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
        if (cpu_class_is_omap1()) {
                u16 w;
-                w = dma_read(CCR2(lch));
+                w = p->dma_read(CCR2, lch);
                w &= ~0x03;
                switch (mode) {
@@ -342,23 +293,22 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
                default:
                        BUG();
                }
-                dma_write(w, CCR2(lch));
+                p->dma_write(w, CCR2, lch);
-                w = dma_read(LCH_CTRL(lch));
+                w = p->dma_read(LCH_CTRL, lch);
                w &= ~0x0f;
                /* Default is channel type 2D */
                if (mode) {
-                        dma_write((u16)color, COLOR_L(lch));
+                        p->dma_write(color, COLOR, lch);
-                        dma_write((u16)(color >> 16), COLOR_U(lch));
                        w |= 1;         /* Channel type G */
                }
-                dma_write(w, LCH_CTRL(lch));
+                p->dma_write(w, LCH_CTRL, lch);
        }
        if (cpu_class_is_omap2()) {
                u32 val;
-                val = dma_read(CCR(lch));
+                val = p->dma_read(CCR, lch);
                val &= ~((1 << 17) | (1 << 16));
                switch (mode) {
@@ -373,10 +323,10 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
                default:
                        BUG();
                }
-                dma_write(val, CCR(lch));
+                p->dma_write(val, CCR, lch);
                color &= 0xffffff;
-                dma_write(color, COLOR(lch));
+                p->dma_write(color, COLOR, lch);
        }
 }
 EXPORT_SYMBOL(omap_set_dma_color_mode);
@@ -386,10 +336,10 @@ void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
        if (cpu_class_is_omap2()) {
                u32 csdp;
-                csdp = dma_read(CSDP(lch));
+                csdp = p->dma_read(CSDP, lch);
                csdp &= ~(0x3 << 16);
                csdp |= (mode << 16);
-                dma_write(csdp, CSDP(lch));
+                p->dma_write(csdp, CSDP, lch);
        }
 }
 EXPORT_SYMBOL(omap_set_dma_write_mode);
@@ -399,10 +349,10 @@ void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
        if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
                u32 l;
-                l = dma_read(LCH_CTRL(lch));
+                l = p->dma_read(LCH_CTRL, lch);
                l &= ~0x7;
                l |= mode;
-                dma_write(l, LCH_CTRL(lch));
+                p->dma_write(l, LCH_CTRL, lch);
        }
 }
 EXPORT_SYMBOL(omap_set_dma_channel_mode);
@@ -417,27 +367,21 @@ void omap_set_dma_src_params(int lch, int src_port, int src_amode,
        if (cpu_class_is_omap1()) {
                u16 w;
-                w = dma_read(CSDP(lch));
+                w = p->dma_read(CSDP, lch);
                w &= ~(0x1f << 2);
                w |= src_port << 2;
-                dma_write(w, CSDP(lch));
+                p->dma_write(w, CSDP, lch);
        }
-        l = dma_read(CCR(lch));
+        l = p->dma_read(CCR, lch);
        l &= ~(0x03 << 12);
        l |= src_amode << 12;
-        dma_write(l, CCR(lch));
+        p->dma_write(l, CCR, lch);
-        if (cpu_class_is_omap1()) {
+        p->dma_write(src_start, CSSA, lch);
-                dma_write(src_start >> 16, CSSA_U(lch));
-                dma_write((u16)src_start, CSSA_L(lch));
-        }
-        if (cpu_class_is_omap2())
+        p->dma_write(src_ei, CSEI, lch);
-                dma_write(src_start, CSSA(lch));
+        p->dma_write(src_fi, CSFI, lch);
-        dma_write(src_ei, CSEI(lch));
-        dma_write(src_fi, CSFI(lch));
 }
 EXPORT_SYMBOL(omap_set_dma_src_params);
@@ -465,8 +409,8 @@ void omap_set_dma_src_index(int lch, int eidx, int fidx)
        if (cpu_class_is_omap2())
                return;
-        dma_write(eidx, CSEI(lch));
+        p->dma_write(eidx, CSEI, lch);
-        dma_write(fidx, CSFI(lch));
+        p->dma_write(fidx, CSFI, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_src_index);
@@ -474,11 +418,11 @@ void omap_set_dma_src_data_pack(int lch, int enable)
 {
        u32 l;
-        l = dma_read(CSDP(lch));
+        l = p->dma_read(CSDP, lch);
        l &= ~(1 << 6);
        if (enable)
                l |= (1 << 6);
-        dma_write(l, CSDP(lch));
+        p->dma_write(l, CSDP, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
@@ -487,7 +431,7 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
        unsigned int burst = 0;
        u32 l;
-        l = dma_read(CSDP(lch));
+        l = p->dma_read(CSDP, lch);
        l &= ~(0x03 << 7);
        switch (burst_mode) {
@@ -523,7 +467,7 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
        }
        l |= (burst << 7);
-        dma_write(l, CSDP(lch));
+        p->dma_write(l, CSDP, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
@@ -535,27 +479,21 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
        u32 l;
        if (cpu_class_is_omap1()) {
-                l = dma_read(CSDP(lch));
+                l = p->dma_read(CSDP, lch);
                l &= ~(0x1f << 9);
                l |= dest_port << 9;
-                dma_write(l, CSDP(lch));
+                p->dma_write(l, CSDP, lch);
        }
-        l = dma_read(CCR(lch));
+        l = p->dma_read(CCR, lch);
        l &= ~(0x03 << 14);
        l |= dest_amode << 14;
-        dma_write(l, CCR(lch));
+        p->dma_write(l, CCR, lch);
-        if (cpu_class_is_omap1()) {
+        p->dma_write(dest_start, CDSA, lch);
-                dma_write(dest_start >> 16, CDSA_U(lch));
-                dma_write(dest_start, CDSA_L(lch));
-        }
-        if (cpu_class_is_omap2())
-                dma_write(dest_start, CDSA(lch));
-        dma_write(dst_ei, CDEI(lch));
+        p->dma_write(dst_ei, CDEI, lch);
-        dma_write(dst_fi, CDFI(lch));
+        p->dma_write(dst_fi, CDFI, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_dest_params);
@@ -564,8 +502,8 @@ void omap_set_dma_dest_index(int lch, int eidx, int fidx)
        if (cpu_class_is_omap2())
                return;
-        dma_write(eidx, CDEI(lch));
+        p->dma_write(eidx, CDEI, lch);
-        dma_write(fidx, CDFI(lch));
+        p->dma_write(fidx, CDFI, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_dest_index);
@@ -573,11 +511,11 @@ void omap_set_dma_dest_data_pack(int lch, int enable)
 {
        u32 l;
-        l = dma_read(CSDP(lch));
+        l = p->dma_read(CSDP, lch);
        l &= ~(1 << 13);
        if (enable)
                l |= 1 << 13;
-        dma_write(l, CSDP(lch));
+        p->dma_write(l, CSDP, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
@@ -586,7 +524,7 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
        unsigned int burst = 0;
        u32 l;
-        l = dma_read(CSDP(lch));
+        l = p->dma_read(CSDP, lch);
        l &= ~(0x03 << 14);
        switch (burst_mode) {
@@ -619,7 +557,7 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
                return;
        }
        l |= (burst << 14);
-        dma_write(l, CSDP(lch));
+        p->dma_write(l, CSDP, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
@@ -629,18 +567,18 @@ static inline void omap_enable_channel_irq(int lch)
        /* Clear CSR */
        if (cpu_class_is_omap1())
-                status = dma_read(CSR(lch));
+                status = p->dma_read(CSR, lch);
        else if (cpu_class_is_omap2())
-                dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
+                p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
        /* Enable some nice interrupts. */
-        dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
+        p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
 }
 static void omap_disable_channel_irq(int lch)
 {
        if (cpu_class_is_omap2())
-                dma_write(0, CICR(lch));
+                p->dma_write(0, CICR, lch);
 }
 void omap_enable_dma_irq(int lch, u16 bits)
@@ -659,7 +597,7 @@ static inline void enable_lnk(int lch)
 {
        u32 l;
-        l = dma_read(CLNK_CTRL(lch));
+        l = p->dma_read(CLNK_CTRL, lch);
        if (cpu_class_is_omap1())
                l &= ~(1 << 14);
@@ -674,18 +612,18 @@ static inline void enable_lnk(int lch)
                        l = dma_chan[lch].next_linked_ch | (1 << 15);
 #endif
-        dma_write(l, CLNK_CTRL(lch));
+        p->dma_write(l, CLNK_CTRL, lch);
 }
 static inline void disable_lnk(int lch)
 {
        u32 l;
-        l = dma_read(CLNK_CTRL(lch));
+        l = p->dma_read(CLNK_CTRL, lch);
        /* Disable interrupts */
        if (cpu_class_is_omap1()) {
-                dma_write(0, CICR(lch));
+                p->dma_write(0, CICR, lch);
                /* Set the STOP_LNK bit */
                l |= 1 << 14;
        }
@@ -696,7 +634,7 @@ static inline void disable_lnk(int lch)
                l &= ~(1 << 15);
        }
-        dma_write(l, CLNK_CTRL(lch));
+        p->dma_write(l, CLNK_CTRL, lch);
        dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 }
@@ -709,9 +647,9 @@ static inline void omap2_enable_irq_lch(int lch)
                return;
        spin_lock_irqsave(&dma_chan_lock, flags);
-        val = dma_read(IRQENABLE_L0);
+        val = p->dma_read(IRQENABLE_L0, lch);
        val |= 1 << lch;
-        dma_write(val, IRQENABLE_L0);
+        p->dma_write(val, IRQENABLE_L0, lch);
        spin_unlock_irqrestore(&dma_chan_lock, flags);
 }
@@ -724,9 +662,9 @@ static inline void omap2_disable_irq_lch(int lch)
                return;
        spin_lock_irqsave(&dma_chan_lock, flags);
-        val = dma_read(IRQENABLE_L0);
+        val = p->dma_read(IRQENABLE_L0, lch);
        val &= ~(1 << lch);
-        dma_write(val, IRQENABLE_L0);
+        p->dma_write(val, IRQENABLE_L0, lch);
        spin_unlock_irqrestore(&dma_chan_lock, flags);
 }
@@ -753,8 +691,8 @@ int omap_request_dma(int dev_id, const char *dev_name,
        chan = dma_chan + free_ch;
        chan->dev_id = dev_id;
-        if (cpu_class_is_omap1())
+        if (p->clear_lch_regs)
-                clear_lch_regs(free_ch);
+                p->clear_lch_regs(free_ch);
        if (cpu_class_is_omap2())
                omap_clear_dma(free_ch);
@@ -791,17 +729,17 @@ int omap_request_dma(int dev_id, const char *dev_name,
                 * Disable the 1510 compatibility mode and set the sync device
                 * id.
                 */
-                dma_write(dev_id | (1 << 10), CCR(free_ch));
+                p->dma_write(dev_id | (1 << 10), CCR, free_ch);
        } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
-                dma_write(dev_id, CCR(free_ch));
+                p->dma_write(dev_id, CCR, free_ch);
        }
        if (cpu_class_is_omap2()) {
                omap2_enable_irq_lch(free_ch);
                omap_enable_channel_irq(free_ch);
                /* Clear the CSR register and IRQ status register */
-                dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
+                p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch);
-                dma_write(1 << free_ch, IRQSTATUS_L0);
+                p->dma_write(1 << free_ch, IRQSTATUS_L0, 0);
        }
        *dma_ch_out = free_ch;
@@ -822,23 +760,23 @@ void omap_free_dma(int lch)
        if (cpu_class_is_omap1()) {
                /* Disable all DMA interrupts for the channel. */
-                dma_write(0, CICR(lch));
+                p->dma_write(0, CICR, lch);
                /* Make sure the DMA transfer is stopped. */
-                dma_write(0, CCR(lch));
+                p->dma_write(0, CCR, lch);
        }
        if (cpu_class_is_omap2()) {
                omap2_disable_irq_lch(lch);
                /* Clear the CSR register and IRQ status register */
-                dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
+                p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
-                dma_write(1 << lch, IRQSTATUS_L0);
+                p->dma_write(1 << lch, IRQSTATUS_L0, lch);
                /* Disable all DMA interrupts for the channel. */
-                dma_write(0, CICR(lch));
+                p->dma_write(0, CICR, lch);
                /* Make sure the DMA transfer is stopped. */
-                dma_write(0, CCR(lch));
+                p->dma_write(0, CCR, lch);
                omap_clear_dma(lch);
        }
@@ -879,7 +817,7 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
        reg |= (0x3 & tparams) << 12;
        reg |= (arb_rate & 0xff) << 16;
-        dma_write(reg, GCR);
+        p->dma_write(reg, GCR, 0);
 }
 EXPORT_SYMBOL(omap_dma_set_global_params);
@@ -902,14 +840,14 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio,
                printk(KERN_ERR "Invalid channel id\n");
                return -EINVAL;
        }
-        l = dma_read(CCR(lch));
+        l = p->dma_read(CCR, lch);
        l &= ~((1 << 6) | (1 << 26));
        if (cpu_is_omap2430() || cpu_is_omap34xx() ||  cpu_is_omap44xx())
                l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
        else
                l |= ((read_prio & 0x1) << 6);
-        dma_write(l, CCR(lch));
+        p->dma_write(l, CCR, lch);
        return 0;
 }
@@ -924,25 +862,7 @@ void omap_clear_dma(int lch)
        unsigned long flags;
        local_irq_save(flags);
+        p->clear_dma(lch);
-        if (cpu_class_is_omap1()) {
-                u32 l;
-                l = dma_read(CCR(lch));
-                l &= ~OMAP_DMA_CCR_EN;
-                dma_write(l, CCR(lch));
-                /* Clear pending interrupts */
-                l = dma_read(CSR(lch));
-        }
-        if (cpu_class_is_omap2()) {
-                int i;
-                void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
-                for (i = 0; i < 0x44; i += 4)
-                        __raw_writel(0, lch_base + i);
-        }
        local_irq_restore(flags);
 }
 EXPORT_SYMBOL(omap_clear_dma);
@@ -956,13 +876,13 @@ void omap_start_dma(int lch)
         * before starting dma transfer.
         */
        if (cpu_is_omap15xx())
-                dma_write(0, CPC(lch));
+                p->dma_write(0, CPC, lch);
        else
-                dma_write(0, CDAC(lch));
+                p->dma_write(0, CDAC, lch);
        if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
                int next_lch, cur_lch;
-                char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
+                char dma_chan_link_map[dma_lch_count];
                dma_chan_link_map[lch] = 1;
                /* Set the link register of the first channel */
@@ -984,26 +904,18 @@ void omap_start_dma(int lch)
                        cur_lch = next_lch;
                } while (next_lch != -1);
-        } else if (cpu_is_omap242x() ||
+        } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
-                (cpu_is_omap243x() &&  omap_type() <= OMAP2430_REV_ES1_0)) {
+                p->dma_write(lch, CLNK_CTRL, lch);
-                /* Errata: Need to write lch even if not using chaining */
-                dma_write(lch, CLNK_CTRL(lch));
-        }
        omap_enable_channel_irq(lch);
-        l = dma_read(CCR(lch));
+        l = p->dma_read(CCR, lch);
-        /*
-         * Errata: On ES2.0 BUFFERING disable must be set.
-         * This will always fail on ES1.0
-         */
-        if (cpu_is_omap24xx())
-                l |= OMAP_DMA_CCR_EN;
+        if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
+                        l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
        l |= OMAP_DMA_CCR_EN;
-        dma_write(l, CCR(lch));
+        p->dma_write(l, CCR, lch);
        dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 }
@@ -1015,15 +927,46 @@ void omap_stop_dma(int lch)
        /* Disable all interrupts on the channel */
        if (cpu_class_is_omap1())
-                dma_write(0, CICR(lch));
+                p->dma_write(0, CICR, lch);
-        l = dma_read(CCR(lch));
+        l = p->dma_read(CCR, lch);
-        l &= ~OMAP_DMA_CCR_EN;
+        if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
-        dma_write(l, CCR(lch));
+                        (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
+                int i = 0;
+                u32 sys_cf;
+                /* Configure No-Standby */
+                l = p->dma_read(OCP_SYSCONFIG, lch);
+                sys_cf = l;
+                l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
+                l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
+                p->dma_write(l , OCP_SYSCONFIG, 0);
+                l = p->dma_read(CCR, lch);
+                l &= ~OMAP_DMA_CCR_EN;
+                p->dma_write(l, CCR, lch);
+                /* Wait for sDMA FIFO drain */
+                l = p->dma_read(CCR, lch);
+                while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
+                                        OMAP_DMA_CCR_WR_ACTIVE))) {
+                        udelay(5);
+                        i++;
+                        l = p->dma_read(CCR, lch);
+                }
+                if (i >= 100)
+                        printk(KERN_ERR "DMA drain did not complete on "
+                                        "lch %d\n", lch);
+                /* Restore OCP_SYSCONFIG */
+                p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
+        } else {
+                l &= ~OMAP_DMA_CCR_EN;
+                p->dma_write(l, CCR, lch);
+        }
        if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
                int next_lch, cur_lch = lch;
-                char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
+                char dma_chan_link_map[dma_lch_count];
                memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
                do {
@@ -1076,7 +1019,7 @@ EXPORT_SYMBOL(omap_set_dma_callback);
 * If the channel is running the caller must disable interrupts prior calling
 * this function and process the returned value before re-enabling interrupt to
 * prevent races with the interrupt handler. Note that in continuous mode there
- * is a chance for CSSA_L register overflow inbetween the two reads resulting
+ * is a chance for CSSA_L register overflow between the two reads resulting
 * in incorrect return value.
 */
 dma_addr_t omap_get_dma_src_pos(int lch)
@@ -1084,19 +1027,15 @@ dma_addr_t omap_get_dma_src_pos(int lch)
        dma_addr_t offset = 0;
        if (cpu_is_omap15xx())
-                offset = dma_read(CPC(lch));
+                offset = p->dma_read(CPC, lch);
        else
-                offset = dma_read(CSAC(lch));
+                offset = p->dma_read(CSAC, lch);
-        /*
+        if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
-         * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
+                offset = p->dma_read(CSAC, lch);
-         * read before the DMA controller finished disabling the channel.
-         */
-        if (!cpu_is_omap15xx() && offset == 0)
-                offset = dma_read(CSAC(lch));
        if (cpu_class_is_omap1())
-                offset |= (dma_read(CSSA_U(lch)) << 16);
+                offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
        return offset;
 }
@@ -1107,7 +1046,7 @@ EXPORT_SYMBOL(omap_get_dma_src_pos);
 * If the channel is running the caller must disable interrupts prior calling
 * this function and process the returned value before re-enabling interrupt to
 * prevent races with the interrupt handler. Note that in continuous mode there
- * is a chance for CDSA_L register overflow inbetween the two reads resulting
+ * is a chance for CDSA_L register overflow between the two reads resulting
 * in incorrect return value.
 */
 dma_addr_t omap_get_dma_dst_pos(int lch)
@@ -1115,19 +1054,19 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
        dma_addr_t offset = 0;
        if (cpu_is_omap15xx())
-                offset = dma_read(CPC(lch));
+                offset = p->dma_read(CPC, lch);
        else
-                offset = dma_read(CDAC(lch));
+                offset = p->dma_read(CDAC, lch);
        /*
         * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
         * read before the DMA controller finished disabling the channel.
         */
        if (!cpu_is_omap15xx() && offset == 0)
-                offset = dma_read(CDAC(lch));
+                offset = p->dma_read(CDAC, lch);
        if (cpu_class_is_omap1())
-                offset |= (dma_read(CDSA_U(lch)) << 16);
+                offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
        return offset;
 }
@@ -1135,7 +1074,7 @@ EXPORT_SYMBOL(omap_get_dma_dst_pos);
 int omap_get_dma_active_status(int lch)
 {
-        return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
+        return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
 }
 EXPORT_SYMBOL(omap_get_dma_active_status);
@@ -1148,7 +1087,7 @@ int omap_dma_running(void)
                        return 1;
        for (lch = 0; lch < dma_chan_count; lch++)
-                if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
+                if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
                        return 1;
        return 0;
@@ -1163,8 +1102,8 @@ void omap_dma_link_lch(int lch_head, int lch_queue)
 {
        if (omap_dma_in_1510_mode()) {
                if (lch_head == lch_queue) {
-                        dma_write(dma_read(CCR(lch_head)) | (3 << 8),
+                        p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
-                                                                CCR(lch_head));
+                                                                CCR, lch_head);
                        return;
                }
                printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
@@ -1190,8 +1129,8 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue)
 {
        if (omap_dma_in_1510_mode()) {
                if (lch_head == lch_queue) {
-                        dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
+                        p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
-                                                                CCR(lch_head));
+                                                                CCR, lch_head);
                        return;
                }
                printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
@@ -1217,8 +1156,6 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue)
 }
 EXPORT_SYMBOL(omap_dma_unlink_lch);
-/*----------------------------------------------------------------------------*/
 #ifndef CONFIG_ARCH_OMAP1
 /* Create chain of DMA channesls */
 static void create_dma_lch_chain(int lch_head, int lch_queue)
@@ -1243,15 +1180,15 @@ static void create_dma_lch_chain(int lch_head, int lch_queue)
                                        lch_queue;
        }
-        l = dma_read(CLNK_CTRL(lch_head));
+        l = p->dma_read(CLNK_CTRL, lch_head);
        l &= ~(0x1f);
        l |= lch_queue;
-        dma_write(l, CLNK_CTRL(lch_head));
+        p->dma_write(l, CLNK_CTRL, lch_head);
-        l = dma_read(CLNK_CTRL(lch_queue));
+        l = p->dma_read(CLNK_CTRL, lch_queue);
        l &= ~(0x1f);
        l |= (dma_chan[lch_queue].next_linked_ch);
-        dma_write(l, CLNK_CTRL(lch_queue));
+        p->dma_write(l, CLNK_CTRL, lch_queue);
 }
 /**
@@ -1527,13 +1464,13 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
        /* Set the params to the free channel */
        if (src_start != 0)
-                dma_write(src_start, CSSA(lch));
+                p->dma_write(src_start, CSSA, lch);
        if (dest_start != 0)
-                dma_write(dest_start, CDSA(lch));
+                p->dma_write(dest_start, CDSA, lch);
        /* Write the buffer size */
-        dma_write(elem_count, CEN(lch));
+        p->dma_write(elem_count, CEN, lch);
-        dma_write(frame_count, CFN(lch));
+        p->dma_write(frame_count, CFN, lch);
        /*
         * If the chain is dynamically linked,
@@ -1566,8 +1503,8 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
                                enable_lnk(dma_chan[lch].prev_linked_ch);
                                dma_chan[lch].state = DMA_CH_QUEUED;
                                start_dma = 0;
-                                if (0 == ((1 << 7) & dma_read(
+                                if (0 == ((1 << 7) & p->dma_read(
-                                        CCR(dma_chan[lch].prev_linked_ch)))) {
+                                        CCR, dma_chan[lch].prev_linked_ch))) {
                                        disable_lnk(dma_chan[lch].
                                                    prev_linked_ch);
                                        pr_debug("\n prev ch is stopped\n");
@@ -1583,7 +1520,7 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
                        }
                        omap_enable_channel_irq(lch);
-                        l = dma_read(CCR(lch));
+                        l = p->dma_read(CCR, lch);
                        if ((0 == (l & (1 << 24))))
                                l &= ~(1 << 25);
@@ -1594,12 +1531,12 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
                                        l |= (1 << 7);
                                        dma_chan[lch].state = DMA_CH_STARTED;
                                        pr_debug("starting %d\n", lch);
-                                        dma_write(l, CCR(lch));
+                                        p->dma_write(l, CCR, lch);
                                } else
                                        start_dma = 0;
                        } else {
                                if (0 == (l & (1 << 7)))
-                                        dma_write(l, CCR(lch));
+                                        p->dma_write(l, CCR, lch);
                        }
                        dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
                }
@@ -1644,7 +1581,7 @@ int omap_start_dma_chain_transfers(int chain_id)
                omap_enable_channel_irq(channels[0]);
        }
-        l = dma_read(CCR(channels[0]));
+        l = p->dma_read(CCR, channels[0]);
        l |= (1 << 7);
        dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
        dma_chan[channels[0]].state = DMA_CH_STARTED;
@@ -1653,7 +1590,7 @@ int omap_start_dma_chain_transfers(int chain_id)
                l &= ~(1 << 25);
        else
                l |= (1 << 25);
-        dma_write(l, CCR(channels[0]));
+        p->dma_write(l, CCR, channels[0]);
        dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
@@ -1673,7 +1610,7 @@ int omap_stop_dma_chain_transfers(int chain_id)
 {
        int *channels;
        u32 l, i;
-        u32 sys_cf;
+        u32 sys_cf = 0;
        /* Check for input params */
        if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
@@ -1688,22 +1625,20 @@ int omap_stop_dma_chain_transfers(int chain_id)
        }
        channels = dma_linked_lch[chain_id].linked_dmach_q;
-        /*
+        if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
-         * DMA Errata:
+                sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
-         * Special programming model needed to disable DMA before end of block
+                l = sys_cf;
-         */
+                /* Middle mode reg set no Standby */
-        sys_cf = dma_read(OCP_SYSCONFIG);
+                l &= ~((1 << 12)|(1 << 13));
-        l = sys_cf;
+                p->dma_write(l, OCP_SYSCONFIG, 0);
-        /* Middle mode reg set no Standby */
+        }
-        l &= ~((1 << 12)|(1 << 13));
-        dma_write(l, OCP_SYSCONFIG);
        for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
                /* Stop the Channel transmission */
-                l = dma_read(CCR(channels[i]));
+                l = p->dma_read(CCR, channels[i]);
                l &= ~(1 << 7);
-                dma_write(l, CCR(channels[i]));
+                p->dma_write(l, CCR, channels[i]);
                /* Disable the link in all the channels */
                disable_lnk(channels[i]);
@@ -1715,8 +1650,8 @@ int omap_stop_dma_chain_transfers(int chain_id)
        /* Reset the Queue pointers */
        OMAP_DMA_CHAIN_QINIT(chain_id);
-        /* Errata - put in the old value */
+        if (IS_DMA_ERRATA(DMA_ERRATA_i88))
-        dma_write(sys_cf, OCP_SYSCONFIG);
+                p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
        return 0;
 }
@@ -1758,8 +1693,8 @@ int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
        /* Get the current channel */
        lch = channels[dma_linked_lch[chain_id].q_head];
-        *ei = dma_read(CCEN(lch));
+        *ei = p->dma_read(CCEN, lch);
-        *fi = dma_read(CCFN(lch));
+        *fi = p->dma_read(CCFN, lch);
        return 0;
 }
@@ -1796,7 +1731,7 @@ int omap_get_dma_chain_dst_pos(int chain_id)
        /* Get the current channel */
        lch = channels[dma_linked_lch[chain_id].q_head];
-        return dma_read(CDAC(lch));
+        return p->dma_read(CDAC, lch);
 }
 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
@@ -1830,7 +1765,7 @@ int omap_get_dma_chain_src_pos(int chain_id)
        /* Get the current channel */
        lch = channels[dma_linked_lch[chain_id].q_head];
-        return dma_read(CSAC(lch));
+        return p->dma_read(CSAC, lch);
 }
 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
@@ -1847,7 +1782,7 @@ static int omap1_dma_handle_ch(int ch)
                csr = dma_chan[ch].saved_csr;
                dma_chan[ch].saved_csr = 0;
        } else
-                csr = dma_read(CSR(ch));
+                csr = p->dma_read(CSR, ch);
        if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
                dma_chan[ch + 6].saved_csr = csr >> 7;
                csr &= 0x7f;
@@ -1900,13 +1835,13 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
 static int omap2_dma_handle_ch(int ch)
 {
-        u32 status = dma_read(CSR(ch));
+        u32 status = p->dma_read(CSR, ch);
        if (!status) {
                if (printk_ratelimit())
                        printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
                                ch);
-                dma_write(1 << ch, IRQSTATUS_L0);
+                p->dma_write(1 << ch, IRQSTATUS_L0, ch);
                return 0;
        }
        if (unlikely(dma_chan[ch].dev_id == -1)) {
@@ -1922,17 +1857,12 @@ static int omap2_dma_handle_ch(int ch)
        if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
                printk(KERN_INFO "DMA transaction error with device %d\n",
                       dma_chan[ch].dev_id);
-                if (cpu_class_is_omap2()) {
+                if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
-                        /*
-                         * Errata: sDMA Channel is not disabled
-                         * after a transaction error. So we explicitely
-                         * disable the channel
-                         */
                        u32 ccr;
-                        ccr = dma_read(CCR(ch));
+                        ccr = p->dma_read(CCR, ch);
                        ccr &= ~OMAP_DMA_CCR_EN;
-                        dma_write(ccr, CCR(ch));
+                        p->dma_write(ccr, CCR, ch);
                        dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
                }
        }
@@ -1943,14 +1873,16 @@ static int omap2_dma_handle_ch(int ch)
                printk(KERN_INFO "DMA misaligned error with device %d\n",
                       dma_chan[ch].dev_id);
-        dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
+        p->dma_write(status, CSR, ch);
-        dma_write(1 << ch, IRQSTATUS_L0);
+        p->dma_write(1 << ch, IRQSTATUS_L0, ch);
+        /* read back the register to flush the write */
+        p->dma_read(IRQSTATUS_L0, ch);
        /* If the ch is not chained then chain_id will be -1 */
        if (dma_chan[ch].chain_id != -1) {
                int chain_id = dma_chan[ch].chain_id;
                dma_chan[ch].state = DMA_CH_NOTSTARTED;
-                if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
+                if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
                        dma_chan[dma_chan[ch].next_linked_ch].state =
                                                        DMA_CH_STARTED;
                if (dma_linked_lch[chain_id].chain_mode ==
@@ -1960,11 +1892,10 @@ static int omap2_dma_handle_ch(int ch)
                if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
                        OMAP_DMA_CHAIN_INCQHEAD(chain_id);
-                status = dma_read(CSR(ch));
+                status = p->dma_read(CSR, ch);
+                p->dma_write(status, CSR, ch);
        }
-        dma_write(status, CSR(ch));
        if (likely(dma_chan[ch].callback != NULL))
                dma_chan[ch].callback(ch, status, dma_chan[ch].data);
@@ -1977,13 +1908,13 @@ static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
        u32 val, enable_reg;
        int i;
-        val = dma_read(IRQSTATUS_L0);
+        val = p->dma_read(IRQSTATUS_L0, 0);
        if (val == 0) {
                if (printk_ratelimit())
                        printk(KERN_WARNING "Spurious DMA IRQ\n");
                return IRQ_HANDLED;
        }
-        enable_reg = dma_read(IRQENABLE_L0);
+        enable_reg = p->dma_read(IRQENABLE_L0, 0);
        val &= enable_reg; /* Dispatch only relevant interrupts */
        for (i = 0; i < dma_lch_count && val != 0; i++) {
                if (val & 1)
@@ -2009,119 +1940,66 @@ static struct irqaction omap24xx_dma_irq;
 void omap_dma_global_context_save(void)
 {
        omap_dma_global_context.dma_irqenable_l0 =
-                dma_read(IRQENABLE_L0);
+                p->dma_read(IRQENABLE_L0, 0);
        omap_dma_global_context.dma_ocp_sysconfig =
-                dma_read(OCP_SYSCONFIG);
+                p->dma_read(OCP_SYSCONFIG, 0);
-        omap_dma_global_context.dma_gcr = dma_read(GCR);
+        omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
 }
 void omap_dma_global_context_restore(void)
 {
        int ch;
-        dma_write(omap_dma_global_context.dma_gcr, GCR);
+        p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
-        dma_write(omap_dma_global_context.dma_ocp_sysconfig,
+        p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
-                OCP_SYSCONFIG);
+                OCP_SYSCONFIG, 0);
-        dma_write(omap_dma_global_context.dma_irqenable_l0,
+        p->dma_write(omap_dma_global_context.dma_irqenable_l0,
-                IRQENABLE_L0);
+                IRQENABLE_L0, 0);
-        /*
+        if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
-         * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
+                p->dma_write(0x3 , IRQSTATUS_L0, 0);
-         * after secure sram context save and restore. Hence we need to
-         * manually clear those IRQs to avoid spurious interrupts. This
-         * affects only secure devices.
-         */
-        if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
-                dma_write(0x3 , IRQSTATUS_L0);
        for (ch = 0; ch < dma_chan_count; ch++)
                if (dma_chan[ch].dev_id != -1)
                        omap_clear_dma(ch);
 }
-/*----------------------------------------------------------------------------*/
+static int __devinit omap_system_dma_probe(struct platform_device *pdev)
-static int __init omap_init_dma(void)
 {
-        unsigned long base;
+        int ch, ret = 0;
-        int ch, r;
+        int dma_irq;
+        char irq_name[4];
-        if (cpu_class_is_omap1()) {
+        int irq_rel;
-                base = OMAP1_DMA_BASE;
-                dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
+        p = pdev->dev.platform_data;
-        } else if (cpu_is_omap24xx()) {
+        if (!p) {
-                base = OMAP24XX_DMA4_BASE;
+                dev_err(&pdev->dev, "%s: System DMA initialized without"
-                dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
+                        "platform data\n", __func__);
-        } else if (cpu_is_omap34xx()) {
+                return -EINVAL;
-                base = OMAP34XX_DMA4_BASE;
-                dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
-        } else if (cpu_is_omap44xx()) {
-                base = OMAP44XX_DMA4_BASE;
-                dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
-        } else {
-                pr_err("DMA init failed for unsupported omap\n");
-                return -ENODEV;
        }
-        omap_dma_base = ioremap(base, SZ_4K);
+        d                       = p->dma_attr;
-        BUG_ON(!omap_dma_base);
+        errata                  = p->errata;
-        if (cpu_class_is_omap2() && omap_dma_reserve_channels
+        if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
                        && (omap_dma_reserve_channels <= dma_lch_count))
-                dma_lch_count = omap_dma_reserve_channels;
+                d->lch_count    = omap_dma_reserve_channels;
-        dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
+        dma_lch_count           = d->lch_count;
-                                GFP_KERNEL);
+        dma_chan_count          = dma_lch_count;
-        if (!dma_chan) {
+        dma_chan                = d->chan;
-                r = -ENOMEM;
+        enable_1510_mode        = d->dev_caps & ENABLE_1510_MODE;
-                goto out_unmap;
-        }
        if (cpu_class_is_omap2()) {
                dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
                                                dma_lch_count, GFP_KERNEL);
                if (!dma_linked_lch) {
-                        r = -ENOMEM;
+                        ret = -ENOMEM;
-                        goto out_free;
+                        goto exit_dma_lch_fail;
                }
        }
-        if (cpu_is_omap15xx()) {
-                printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
-                dma_chan_count = 9;
-                enable_1510_mode = 1;
-        } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
-                printk(KERN_INFO "OMAP DMA hardware version %d\n",
-                       dma_read(HW_ID));
-                printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
-                       (dma_read(CAPS_0_U) << 16) |
-                       dma_read(CAPS_0_L),
-                       (dma_read(CAPS_1_U) << 16) |
-                       dma_read(CAPS_1_L),
-                       dma_read(CAPS_2), dma_read(CAPS_3),
-                       dma_read(CAPS_4));
-                if (!enable_1510_mode) {
-                        u16 w;
-                        /* Disable OMAP 3.0/3.1 compatibility mode. */
-                        w = dma_read(GSCR);
-                        w |= 1 << 3;
-                        dma_write(w, GSCR);
-                        dma_chan_count = 16;
-                } else
-                        dma_chan_count = 9;
-        } else if (cpu_class_is_omap2()) {
-                u8 revision = dma_read(REVISION) & 0xff;
-                printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
-                       revision >> 4, revision & 0xf);
-                dma_chan_count = dma_lch_count;
-        } else {
-                dma_chan_count = 0;
-                return 0;
-        }
        spin_lock_init(&dma_chan_lock);
        for (ch = 0; ch < dma_chan_count; ch++) {
                omap_clear_dma(ch);
                if (cpu_class_is_omap2())
@@ -2138,20 +2016,23 @@ static int __init omap_init_dma(void)
                         * request_irq() doesn't like dev_id (ie. ch) being
                         * zero, so we have to kludge around this.
                         */
-                        r = request_irq(omap1_dma_irq[ch],
+                        sprintf(&irq_name[0], "%d", ch);
+                        dma_irq = platform_get_irq_byname(pdev, irq_name);
+                        if (dma_irq < 0) {
+                                ret = dma_irq;
+                                goto exit_dma_irq_fail;
+                        }
+                        /* INT_DMA_LCD is handled in lcd_dma.c */
+                        if (dma_irq == INT_DMA_LCD)
+                                continue;
+                        ret = request_irq(dma_irq,
                                        omap1_dma_irq_handler, 0, "DMA",
                                        (void *) (ch + 1));
-                        if (r != 0) {
+                        if (ret != 0)
-                                int i;
+                                goto exit_dma_irq_fail;
-                                printk(KERN_ERR "unable to request IRQ %d "
-                                       "for DMA (error %d)\n",
-                                       omap1_dma_irq[ch], r);
-                                for (i = 0; i < ch; i++)
-                                        free_irq(omap1_dma_irq[i],
-                                                 (void *) (i + 1));
-                                goto out_free;
-                        }
                }
        }
@@ -2160,46 +2041,91 @@ static int __init omap_init_dma(void)
                                DMA_DEFAULT_FIFO_DEPTH, 0);
        if (cpu_class_is_omap2()) {
-                int irq;
+                strcpy(irq_name, "0");
-                if (cpu_is_omap44xx())
+                dma_irq = platform_get_irq_byname(pdev, irq_name);
-                        irq = OMAP44XX_IRQ_SDMA_0;
+                if (dma_irq < 0) {
-                else
+                        dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
-                        irq = INT_24XX_SDMA_IRQ0;
+                        goto exit_dma_lch_fail;
-                setup_irq(irq, &omap24xx_dma_irq);
+                }
-        }
+                ret = setup_irq(dma_irq, &omap24xx_dma_irq);
+                if (ret) {
-        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+                        dev_err(&pdev->dev, "set_up failed for IRQ %d"
-                /* Enable smartidle idlemodes and autoidle */
+                                "for DMA (error %d)\n", dma_irq, ret);
-                u32 v = dma_read(OCP_SYSCONFIG);
+                        goto exit_dma_lch_fail;
-                v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
-                                DMA_SYSCONFIG_SIDLEMODE_MASK |
-                                DMA_SYSCONFIG_AUTOIDLE);
-                v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
-                        DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
-                        DMA_SYSCONFIG_AUTOIDLE);
-                dma_write(v , OCP_SYSCONFIG);
-                /* reserve dma channels 0 and 1 in high security devices */
-                if (cpu_is_omap34xx() &&
-                        (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
-                        printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
-                                        "HS ROM code\n");
-                        dma_chan[0].dev_id = 0;
-                        dma_chan[1].dev_id = 1;
                }
        }
+        /* reserve dma channels 0 and 1 in high security devices */
+        if (cpu_is_omap34xx() &&
+                (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
+                printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
+                                "HS ROM code\n");
+                dma_chan[0].dev_id = 0;
+                dma_chan[1].dev_id = 1;
+        }
+        p->show_dma_caps();
        return 0;
-out_free:
+exit_dma_irq_fail:
+        dev_err(&pdev->dev, "unable to request IRQ %d"
+                        "for DMA (error %d)\n", dma_irq, ret);
+        for (irq_rel = 0; irq_rel < ch; irq_rel++) {
+                dma_irq = platform_get_irq(pdev, irq_rel);
+                free_irq(dma_irq, (void *)(irq_rel + 1));
+        }
+exit_dma_lch_fail:
+        kfree(p);
+        kfree(d);
        kfree(dma_chan);
+        return ret;
+}
-out_unmap:
+static int __devexit omap_system_dma_remove(struct platform_device *pdev)
-        iounmap(omap_dma_base);
+{
+        int dma_irq;
-        return r;
+        if (cpu_class_is_omap2()) {
+                char irq_name[4];
+                strcpy(irq_name, "0");
+                dma_irq = platform_get_irq_byname(pdev, irq_name);
+                remove_irq(dma_irq, &omap24xx_dma_irq);
+        } else {
+                int irq_rel = 0;
+                for ( ; irq_rel < dma_chan_count; irq_rel++) {
+                        dma_irq = platform_get_irq(pdev, irq_rel);
+                        free_irq(dma_irq, (void *)(irq_rel + 1));
+                }
+        }
+        kfree(p);
+        kfree(d);
+        kfree(dma_chan);
+        return 0;
+}
+static struct platform_driver omap_system_dma_driver = {
+        .probe          = omap_system_dma_probe,
+        .remove         = omap_system_dma_remove,
+        .driver         = {
+                .name   = "omap_dma_system"
+        },
+};
+static int __init omap_system_dma_init(void)
+{
+        return platform_driver_register(&omap_system_dma_driver);
+}
+arch_initcall(omap_system_dma_init);
+static void __exit omap_system_dma_exit(void)
+{
+        platform_driver_unregister(&omap_system_dma_driver);
 }
-arch_initcall(omap_init_dma);
+MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRIVER_NAME);
+MODULE_AUTHOR("Texas Instruments Inc");
 /*
 * Reserve the omap SDMA channels using cmdline bootarg
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 44bafdab2dce..ee9f6ebba29b 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -342,6 +342,10 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
        l |= 0x02 << 3;  /* Set to smart-idle mode */
        l |= 0x2 << 8;   /* Set clock activity to perserve f-clock on idle */
+        /* Enable autoidle on OMAP2 / OMAP3 */
+        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+                l |= 0x1 << 0;
        /*
         * Enable wake-up on OMAP2 CPUs.
         */
@@ -581,7 +585,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
         * When the functional clock disappears, too quick writes seem
         * to cause an abort. XXX Is this still necessary?
         */
-        __delay(150000);
+        __delay(300000);
        return ret;
 }
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index 0054b9501a53..c9e5d7298c40 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -36,6 +36,8 @@
 #include <plat/board.h>
 #include <plat/sram.h>
+#include "fb.h"
 #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
 static struct omapfb_platform_data omapfb_config;
@@ -94,7 +96,7 @@ static int fbmem_region_reserved(unsigned long start, size_t size)
 * Get the region_idx`th region from board config/ATAG and convert it to
 * our internal format.
 */
-static int get_fbmem_region(int region_idx, struct omapfb_mem_region *rg)
+static int __init get_fbmem_region(int region_idx, struct omapfb_mem_region *rg)
 {
        const struct omap_fbmem_config  *conf;
        u32                             paddr;
@@ -126,7 +128,7 @@ static int set_fbmem_region_type(struct omapfb_mem_region *rg, int mem_type,
         * type = 0 && paddr = 0, a default don't care case maps to
         * the SDRAM type.
         */
-        if (rg->type || (!rg->type && !rg->paddr))
+        if (rg->type || !rg->paddr)
                return 0;
        if (ranges_overlap(rg->paddr, rg->size, mem_start, mem_size)) {
                rg->type = mem_type;
@@ -173,11 +175,7 @@ static int check_fbmem_region(int region_idx, struct omapfb_mem_region *rg,
 static int valid_sdram(unsigned long addr, unsigned long size)
 {
-        struct memblock_property res;
+        return memblock_is_region_memory(addr, size);
-        res.base = addr;
-        res.size = size;
-        return !memblock_find(&res) && res.base == addr && res.size == size;
 }
 static int reserve_sdram(unsigned long addr, unsigned long size)
@@ -262,7 +260,7 @@ void __init omapfb_reserve_sdram_memblock(void)
 * this point, since the driver built as a module would have problem with
 * freeing / reallocating the regions.
 */
-unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
+unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
                                  unsigned long sram_vstart,
                                  unsigned long sram_size,
                                  unsigned long pstart_avail,
@@ -336,7 +334,7 @@ void omapfb_set_ctrl_platform_data(void *data)
        omapfb_config.ctrl_platform_data = data;
 }
-static inline int omap_init_fb(void)
+static int __init omap_init_fb(void)
 {
        const struct omap_lcd_config *conf;
@@ -381,7 +379,7 @@ void omapfb_set_platform_data(struct omapfb_platform_data *data)
        omapfb_config = *data;
 }
-static inline int omap_init_fb(void)
+static int __init omap_init_fb(void)
 {
        return platform_device_register(&omap_fb_device);
 }
@@ -392,7 +390,7 @@ void omapfb_reserve_sdram_memblock(void)
 {
 }
-unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
+unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
                                  unsigned long sram_vstart,
                                  unsigned long sram_size,
                                  unsigned long start_avail,
@@ -411,7 +409,7 @@ void omapfb_reserve_sdram_memblock(void)
 {
 }
-unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
+unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
                                  unsigned long sram_vstart,
                                  unsigned long sram_size,
                                  unsigned long start_avail,
diff --git a/arch/arm/plat-omap/fb.h b/arch/arm/plat-omap/fb.h
new file mode 100644
index 000000000000..d765d0bd8520
--- /dev/null
+++ b/arch/arm/plat-omap/fb.h
@@ -0,0 +1,10 @@
+#ifndef __PLAT_OMAP_FB_H__
+#define __PLAT_OMAP_FB_H__
+extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
+                                         unsigned long sram_vstart,
+                                         unsigned long sram_size,
+                                         unsigned long pstart_avail,
+                                         unsigned long size_avail);
+#endif /* __PLAT_OMAP_FB_H__ */
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
deleted file mode 100644
index 7951eefe1a0e..000000000000
--- a/arch/arm/plat-omap/gpio.c
+++ /dev/null
@@ -1,2344 +0,0 @@
-/*
- *  linux/arch/arm/plat-omap/gpio.c
- *
- * Support functions for OMAP GPIO
- *
- * Copyright (C) 2003-2005 Nokia Corporation
- * Written by Juha Yrjölä <juha.yrjola@nokia.com>
- *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/sysdev.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <mach/irqs.h>
-#include <mach/gpio.h>
-#include <asm/mach/irq.h>
-#include <plat/powerdomain.h>
-/*
- * OMAP1510 GPIO registers
- */
-#define OMAP1510_GPIO_BASE              0xfffce000
-#define OMAP1510_GPIO_DATA_INPUT        0x00
-#define OMAP1510_GPIO_DATA_OUTPUT       0x04
-#define OMAP1510_GPIO_DIR_CONTROL       0x08
-#define OMAP1510_GPIO_INT_CONTROL       0x0c
-#define OMAP1510_GPIO_INT_MASK          0x10
-#define OMAP1510_GPIO_INT_STATUS        0x14
-#define OMAP1510_GPIO_PIN_CONTROL       0x18
-#define OMAP1510_IH_GPIO_BASE           64
-/*
- * OMAP1610 specific GPIO registers
- */
-#define OMAP1610_GPIO1_BASE             0xfffbe400
-#define OMAP1610_GPIO2_BASE             0xfffbec00
-#define OMAP1610_GPIO3_BASE             0xfffbb400
-#define OMAP1610_GPIO4_BASE             0xfffbbc00
-#define OMAP1610_GPIO_REVISION          0x0000
-#define OMAP1610_GPIO_SYSCONFIG         0x0010
-#define OMAP1610_GPIO_SYSSTATUS         0x0014
-#define OMAP1610_GPIO_IRQSTATUS1        0x0018
-#define OMAP1610_GPIO_IRQENABLE1        0x001c
-#define OMAP1610_GPIO_WAKEUPENABLE      0x0028
-#define OMAP1610_GPIO_DATAIN            0x002c
-#define OMAP1610_GPIO_DATAOUT           0x0030
-#define OMAP1610_GPIO_DIRECTION         0x0034
-#define OMAP1610_GPIO_EDGE_CTRL1        0x0038
-#define OMAP1610_GPIO_EDGE_CTRL2        0x003c
-#define OMAP1610_GPIO_CLEAR_IRQENABLE1  0x009c
-#define OMAP1610_GPIO_CLEAR_WAKEUPENA   0x00a8
-#define OMAP1610_GPIO_CLEAR_DATAOUT     0x00b0
-#define OMAP1610_GPIO_SET_IRQENABLE1    0x00dc
-#define OMAP1610_GPIO_SET_WAKEUPENA     0x00e8
-#define OMAP1610_GPIO_SET_DATAOUT       0x00f0
-/*
- * OMAP7XX specific GPIO registers
- */
-#define OMAP7XX_GPIO1_BASE              0xfffbc000
-#define OMAP7XX_GPIO2_BASE              0xfffbc800
-#define OMAP7XX_GPIO3_BASE              0xfffbd000
-#define OMAP7XX_GPIO4_BASE              0xfffbd800
-#define OMAP7XX_GPIO5_BASE              0xfffbe000
-#define OMAP7XX_GPIO6_BASE              0xfffbe800
-#define OMAP7XX_GPIO_DATA_INPUT         0x00
-#define OMAP7XX_GPIO_DATA_OUTPUT        0x04
-#define OMAP7XX_GPIO_DIR_CONTROL        0x08
-#define OMAP7XX_GPIO_INT_CONTROL        0x0c
-#define OMAP7XX_GPIO_INT_MASK           0x10
-#define OMAP7XX_GPIO_INT_STATUS         0x14
-#define OMAP1_MPUIO_VBASE               OMAP1_MPUIO_BASE
-/*
- * omap24xx specific GPIO registers
- */
-#define OMAP242X_GPIO1_BASE             0x48018000
-#define OMAP242X_GPIO2_BASE             0x4801a000
-#define OMAP242X_GPIO3_BASE             0x4801c000
-#define OMAP242X_GPIO4_BASE             0x4801e000
-#define OMAP243X_GPIO1_BASE             0x4900C000
-#define OMAP243X_GPIO2_BASE             0x4900E000
-#define OMAP243X_GPIO3_BASE             0x49010000
-#define OMAP243X_GPIO4_BASE             0x49012000
-#define OMAP243X_GPIO5_BASE             0x480B6000
-#define OMAP24XX_GPIO_REVISION          0x0000
-#define OMAP24XX_GPIO_SYSCONFIG         0x0010
-#define OMAP24XX_GPIO_SYSSTATUS         0x0014
-#define OMAP24XX_GPIO_IRQSTATUS1        0x0018
-#define OMAP24XX_GPIO_IRQSTATUS2        0x0028
-#define OMAP24XX_GPIO_IRQENABLE2        0x002c
-#define OMAP24XX_GPIO_IRQENABLE1        0x001c
-#define OMAP24XX_GPIO_WAKE_EN           0x0020
-#define OMAP24XX_GPIO_CTRL              0x0030
-#define OMAP24XX_GPIO_OE                0x0034
-#define OMAP24XX_GPIO_DATAIN            0x0038
-#define OMAP24XX_GPIO_DATAOUT           0x003c
-#define OMAP24XX_GPIO_LEVELDETECT0      0x0040
-#define OMAP24XX_GPIO_LEVELDETECT1      0x0044
-#define OMAP24XX_GPIO_RISINGDETECT      0x0048
-#define OMAP24XX_GPIO_FALLINGDETECT     0x004c
-#define OMAP24XX_GPIO_DEBOUNCE_EN       0x0050
-#define OMAP24XX_GPIO_DEBOUNCE_VAL      0x0054
-#define OMAP24XX_GPIO_CLEARIRQENABLE1   0x0060
-#define OMAP24XX_GPIO_SETIRQENABLE1     0x0064
-#define OMAP24XX_GPIO_CLEARWKUENA       0x0080
-#define OMAP24XX_GPIO_SETWKUENA         0x0084
-#define OMAP24XX_GPIO_CLEARDATAOUT      0x0090
-#define OMAP24XX_GPIO_SETDATAOUT        0x0094
-#define OMAP4_GPIO_REVISION             0x0000
-#define OMAP4_GPIO_SYSCONFIG            0x0010
-#define OMAP4_GPIO_EOI                  0x0020
-#define OMAP4_GPIO_IRQSTATUSRAW0        0x0024
-#define OMAP4_GPIO_IRQSTATUSRAW1        0x0028
-#define OMAP4_GPIO_IRQSTATUS0           0x002c
-#define OMAP4_GPIO_IRQSTATUS1           0x0030
-#define OMAP4_GPIO_IRQSTATUSSET0        0x0034
-#define OMAP4_GPIO_IRQSTATUSSET1        0x0038
-#define OMAP4_GPIO_IRQSTATUSCLR0        0x003c
-#define OMAP4_GPIO_IRQSTATUSCLR1        0x0040
-#define OMAP4_GPIO_IRQWAKEN0            0x0044
-#define OMAP4_GPIO_IRQWAKEN1            0x0048
-#define OMAP4_GPIO_SYSSTATUS            0x0114
-#define OMAP4_GPIO_IRQENABLE1           0x011c
-#define OMAP4_GPIO_WAKE_EN              0x0120
-#define OMAP4_GPIO_IRQSTATUS2           0x0128
-#define OMAP4_GPIO_IRQENABLE2           0x012c
-#define OMAP4_GPIO_CTRL                 0x0130
-#define OMAP4_GPIO_OE                   0x0134
-#define OMAP4_GPIO_DATAIN               0x0138
-#define OMAP4_GPIO_DATAOUT              0x013c
-#define OMAP4_GPIO_LEVELDETECT0         0x0140
-#define OMAP4_GPIO_LEVELDETECT1         0x0144
-#define OMAP4_GPIO_RISINGDETECT         0x0148
-#define OMAP4_GPIO_FALLINGDETECT        0x014c
-#define OMAP4_GPIO_DEBOUNCENABLE        0x0150
-#define OMAP4_GPIO_DEBOUNCINGTIME       0x0154
-#define OMAP4_GPIO_CLEARIRQENABLE1      0x0160
-#define OMAP4_GPIO_SETIRQENABLE1        0x0164
-#define OMAP4_GPIO_CLEARWKUENA          0x0180
-#define OMAP4_GPIO_SETWKUENA            0x0184
-#define OMAP4_GPIO_CLEARDATAOUT         0x0190
-#define OMAP4_GPIO_SETDATAOUT           0x0194
-/*
- * omap34xx specific GPIO registers
- */
-#define OMAP34XX_GPIO1_BASE             0x48310000
-#define OMAP34XX_GPIO2_BASE             0x49050000
-#define OMAP34XX_GPIO3_BASE             0x49052000
-#define OMAP34XX_GPIO4_BASE             0x49054000
-#define OMAP34XX_GPIO5_BASE             0x49056000
-#define OMAP34XX_GPIO6_BASE             0x49058000
-/*
- * OMAP44XX  specific GPIO registers
- */
-#define OMAP44XX_GPIO1_BASE             0x4a310000
-#define OMAP44XX_GPIO2_BASE             0x48055000
-#define OMAP44XX_GPIO3_BASE             0x48057000
-#define OMAP44XX_GPIO4_BASE             0x48059000
-#define OMAP44XX_GPIO5_BASE             0x4805B000
-#define OMAP44XX_GPIO6_BASE             0x4805D000
-struct gpio_bank {
-        unsigned long pbase;
-        void __iomem *base;
-        u16 irq;
-        u16 virtual_irq_start;
-        int method;
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
-        u32 suspend_wakeup;
-        u32 saved_wakeup;
-#endif
-#ifdef CONFIG_ARCH_OMAP2PLUS
-        u32 non_wakeup_gpios;
-        u32 enabled_non_wakeup_gpios;
-        u32 saved_datain;
-        u32 saved_fallingdetect;
-        u32 saved_risingdetect;
-#endif
-        u32 level_mask;
-        u32 toggle_mask;
-        spinlock_t lock;
-        struct gpio_chip chip;
-        struct clk *dbck;
-        u32 mod_usage;
-        u32 dbck_enable_mask;
-};
-#define METHOD_MPUIO            0
-#define METHOD_GPIO_1510        1
-#define METHOD_GPIO_1610        2
-#define METHOD_GPIO_7XX         3
-#define METHOD_GPIO_24XX        5
-#define METHOD_GPIO_44XX        6
-#ifdef CONFIG_ARCH_OMAP16XX
-static struct gpio_bank gpio_bank_1610[5] = {
-        { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
-                METHOD_MPUIO },
-        { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
-                METHOD_GPIO_1610 },
-        { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
-                METHOD_GPIO_1610 },
-        { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
-                METHOD_GPIO_1610 },
-        { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
-                METHOD_GPIO_1610 },
-};
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-static struct gpio_bank gpio_bank_1510[2] = {
-        { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
-                METHOD_MPUIO },
-        { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
-                METHOD_GPIO_1510 }
-};
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-static struct gpio_bank gpio_bank_7xx[7] = {
-        { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
-                METHOD_MPUIO },
-        { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
-                METHOD_GPIO_7XX },
-        { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
-                METHOD_GPIO_7XX },
-        { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
-                METHOD_GPIO_7XX },
-        { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4,  IH_GPIO_BASE + 96,
-                METHOD_GPIO_7XX },
-        { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5,  IH_GPIO_BASE + 128,
-                METHOD_GPIO_7XX },
-        { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6,  IH_GPIO_BASE + 160,
-                METHOD_GPIO_7XX },
-};
-#endif
-#ifdef CONFIG_ARCH_OMAP2
-static struct gpio_bank gpio_bank_242x[4] = {
-        { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
-                METHOD_GPIO_24XX },
-        { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
-                METHOD_GPIO_24XX },
-        { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
-                METHOD_GPIO_24XX },
-        { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
-                METHOD_GPIO_24XX },
-};
-static struct gpio_bank gpio_bank_243x[5] = {
-        { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
-                METHOD_GPIO_24XX },
-        { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
-                METHOD_GPIO_24XX },
-        { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
-                METHOD_GPIO_24XX },
-        { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
-                METHOD_GPIO_24XX },
-        { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
-                METHOD_GPIO_24XX },
-};
-#endif
-#ifdef CONFIG_ARCH_OMAP3
-static struct gpio_bank gpio_bank_34xx[6] = {
-        { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
-                METHOD_GPIO_24XX },
-        { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
-                METHOD_GPIO_24XX },
-        { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
-                METHOD_GPIO_24XX },
-        { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
-                METHOD_GPIO_24XX },
-        { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
-                METHOD_GPIO_24XX },
-        { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
-                METHOD_GPIO_24XX },
-};
-struct omap3_gpio_regs {
-        u32 sysconfig;
-        u32 irqenable1;
-        u32 irqenable2;
-        u32 wake_en;
-        u32 ctrl;
-        u32 oe;
-        u32 leveldetect0;
-        u32 leveldetect1;
-        u32 risingdetect;
-        u32 fallingdetect;
-        u32 dataout;
-};
-static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-static struct gpio_bank gpio_bank_44xx[6] = {
-        { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE,
-                METHOD_GPIO_44XX },
-        { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32,
-                METHOD_GPIO_44XX },
-        { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64,
-                METHOD_GPIO_44XX },
-        { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96,
-                METHOD_GPIO_44XX },
-        { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128,
-                METHOD_GPIO_44XX },
-        { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160,
-                METHOD_GPIO_44XX },
-};
-#endif
-static struct gpio_bank *gpio_bank;
-static int gpio_bank_count;
-static inline struct gpio_bank *get_gpio_bank(int gpio)
-{
-        if (cpu_is_omap15xx()) {
-                if (OMAP_GPIO_IS_MPUIO(gpio))
-                        return &gpio_bank[0];
-                return &gpio_bank[1];
-        }
-        if (cpu_is_omap16xx()) {
-                if (OMAP_GPIO_IS_MPUIO(gpio))
-                        return &gpio_bank[0];
-                return &gpio_bank[1 + (gpio >> 4)];
-        }
-        if (cpu_is_omap7xx()) {
-                if (OMAP_GPIO_IS_MPUIO(gpio))
-                        return &gpio_bank[0];
-                return &gpio_bank[1 + (gpio >> 5)];
-        }
-        if (cpu_is_omap24xx())
-                return &gpio_bank[gpio >> 5];
-        if (cpu_is_omap34xx() || cpu_is_omap44xx())
-                return &gpio_bank[gpio >> 5];
-        BUG();
-        return NULL;
-}
-static inline int get_gpio_index(int gpio)
-{
-        if (cpu_is_omap7xx())
-                return gpio & 0x1f;
-        if (cpu_is_omap24xx())
-                return gpio & 0x1f;
-        if (cpu_is_omap34xx() || cpu_is_omap44xx())
-                return gpio & 0x1f;
-        return gpio & 0x0f;
-}
-static inline int gpio_valid(int gpio)
-{
-        if (gpio < 0)
-                return -1;
-        if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
-                if (gpio >= OMAP_MAX_GPIO_LINES + 16)
-                        return -1;
-                return 0;
-        }
-        if (cpu_is_omap15xx() && gpio < 16)
-                return 0;
-        if ((cpu_is_omap16xx()) && gpio < 64)
-                return 0;
-        if (cpu_is_omap7xx() && gpio < 192)
-                return 0;
-        if (cpu_is_omap2420() && gpio < 128)
-                return 0;
-        if (cpu_is_omap2430() && gpio < 160)
-                return 0;
-        if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
-                return 0;
-        return -1;
-}
-static int check_gpio(int gpio)
-{
-        if (unlikely(gpio_valid(gpio) < 0)) {
-                printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
-                dump_stack();
-                return -1;
-        }
-        return 0;
-}
-static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
-{
-        void __iomem *reg = bank->base;
-        u32 l;
-        switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP1
-        case METHOD_MPUIO:
-                reg += OMAP_MPUIO_IO_CNTL;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_DIR_CONTROL;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-        case METHOD_GPIO_1610:
-                reg += OMAP1610_GPIO_DIRECTION;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        case METHOD_GPIO_7XX:
-                reg += OMAP7XX_GPIO_DIR_CONTROL;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-        case METHOD_GPIO_24XX:
-                reg += OMAP24XX_GPIO_OE;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
-        case METHOD_GPIO_44XX:
-                reg += OMAP4_GPIO_OE;
-                break;
-#endif
-        default:
-                WARN_ON(1);
-                return;
-        }
-        l = __raw_readl(reg);
-        if (is_input)
-                l |= 1 << gpio;
-        else
-                l &= ~(1 << gpio);
-        __raw_writel(l, reg);
-}
-static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
-{
-        void __iomem *reg = bank->base;
-        u32 l = 0;
-        switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP1
-        case METHOD_MPUIO:
-                reg += OMAP_MPUIO_OUTPUT;
-                l = __raw_readl(reg);
-                if (enable)
-                        l |= 1 << gpio;
-                else
-                        l &= ~(1 << gpio);
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_DATA_OUTPUT;
-                l = __raw_readl(reg);
-                if (enable)
-                        l |= 1 << gpio;
-                else
-                        l &= ~(1 << gpio);
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-        case METHOD_GPIO_1610:
-                if (enable)
-                        reg += OMAP1610_GPIO_SET_DATAOUT;
-                else
-                        reg += OMAP1610_GPIO_CLEAR_DATAOUT;
-                l = 1 << gpio;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        case METHOD_GPIO_7XX:
-                reg += OMAP7XX_GPIO_DATA_OUTPUT;
-                l = __raw_readl(reg);
-                if (enable)
-                        l |= 1 << gpio;
-                else
-                        l &= ~(1 << gpio);
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-        case METHOD_GPIO_24XX:
-                if (enable)
-                        reg += OMAP24XX_GPIO_SETDATAOUT;
-                else
-                        reg += OMAP24XX_GPIO_CLEARDATAOUT;
-                l = 1 << gpio;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-        case METHOD_GPIO_44XX:
-                if (enable)
-                        reg += OMAP4_GPIO_SETDATAOUT;
-                else
-                        reg += OMAP4_GPIO_CLEARDATAOUT;
-                l = 1 << gpio;
-                break;
-#endif
-        default:
-                WARN_ON(1);
-                return;
-        }
-        __raw_writel(l, reg);
-}
-static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
-{
-        void __iomem *reg;
-        if (check_gpio(gpio) < 0)
-                return -EINVAL;
-        reg = bank->base;
-        switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP1
-        case METHOD_MPUIO:
-                reg += OMAP_MPUIO_INPUT_LATCH;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_DATA_INPUT;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-        case METHOD_GPIO_1610:
-                reg += OMAP1610_GPIO_DATAIN;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        case METHOD_GPIO_7XX:
-                reg += OMAP7XX_GPIO_DATA_INPUT;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-        case METHOD_GPIO_24XX:
-                reg += OMAP24XX_GPIO_DATAIN;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-        case METHOD_GPIO_44XX:
-                reg += OMAP4_GPIO_DATAIN;
-                break;
-#endif
-        default:
-                return -EINVAL;
-        }
-        return (__raw_readl(reg)
-                        & (1 << get_gpio_index(gpio))) != 0;
-}
-static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
-{
-        void __iomem *reg;
-        if (check_gpio(gpio) < 0)
-                return -EINVAL;
-        reg = bank->base;
-        switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP1
-        case METHOD_MPUIO:
-                reg += OMAP_MPUIO_OUTPUT;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_DATA_OUTPUT;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-        case METHOD_GPIO_1610:
-                reg += OMAP1610_GPIO_DATAOUT;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        case METHOD_GPIO_7XX:
-                reg += OMAP7XX_GPIO_DATA_OUTPUT;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-        case METHOD_GPIO_24XX:
-                reg += OMAP24XX_GPIO_DATAOUT;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-        case METHOD_GPIO_44XX:
-                reg += OMAP4_GPIO_DATAOUT;
-                break;
-#endif
-        default:
-                return -EINVAL;
-        }
-        return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
-}
-#define MOD_REG_BIT(reg, bit_mask, set) \
-do {    \
-        int l = __raw_readl(base + reg); \
-        if (set) l |= bit_mask; \
-        else l &= ~bit_mask; \
-        __raw_writel(l, base + reg); \
-} while(0)
-/**
- * _set_gpio_debounce - low level gpio debounce time
- * @bank: the gpio bank we're acting upon
- * @gpio: the gpio number on this @gpio
- * @debounce: debounce time to use
- *
- * OMAP's debounce time is in 31us steps so we need
- * to convert and round up to the closest unit.
- */
-static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
-                unsigned debounce)
-{
-        void __iomem            *reg = bank->base;
-        u32                     val;
-        u32                     l;
-        if (debounce < 32)
-                debounce = 0x01;
-        else if (debounce > 7936)
-                debounce = 0xff;
-        else
-                debounce = (debounce / 0x1f) - 1;
-        l = 1 << get_gpio_index(gpio);
-        if (cpu_is_omap44xx())
-                reg += OMAP4_GPIO_DEBOUNCINGTIME;
-        else
-                reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
-        __raw_writel(debounce, reg);
-        reg = bank->base;
-        if (cpu_is_omap44xx())
-                reg += OMAP4_GPIO_DEBOUNCENABLE;
-        else
-                reg += OMAP24XX_GPIO_DEBOUNCE_EN;
-        val = __raw_readl(reg);
-        if (debounce) {
-                val |= l;
-                if (cpu_is_omap34xx() || cpu_is_omap44xx())
-                        clk_enable(bank->dbck);
-        } else {
-                val &= ~l;
-                if (cpu_is_omap34xx() || cpu_is_omap44xx())
-                        clk_disable(bank->dbck);
-        }
-        bank->dbck_enable_mask = val;
-        __raw_writel(val, reg);
-}
-#ifdef CONFIG_ARCH_OMAP2PLUS
-static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
-                                                int trigger)
-{
-        void __iomem *base = bank->base;
-        u32 gpio_bit = 1 << gpio;
-        u32 val;
-        if (cpu_is_omap44xx()) {
-                MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
-                        trigger & IRQ_TYPE_LEVEL_LOW);
-                MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
-                        trigger & IRQ_TYPE_LEVEL_HIGH);
-                MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
-                        trigger & IRQ_TYPE_EDGE_RISING);
-                MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
-                        trigger & IRQ_TYPE_EDGE_FALLING);
-        } else {
-                MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
-                        trigger & IRQ_TYPE_LEVEL_LOW);
-                MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
-                        trigger & IRQ_TYPE_LEVEL_HIGH);
-                MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
-                        trigger & IRQ_TYPE_EDGE_RISING);
-                MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
-                        trigger & IRQ_TYPE_EDGE_FALLING);
-        }
-        if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
-                if (cpu_is_omap44xx()) {
-                        if (trigger != 0)
-                                __raw_writel(1 << gpio, bank->base+
-                                                OMAP4_GPIO_IRQWAKEN0);
-                        else {
-                                val = __raw_readl(bank->base +
-                                                        OMAP4_GPIO_IRQWAKEN0);
-                                __raw_writel(val & (~(1 << gpio)), bank->base +
-                                                         OMAP4_GPIO_IRQWAKEN0);
-                        }
-                } else {
-                        /*
-                         * GPIO wakeup request can only be generated on edge
-                         * transitions
-                         */
-                        if (trigger & IRQ_TYPE_EDGE_BOTH)
-                                __raw_writel(1 << gpio, bank->base
-                                        + OMAP24XX_GPIO_SETWKUENA);
-                        else
-                                __raw_writel(1 << gpio, bank->base
-                                        + OMAP24XX_GPIO_CLEARWKUENA);
-                }
-        }
-        /* This part needs to be executed always for OMAP34xx */
-        if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
-                /*
-                 * Log the edge gpio and manually trigger the IRQ
-                 * after resume if the input level changes
-                 * to avoid irq lost during PER RET/OFF mode
-                 * Applies for omap2 non-wakeup gpio and all omap3 gpios
-                 */
-                if (trigger & IRQ_TYPE_EDGE_BOTH)
-                        bank->enabled_non_wakeup_gpios |= gpio_bit;
-                else
-                        bank->enabled_non_wakeup_gpios &= ~gpio_bit;
-        }
-        if (cpu_is_omap44xx()) {
-                bank->level_mask =
-                        __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
-                        __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
-        } else {
-                bank->level_mask =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
-                        __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
-        }
-}
-#endif
-#ifdef CONFIG_ARCH_OMAP1
-/*
- * This only applies to chips that can't do both rising and falling edge
- * detection at once.  For all other chips, this function is a noop.
- */
-static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
-{
-        void __iomem *reg = bank->base;
-        u32 l = 0;
-        switch (bank->method) {
-        case METHOD_MPUIO:
-                reg += OMAP_MPUIO_GPIO_INT_EDGE;
-                break;
-#ifdef CONFIG_ARCH_OMAP15XX
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_INT_CONTROL;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        case METHOD_GPIO_7XX:
-                reg += OMAP7XX_GPIO_INT_CONTROL;
-                break;
-#endif
-        default:
-                return;
-        }
-        l = __raw_readl(reg);
-        if ((l >> gpio) & 1)
-                l &= ~(1 << gpio);
-        else
-                l |= 1 << gpio;
-        __raw_writel(l, reg);
-}
-#endif
-static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
-{
-        void __iomem *reg = bank->base;
-        u32 l = 0;
-        switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP1
-        case METHOD_MPUIO:
-                reg += OMAP_MPUIO_GPIO_INT_EDGE;
-                l = __raw_readl(reg);
-                if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
-                        bank->toggle_mask |= 1 << gpio;
-                if (trigger & IRQ_TYPE_EDGE_RISING)
-                        l |= 1 << gpio;
-                else if (trigger & IRQ_TYPE_EDGE_FALLING)
-                        l &= ~(1 << gpio);
-                else
-                        goto bad;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_INT_CONTROL;
-                l = __raw_readl(reg);
-                if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
-                        bank->toggle_mask |= 1 << gpio;
-                if (trigger & IRQ_TYPE_EDGE_RISING)
-                        l |= 1 << gpio;
-                else if (trigger & IRQ_TYPE_EDGE_FALLING)
-                        l &= ~(1 << gpio);
-                else
-                        goto bad;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-        case METHOD_GPIO_1610:
-                if (gpio & 0x08)
-                        reg += OMAP1610_GPIO_EDGE_CTRL2;
-                else
-                        reg += OMAP1610_GPIO_EDGE_CTRL1;
-                gpio &= 0x07;
-                l = __raw_readl(reg);
-                l &= ~(3 << (gpio << 1));
-                if (trigger & IRQ_TYPE_EDGE_RISING)
-                        l |= 2 << (gpio << 1);
-                if (trigger & IRQ_TYPE_EDGE_FALLING)
-                        l |= 1 << (gpio << 1);
-                if (trigger)
-                        /* Enable wake-up during idle for dynamic tick */
-                        __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
-                else
-                        __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        case METHOD_GPIO_7XX:
-                reg += OMAP7XX_GPIO_INT_CONTROL;
-                l = __raw_readl(reg);
-                if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
-                        bank->toggle_mask |= 1 << gpio;
-                if (trigger & IRQ_TYPE_EDGE_RISING)
-                        l |= 1 << gpio;
-                else if (trigger & IRQ_TYPE_EDGE_FALLING)
-                        l &= ~(1 << gpio);
-                else
-                        goto bad;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP2PLUS
-        case METHOD_GPIO_24XX:
-        case METHOD_GPIO_44XX:
-                set_24xx_gpio_triggering(bank, gpio, trigger);
-                break;
-#endif
-        default:
-                goto bad;
-        }
-        __raw_writel(l, reg);
-        return 0;
-bad:
-        return -EINVAL;
-}
-static int gpio_irq_type(unsigned irq, unsigned type)
-{
-        struct gpio_bank *bank;
-        unsigned gpio;
-        int retval;
-        unsigned long flags;
-        if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
-                gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
-        else
-                gpio = irq - IH_GPIO_BASE;
-        if (check_gpio(gpio) < 0)
-                return -EINVAL;
-        if (type & ~IRQ_TYPE_SENSE_MASK)
-                return -EINVAL;
-        /* OMAP1 allows only only edge triggering */
-        if (!cpu_class_is_omap2()
-                        && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
-                return -EINVAL;
-        bank = get_irq_chip_data(irq);
-        spin_lock_irqsave(&bank->lock, flags);
-        retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
-        if (retval == 0) {
-                irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
-                irq_desc[irq].status |= type;
-        }
-        spin_unlock_irqrestore(&bank->lock, flags);
-        if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
-                __set_irq_handler_unlocked(irq, handle_level_irq);
-        else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
-                __set_irq_handler_unlocked(irq, handle_edge_irq);
-        return retval;
-}
-static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
-{
-        void __iomem *reg = bank->base;
-        switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP1
-        case METHOD_MPUIO:
-                /* MPUIO irqstatus is reset by reading the status register,
-                 * so do nothing here */
-                return;
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_INT_STATUS;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-        case METHOD_GPIO_1610:
-                reg += OMAP1610_GPIO_IRQSTATUS1;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        case METHOD_GPIO_7XX:
-                reg += OMAP7XX_GPIO_INT_STATUS;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-        case METHOD_GPIO_24XX:
-                reg += OMAP24XX_GPIO_IRQSTATUS1;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
-        case METHOD_GPIO_44XX:
-                reg += OMAP4_GPIO_IRQSTATUS0;
-                break;
-#endif
-        default:
-                WARN_ON(1);
-                return;
-        }
-        __raw_writel(gpio_mask, reg);
-        /* Workaround for clearing DSP GPIO interrupts to allow retention */
-        if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
-        else if (cpu_is_omap44xx())
-                reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
-        if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                __raw_writel(gpio_mask, reg);
-        /* Flush posted write for the irq status to avoid spurious interrupts */
-        __raw_readl(reg);
-        }
-}
-static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
-{
-        _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
-}
-static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
-{
-        void __iomem *reg = bank->base;
-        int inv = 0;
-        u32 l;
-        u32 mask;
-        switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP1
-        case METHOD_MPUIO:
-                reg += OMAP_MPUIO_GPIO_MASKIT;
-                mask = 0xffff;
-                inv = 1;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_INT_MASK;
-                mask = 0xffff;
-                inv = 1;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-        case METHOD_GPIO_1610:
-                reg += OMAP1610_GPIO_IRQENABLE1;
-                mask = 0xffff;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        case METHOD_GPIO_7XX:
-                reg += OMAP7XX_GPIO_INT_MASK;
-                mask = 0xffffffff;
-                inv = 1;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-        case METHOD_GPIO_24XX:
-                reg += OMAP24XX_GPIO_IRQENABLE1;
-                mask = 0xffffffff;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
-        case METHOD_GPIO_44XX:
-                reg += OMAP4_GPIO_IRQSTATUSSET0;
-                mask = 0xffffffff;
-                break;
-#endif
-        default:
-                WARN_ON(1);
-                return 0;
-        }
-        l = __raw_readl(reg);
-        if (inv)
-                l = ~l;
-        l &= mask;
-        return l;
-}
-static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
-{
-        void __iomem *reg = bank->base;
-        u32 l;
-        switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP1
-        case METHOD_MPUIO:
-                reg += OMAP_MPUIO_GPIO_MASKIT;
-                l = __raw_readl(reg);
-                if (enable)
-                        l &= ~(gpio_mask);
-                else
-                        l |= gpio_mask;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_INT_MASK;
-                l = __raw_readl(reg);
-                if (enable)
-                        l &= ~(gpio_mask);
-                else
-                        l |= gpio_mask;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-        case METHOD_GPIO_1610:
-                if (enable)
-                        reg += OMAP1610_GPIO_SET_IRQENABLE1;
-                else
-                        reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
-                l = gpio_mask;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        case METHOD_GPIO_7XX:
-                reg += OMAP7XX_GPIO_INT_MASK;
-                l = __raw_readl(reg);
-                if (enable)
-                        l &= ~(gpio_mask);
-                else
-                        l |= gpio_mask;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-        case METHOD_GPIO_24XX:
-                if (enable)
-                        reg += OMAP24XX_GPIO_SETIRQENABLE1;
-                else
-                        reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
-                l = gpio_mask;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-        case METHOD_GPIO_44XX:
-                if (enable)
-                        reg += OMAP4_GPIO_IRQSTATUSSET0;
-                else
-                        reg += OMAP4_GPIO_IRQSTATUSCLR0;
-                l = gpio_mask;
-                break;
-#endif
-        default:
-                WARN_ON(1);
-                return;
-        }
-        __raw_writel(l, reg);
-}
-static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
-{
-        _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
-}
-/*
- * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
- * 1510 does not seem to have a wake-up register. If JTAG is connected
- * to the target, system will wake up always on GPIO events. While
- * system is running all registered GPIO interrupts need to have wake-up
- * enabled. When system is suspended, only selected GPIO interrupts need
- * to have wake-up enabled.
- */
-static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
-{
-        unsigned long uninitialized_var(flags);
-        switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP16XX
-        case METHOD_MPUIO:
-        case METHOD_GPIO_1610:
-                spin_lock_irqsave(&bank->lock, flags);
-                if (enable)
-                        bank->suspend_wakeup |= (1 << gpio);
-                else
-                        bank->suspend_wakeup &= ~(1 << gpio);
-                spin_unlock_irqrestore(&bank->lock, flags);
-                return 0;
-#endif
-#ifdef CONFIG_ARCH_OMAP2PLUS
-        case METHOD_GPIO_24XX:
-        case METHOD_GPIO_44XX:
-                if (bank->non_wakeup_gpios & (1 << gpio)) {
-                        printk(KERN_ERR "Unable to modify wakeup on "
-                                        "non-wakeup GPIO%d\n",
-                                        (bank - gpio_bank) * 32 + gpio);
-                        return -EINVAL;
-                }
-                spin_lock_irqsave(&bank->lock, flags);
-                if (enable)
-                        bank->suspend_wakeup |= (1 << gpio);
-                else
-                        bank->suspend_wakeup &= ~(1 << gpio);
-                spin_unlock_irqrestore(&bank->lock, flags);
-                return 0;
-#endif
-        default:
-                printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
-                       bank->method);
-                return -EINVAL;
-        }
-}
-static void _reset_gpio(struct gpio_bank *bank, int gpio)
-{
-        _set_gpio_direction(bank, get_gpio_index(gpio), 1);
-        _set_gpio_irqenable(bank, gpio, 0);
-        _clear_gpio_irqstatus(bank, gpio);
-        _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
-}
-/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
-static int gpio_wake_enable(unsigned int irq, unsigned int enable)
-{
-        unsigned int gpio = irq - IH_GPIO_BASE;
-        struct gpio_bank *bank;
-        int retval;
-        if (check_gpio(gpio) < 0)
-                return -ENODEV;
-        bank = get_irq_chip_data(irq);
-        retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
-        return retval;
-}
-static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
-{
-        struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
-        unsigned long flags;
-        spin_lock_irqsave(&bank->lock, flags);
-        /* Set trigger to none. You need to enable the desired trigger with
-         * request_irq() or set_irq_type().
-         */
-        _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
-#ifdef CONFIG_ARCH_OMAP15XX
-        if (bank->method == METHOD_GPIO_1510) {
-                void __iomem *reg;
-                /* Claim the pin for MPU */
-                reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
-                __raw_writel(__raw_readl(reg) | (1 << offset), reg);
-        }
-#endif
-        if (!cpu_class_is_omap1()) {
-                if (!bank->mod_usage) {
-                        void __iomem *reg = bank->base;
-                        u32 ctrl;
-                        if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                                reg += OMAP24XX_GPIO_CTRL;
-                        else if (cpu_is_omap44xx())
-                                reg += OMAP4_GPIO_CTRL;
-                        ctrl = __raw_readl(reg);
-                        /* Module is enabled, clocks are not gated */
-                        ctrl &= 0xFFFFFFFE;
-                        __raw_writel(ctrl, reg);
-                }
-                bank->mod_usage |= 1 << offset;
-        }
-        spin_unlock_irqrestore(&bank->lock, flags);
-        return 0;
-}
-static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
-{
-        struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
-        unsigned long flags;
-        spin_lock_irqsave(&bank->lock, flags);
-#ifdef CONFIG_ARCH_OMAP16XX
-        if (bank->method == METHOD_GPIO_1610) {
-                /* Disable wake-up during idle for dynamic tick */
-                void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
-                __raw_writel(1 << offset, reg);
-        }
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-        if (bank->method == METHOD_GPIO_24XX) {
-                /* Disable wake-up during idle for dynamic tick */
-                void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
-                __raw_writel(1 << offset, reg);
-        }
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-        if (bank->method == METHOD_GPIO_44XX) {
-                /* Disable wake-up during idle for dynamic tick */
-                void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
-                __raw_writel(1 << offset, reg);
-        }
-#endif
-        if (!cpu_class_is_omap1()) {
-                bank->mod_usage &= ~(1 << offset);
-                if (!bank->mod_usage) {
-                        void __iomem *reg = bank->base;
-                        u32 ctrl;
-                        if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                                reg += OMAP24XX_GPIO_CTRL;
-                        else if (cpu_is_omap44xx())
-                                reg += OMAP4_GPIO_CTRL;
-                        ctrl = __raw_readl(reg);
-                        /* Module is disabled, clocks are gated */
-                        ctrl |= 1;
-                        __raw_writel(ctrl, reg);
-                }
-        }
-        _reset_gpio(bank, bank->chip.base + offset);
-        spin_unlock_irqrestore(&bank->lock, flags);
-}
-/*
- * We need to unmask the GPIO bank interrupt as soon as possible to
- * avoid missing GPIO interrupts for other lines in the bank.
- * Then we need to mask-read-clear-unmask the triggered GPIO lines
- * in the bank to avoid missing nested interrupts for a GPIO line.
- * If we wait to unmask individual GPIO lines in the bank after the
- * line's interrupt handler has been run, we may miss some nested
- * interrupts.
- */
-static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-        void __iomem *isr_reg = NULL;
-        u32 isr;
-        unsigned int gpio_irq, gpio_index;
-        struct gpio_bank *bank;
-        u32 retrigger = 0;
-        int unmasked = 0;
-        desc->chip->ack(irq);
-        bank = get_irq_data(irq);
-#ifdef CONFIG_ARCH_OMAP1
-        if (bank->method == METHOD_MPUIO)
-                isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-        if (bank->method == METHOD_GPIO_1510)
-                isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
-#endif
-#if defined(CONFIG_ARCH_OMAP16XX)
-        if (bank->method == METHOD_GPIO_1610)
-                isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        if (bank->method == METHOD_GPIO_7XX)
-                isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-        if (bank->method == METHOD_GPIO_24XX)
-                isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
-        if (bank->method == METHOD_GPIO_44XX)
-                isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
-#endif
-        while(1) {
-                u32 isr_saved, level_mask = 0;
-                u32 enabled;
-                enabled = _get_gpio_irqbank_mask(bank);
-                isr_saved = isr = __raw_readl(isr_reg) & enabled;
-                if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
-                        isr &= 0x0000ffff;
-                if (cpu_class_is_omap2()) {
-                        level_mask = bank->level_mask & enabled;
-                }
-                /* clear edge sensitive interrupts before handler(s) are
-                called so that we don't miss any interrupt occurred while
-                executing them */
-                _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
-                _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
-                _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
-                /* if there is only edge sensitive GPIO pin interrupts
-                configured, we could unmask GPIO bank interrupt immediately */
-                if (!level_mask && !unmasked) {
-                        unmasked = 1;
-                        desc->chip->unmask(irq);
-                }
-                isr |= retrigger;
-                retrigger = 0;
-                if (!isr)
-                        break;
-                gpio_irq = bank->virtual_irq_start;
-                for (; isr != 0; isr >>= 1, gpio_irq++) {
-                        gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
-                        if (!(isr & 1))
-                                continue;
-#ifdef CONFIG_ARCH_OMAP1
-                        /*
-                         * Some chips can't respond to both rising and falling
-                         * at the same time.  If this irq was requested with
-                         * both flags, we need to flip the ICR data for the IRQ
-                         * to respond to the IRQ for the opposite direction.
-                         * This will be indicated in the bank toggle_mask.
-                         */
-                        if (bank->toggle_mask & (1 << gpio_index))
-                                _toggle_gpio_edge_triggering(bank, gpio_index);
-#endif
-                        generic_handle_irq(gpio_irq);
-                }
-        }
-        /* if bank has any level sensitive GPIO pin interrupt
-        configured, we must unmask the bank interrupt only after
-        handler(s) are executed in order to avoid spurious bank
-        interrupt */
-        if (!unmasked)
-                desc->chip->unmask(irq);
-}
-static void gpio_irq_shutdown(unsigned int irq)
-{
-        unsigned int gpio = irq - IH_GPIO_BASE;
-        struct gpio_bank *bank = get_irq_chip_data(irq);
-        _reset_gpio(bank, gpio);
-}
-static void gpio_ack_irq(unsigned int irq)
-{
-        unsigned int gpio = irq - IH_GPIO_BASE;
-        struct gpio_bank *bank = get_irq_chip_data(irq);
-        _clear_gpio_irqstatus(bank, gpio);
-}
-static void gpio_mask_irq(unsigned int irq)
-{
-        unsigned int gpio = irq - IH_GPIO_BASE;
-        struct gpio_bank *bank = get_irq_chip_data(irq);
-        _set_gpio_irqenable(bank, gpio, 0);
-        _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
-}
-static void gpio_unmask_irq(unsigned int irq)
-{
-        unsigned int gpio = irq - IH_GPIO_BASE;
-        struct gpio_bank *bank = get_irq_chip_data(irq);
-        unsigned int irq_mask = 1 << get_gpio_index(gpio);
-        struct irq_desc *desc = irq_to_desc(irq);
-        u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
-        if (trigger)
-                _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
-        /* For level-triggered GPIOs, the clearing must be done after
-         * the HW source is cleared, thus after the handler has run */
-        if (bank->level_mask & irq_mask) {
-                _set_gpio_irqenable(bank, gpio, 0);
-                _clear_gpio_irqstatus(bank, gpio);
-        }
-        _set_gpio_irqenable(bank, gpio, 1);
-}
-static struct irq_chip gpio_irq_chip = {
-        .name           = "GPIO",
-        .shutdown       = gpio_irq_shutdown,
-        .ack            = gpio_ack_irq,
-        .mask           = gpio_mask_irq,
-        .unmask         = gpio_unmask_irq,
-        .set_type       = gpio_irq_type,
-        .set_wake       = gpio_wake_enable,
-};
-/*---------------------------------------------------------------------*/
-#ifdef CONFIG_ARCH_OMAP1
-/* MPUIO uses the always-on 32k clock */
-static void mpuio_ack_irq(unsigned int irq)
-{
-        /* The ISR is reset automatically, so do nothing here. */
-}
-static void mpuio_mask_irq(unsigned int irq)
-{
-        unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
-        struct gpio_bank *bank = get_irq_chip_data(irq);
-        _set_gpio_irqenable(bank, gpio, 0);
-}
-static void mpuio_unmask_irq(unsigned int irq)
-{
-        unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
-        struct gpio_bank *bank = get_irq_chip_data(irq);
-        _set_gpio_irqenable(bank, gpio, 1);
-}
-static struct irq_chip mpuio_irq_chip = {
-        .name           = "MPUIO",
-        .ack            = mpuio_ack_irq,
-        .mask           = mpuio_mask_irq,
-        .unmask         = mpuio_unmask_irq,
-        .set_type       = gpio_irq_type,
-#ifdef CONFIG_ARCH_OMAP16XX
-        /* REVISIT: assuming only 16xx supports MPUIO wake events */
-        .set_wake       = gpio_wake_enable,
-#endif
-};
-#define bank_is_mpuio(bank)     ((bank)->method == METHOD_MPUIO)
-#ifdef CONFIG_ARCH_OMAP16XX
-#include <linux/platform_device.h>
-static int omap_mpuio_suspend_noirq(struct device *dev)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct gpio_bank        *bank = platform_get_drvdata(pdev);
-        void __iomem            *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
-        unsigned long           flags;
-        spin_lock_irqsave(&bank->lock, flags);
-        bank->saved_wakeup = __raw_readl(mask_reg);
-        __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
-        spin_unlock_irqrestore(&bank->lock, flags);
-        return 0;
-}
-static int omap_mpuio_resume_noirq(struct device *dev)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct gpio_bank        *bank = platform_get_drvdata(pdev);
-        void __iomem            *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
-        unsigned long           flags;
-        spin_lock_irqsave(&bank->lock, flags);
-        __raw_writel(bank->saved_wakeup, mask_reg);
-        spin_unlock_irqrestore(&bank->lock, flags);
-        return 0;
-}
-static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
-        .suspend_noirq = omap_mpuio_suspend_noirq,
-        .resume_noirq = omap_mpuio_resume_noirq,
-};
-/* use platform_driver for this, now that there's no longer any
- * point to sys_device (other than not disturbing old code).
- */
-static struct platform_driver omap_mpuio_driver = {
-        .driver         = {
-                .name   = "mpuio",
-                .pm     = &omap_mpuio_dev_pm_ops,
-        },
-};
-static struct platform_device omap_mpuio_device = {
-        .name           = "mpuio",
-        .id             = -1,
-        .dev = {
-                .driver = &omap_mpuio_driver.driver,
-        }
-        /* could list the /proc/iomem resources */
-};
-static inline void mpuio_init(void)
-{
-        platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
-        if (platform_driver_register(&omap_mpuio_driver) == 0)
-                (void) platform_device_register(&omap_mpuio_device);
-}
-#else
-static inline void mpuio_init(void) {}
-#endif  /* 16xx */
-#else
-extern struct irq_chip mpuio_irq_chip;
-#define bank_is_mpuio(bank)     0
-static inline void mpuio_init(void) {}
-#endif
-/*---------------------------------------------------------------------*/
-/* REVISIT these are stupid implementations!  replace by ones that
- * don't switch on METHOD_* and which mostly avoid spinlocks
- */
-static int gpio_input(struct gpio_chip *chip, unsigned offset)
-{
-        struct gpio_bank *bank;
-        unsigned long flags;
-        bank = container_of(chip, struct gpio_bank, chip);
-        spin_lock_irqsave(&bank->lock, flags);
-        _set_gpio_direction(bank, offset, 1);
-        spin_unlock_irqrestore(&bank->lock, flags);
-        return 0;
-}
-static int gpio_is_input(struct gpio_bank *bank, int mask)
-{
-        void __iomem *reg = bank->base;
-        switch (bank->method) {
-        case METHOD_MPUIO:
-                reg += OMAP_MPUIO_IO_CNTL;
-                break;
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_DIR_CONTROL;
-                break;
-        case METHOD_GPIO_1610:
-                reg += OMAP1610_GPIO_DIRECTION;
-                break;
-        case METHOD_GPIO_7XX:
-                reg += OMAP7XX_GPIO_DIR_CONTROL;
-                break;
-        case METHOD_GPIO_24XX:
-                reg += OMAP24XX_GPIO_OE;
-                break;
-        case METHOD_GPIO_44XX:
-                reg += OMAP4_GPIO_OE;
-                break;
-        default:
-                WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
-                return -EINVAL;
-        }
-        return __raw_readl(reg) & mask;
-}
-static int gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-        struct gpio_bank *bank;
-        void __iomem *reg;
-        int gpio;
-        u32 mask;
-        gpio = chip->base + offset;
-        bank = get_gpio_bank(gpio);
-        reg = bank->base;
-        mask = 1 << get_gpio_index(gpio);
-        if (gpio_is_input(bank, mask))
-                return _get_gpio_datain(bank, gpio);
-        else
-                return _get_gpio_dataout(bank, gpio);
-}
-static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
-{
-        struct gpio_bank *bank;
-        unsigned long flags;
-        bank = container_of(chip, struct gpio_bank, chip);
-        spin_lock_irqsave(&bank->lock, flags);
-        _set_gpio_dataout(bank, offset, value);
-        _set_gpio_direction(bank, offset, 0);
-        spin_unlock_irqrestore(&bank->lock, flags);
-        return 0;
-}
-static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
-                unsigned debounce)
-{
-        struct gpio_bank *bank;
-        unsigned long flags;
-        bank = container_of(chip, struct gpio_bank, chip);
-        spin_lock_irqsave(&bank->lock, flags);
-        _set_gpio_debounce(bank, offset, debounce);
-        spin_unlock_irqrestore(&bank->lock, flags);
-        return 0;
-}
-static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
-        struct gpio_bank *bank;
-        unsigned long flags;
-        bank = container_of(chip, struct gpio_bank, chip);
-        spin_lock_irqsave(&bank->lock, flags);
-        _set_gpio_dataout(bank, offset, value);
-        spin_unlock_irqrestore(&bank->lock, flags);
-}
-static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
-{
-        struct gpio_bank *bank;
-        bank = container_of(chip, struct gpio_bank, chip);
-        return bank->virtual_irq_start + offset;
-}
-/*---------------------------------------------------------------------*/
-static int initialized;
-#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
-static struct clk * gpio_ick;
-#endif
-#if defined(CONFIG_ARCH_OMAP2)
-static struct clk * gpio_fck;
-#endif
-#if defined(CONFIG_ARCH_OMAP2430)
-static struct clk * gpio5_ick;
-static struct clk * gpio5_fck;
-#endif
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
-#endif
-static void __init omap_gpio_show_rev(void)
-{
-        u32 rev;
-        if (cpu_is_omap16xx())
-                rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
-        else if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
-        else if (cpu_is_omap44xx())
-                rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
-        else
-                return;
-        printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
-                (rev >> 4) & 0x0f, rev & 0x0f);
-}
-/* This lock class tells lockdep that GPIO irqs are in a different
- * category than their parents, so it won't report false recursion.
- */
-static struct lock_class_key gpio_lock_class;
-static int __init _omap_gpio_init(void)
-{
-        int i;
-        int gpio = 0;
-        struct gpio_bank *bank;
-        int bank_size = SZ_8K;  /* Module 4KB + L4 4KB except on omap1 */
-        char clk_name[11];
-        initialized = 1;
-#if defined(CONFIG_ARCH_OMAP1)
-        if (cpu_is_omap15xx()) {
-                gpio_ick = clk_get(NULL, "arm_gpio_ck");
-                if (IS_ERR(gpio_ick))
-                        printk("Could not get arm_gpio_ck\n");
-                else
-                        clk_enable(gpio_ick);
-        }
-#endif
-#if defined(CONFIG_ARCH_OMAP2)
-        if (cpu_class_is_omap2()) {
-                gpio_ick = clk_get(NULL, "gpios_ick");
-                if (IS_ERR(gpio_ick))
-                        printk("Could not get gpios_ick\n");
-                else
-                        clk_enable(gpio_ick);
-                gpio_fck = clk_get(NULL, "gpios_fck");
-                if (IS_ERR(gpio_fck))
-                        printk("Could not get gpios_fck\n");
-                else
-                        clk_enable(gpio_fck);
-                /*
-                 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
-                 */
-#if defined(CONFIG_ARCH_OMAP2430)
-                if (cpu_is_omap2430()) {
-                        gpio5_ick = clk_get(NULL, "gpio5_ick");
-                        if (IS_ERR(gpio5_ick))
-                                printk("Could not get gpio5_ick\n");
-                        else
-                                clk_enable(gpio5_ick);
-                        gpio5_fck = clk_get(NULL, "gpio5_fck");
-                        if (IS_ERR(gpio5_fck))
-                                printk("Could not get gpio5_fck\n");
-                        else
-                                clk_enable(gpio5_fck);
-                }
-#endif
-        }
-#endif
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
-                        sprintf(clk_name, "gpio%d_ick", i + 1);
-                        gpio_iclks[i] = clk_get(NULL, clk_name);
-                        if (IS_ERR(gpio_iclks[i]))
-                                printk(KERN_ERR "Could not get %s\n", clk_name);
-                        else
-                                clk_enable(gpio_iclks[i]);
-                }
-        }
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-        if (cpu_is_omap15xx()) {
-                gpio_bank_count = 2;
-                gpio_bank = gpio_bank_1510;
-                bank_size = SZ_2K;
-        }
-#endif
-#if defined(CONFIG_ARCH_OMAP16XX)
-        if (cpu_is_omap16xx()) {
-                gpio_bank_count = 5;
-                gpio_bank = gpio_bank_1610;
-                bank_size = SZ_2K;
-        }
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        if (cpu_is_omap7xx()) {
-                gpio_bank_count = 7;
-                gpio_bank = gpio_bank_7xx;
-                bank_size = SZ_2K;
-        }
-#endif
-#ifdef CONFIG_ARCH_OMAP2
-        if (cpu_is_omap242x()) {
-                gpio_bank_count = 4;
-                gpio_bank = gpio_bank_242x;
-        }
-        if (cpu_is_omap243x()) {
-                gpio_bank_count = 5;
-                gpio_bank = gpio_bank_243x;
-        }
-#endif
-#ifdef CONFIG_ARCH_OMAP3
-        if (cpu_is_omap34xx()) {
-                gpio_bank_count = OMAP34XX_NR_GPIOS;
-                gpio_bank = gpio_bank_34xx;
-        }
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-        if (cpu_is_omap44xx()) {
-                gpio_bank_count = OMAP34XX_NR_GPIOS;
-                gpio_bank = gpio_bank_44xx;
-        }
-#endif
-        for (i = 0; i < gpio_bank_count; i++) {
-                int j, gpio_count = 16;
-                bank = &gpio_bank[i];
-                spin_lock_init(&bank->lock);
-                /* Static mapping, never released */
-                bank->base = ioremap(bank->pbase, bank_size);
-                if (!bank->base) {
-                        printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
-                        continue;
-                }
-                if (bank_is_mpuio(bank))
-                        __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
-                if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
-                        __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
-                        __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
-                }
-                if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
-                        __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
-                        __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
-                        __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
-                }
-                if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
-                        __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
-                        __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
-                        gpio_count = 32; /* 7xx has 32-bit GPIOs */
-                }
-#ifdef CONFIG_ARCH_OMAP2PLUS
-                if ((bank->method == METHOD_GPIO_24XX) ||
-                                (bank->method == METHOD_GPIO_44XX)) {
-                        static const u32 non_wakeup_gpios[] = {
-                                0xe203ffc0, 0x08700040
-                        };
-                        if (cpu_is_omap44xx()) {
-                                __raw_writel(0xffffffff, bank->base +
-                                                OMAP4_GPIO_IRQSTATUSCLR0);
-                                __raw_writew(0x0015, bank->base +
-                                                OMAP4_GPIO_SYSCONFIG);
-                                __raw_writel(0x00000000, bank->base +
-                                                 OMAP4_GPIO_DEBOUNCENABLE);
-                                /*
-                                 * Initialize interface clock ungated,
-                                 * module enabled
-                                 */
-                                __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
-                        } else {
-                                __raw_writel(0x00000000, bank->base +
-                                                OMAP24XX_GPIO_IRQENABLE1);
-                                __raw_writel(0xffffffff, bank->base +
-                                                OMAP24XX_GPIO_IRQSTATUS1);
-                                __raw_writew(0x0015, bank->base +
-                                                OMAP24XX_GPIO_SYSCONFIG);
-                                __raw_writel(0x00000000, bank->base +
-                                                OMAP24XX_GPIO_DEBOUNCE_EN);
-                                /*
-                                 * Initialize interface clock ungated,
-                                 * module enabled
-                                 */
-                                __raw_writel(0, bank->base +
-                                                OMAP24XX_GPIO_CTRL);
-                        }
-                        if (cpu_is_omap24xx() &&
-                            i < ARRAY_SIZE(non_wakeup_gpios))
-                                bank->non_wakeup_gpios = non_wakeup_gpios[i];
-                        gpio_count = 32;
-                }
-#endif
-                bank->mod_usage = 0;
-                /* REVISIT eventually switch from OMAP-specific gpio structs
-                 * over to the generic ones
-                 */
-                bank->chip.request = omap_gpio_request;
-                bank->chip.free = omap_gpio_free;
-                bank->chip.direction_input = gpio_input;
-                bank->chip.get = gpio_get;
-                bank->chip.direction_output = gpio_output;
-                bank->chip.set_debounce = gpio_debounce;
-                bank->chip.set = gpio_set;
-                bank->chip.to_irq = gpio_2irq;
-                if (bank_is_mpuio(bank)) {
-                        bank->chip.label = "mpuio";
-#ifdef CONFIG_ARCH_OMAP16XX
-                        bank->chip.dev = &omap_mpuio_device.dev;
-#endif
-                        bank->chip.base = OMAP_MPUIO(0);
-                } else {
-                        bank->chip.label = "gpio";
-                        bank->chip.base = gpio;
-                        gpio += gpio_count;
-                }
-                bank->chip.ngpio = gpio_count;
-                gpiochip_add(&bank->chip);
-                for (j = bank->virtual_irq_start;
-                     j < bank->virtual_irq_start + gpio_count; j++) {
-                        lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
-                        set_irq_chip_data(j, bank);
-                        if (bank_is_mpuio(bank))
-                                set_irq_chip(j, &mpuio_irq_chip);
-                        else
-                                set_irq_chip(j, &gpio_irq_chip);
-                        set_irq_handler(j, handle_simple_irq);
-                        set_irq_flags(j, IRQF_VALID);
-                }
-                set_irq_chained_handler(bank->irq, gpio_irq_handler);
-                set_irq_data(bank->irq, bank);
-                if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                        sprintf(clk_name, "gpio%d_dbck", i + 1);
-                        bank->dbck = clk_get(NULL, clk_name);
-                        if (IS_ERR(bank->dbck))
-                                printk(KERN_ERR "Could not get %s\n", clk_name);
-                }
-        }
-        /* Enable system clock for GPIO module.
-         * The CAM_CLK_CTRL *is* really the right place. */
-        if (cpu_is_omap16xx())
-                omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
-        /* Enable autoidle for the OCP interface */
-        if (cpu_is_omap24xx())
-                omap_writel(1 << 0, 0x48019010);
-        if (cpu_is_omap34xx())
-                omap_writel(1 << 0, 0x48306814);
-        omap_gpio_show_rev();
-        return 0;
-}
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
-static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
-{
-        int i;
-        if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
-                return 0;
-        for (i = 0; i < gpio_bank_count; i++) {
-                struct gpio_bank *bank = &gpio_bank[i];
-                void __iomem *wake_status;
-                void __iomem *wake_clear;
-                void __iomem *wake_set;
-                unsigned long flags;
-                switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP16XX
-                case METHOD_GPIO_1610:
-                        wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
-                        wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
-                        wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
-                        break;
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-                case METHOD_GPIO_24XX:
-                        wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
-                        wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
-                        wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
-                        break;
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-                case METHOD_GPIO_44XX:
-                        wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
-                        wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
-                        wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
-                        break;
-#endif
-                default:
-                        continue;
-                }
-                spin_lock_irqsave(&bank->lock, flags);
-                bank->saved_wakeup = __raw_readl(wake_status);
-                __raw_writel(0xffffffff, wake_clear);
-                __raw_writel(bank->suspend_wakeup, wake_set);
-                spin_unlock_irqrestore(&bank->lock, flags);
-        }
-        return 0;
-}
-static int omap_gpio_resume(struct sys_device *dev)
-{
-        int i;
-        if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
-                return 0;
-        for (i = 0; i < gpio_bank_count; i++) {
-                struct gpio_bank *bank = &gpio_bank[i];
-                void __iomem *wake_clear;
-                void __iomem *wake_set;
-                unsigned long flags;
-                switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP16XX
-                case METHOD_GPIO_1610:
-                        wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
-                        wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
-                        break;
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-                case METHOD_GPIO_24XX:
-                        wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
-                        wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
-                        break;
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-                case METHOD_GPIO_44XX:
-                        wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
-                        wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
-                        break;
-#endif
-                default:
-                        continue;
-                }
-                spin_lock_irqsave(&bank->lock, flags);
-                __raw_writel(0xffffffff, wake_clear);
-                __raw_writel(bank->saved_wakeup, wake_set);
-                spin_unlock_irqrestore(&bank->lock, flags);
-        }
-        return 0;
-}
-static struct sysdev_class omap_gpio_sysclass = {
-        .name           = "gpio",
-        .suspend        = omap_gpio_suspend,
-        .resume         = omap_gpio_resume,
-};
-static struct sys_device omap_gpio_device = {
-        .id             = 0,
-        .cls            = &omap_gpio_sysclass,
-};
-#endif
-#ifdef CONFIG_ARCH_OMAP2PLUS
-static int workaround_enabled;
-void omap2_gpio_prepare_for_idle(int power_state)
-{
-        int i, c = 0;
-        int min = 0;
-        if (cpu_is_omap34xx())
-                min = 1;
-        for (i = min; i < gpio_bank_count; i++) {
-                struct gpio_bank *bank = &gpio_bank[i];
-                u32 l1, l2;
-                if (bank->dbck_enable_mask)
-                        clk_disable(bank->dbck);
-                if (power_state > PWRDM_POWER_OFF)
-                        continue;
-                /* If going to OFF, remove triggering for all
-                 * non-wakeup GPIOs.  Otherwise spurious IRQs will be
-                 * generated.  See OMAP2420 Errata item 1.101. */
-                if (!(bank->enabled_non_wakeup_gpios))
-                        continue;
-                if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-                        bank->saved_datain = __raw_readl(bank->base +
-                                        OMAP24XX_GPIO_DATAIN);
-                        l1 = __raw_readl(bank->base +
-                                        OMAP24XX_GPIO_FALLINGDETECT);
-                        l2 = __raw_readl(bank->base +
-                                        OMAP24XX_GPIO_RISINGDETECT);
-                }
-                if (cpu_is_omap44xx()) {
-                        bank->saved_datain = __raw_readl(bank->base +
-                                                OMAP4_GPIO_DATAIN);
-                        l1 = __raw_readl(bank->base +
-                                                OMAP4_GPIO_FALLINGDETECT);
-                        l2 = __raw_readl(bank->base +
-                                                OMAP4_GPIO_RISINGDETECT);
-                }
-                bank->saved_fallingdetect = l1;
-                bank->saved_risingdetect = l2;
-                l1 &= ~bank->enabled_non_wakeup_gpios;
-                l2 &= ~bank->enabled_non_wakeup_gpios;
-                if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-                        __raw_writel(l1, bank->base +
-                                        OMAP24XX_GPIO_FALLINGDETECT);
-                        __raw_writel(l2, bank->base +
-                                        OMAP24XX_GPIO_RISINGDETECT);
-                }
-                if (cpu_is_omap44xx()) {
-                        __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
-                        __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
-                }
-                c++;
-        }
-        if (!c) {
-                workaround_enabled = 0;
-                return;
-        }
-        workaround_enabled = 1;
-}
-void omap2_gpio_resume_after_idle(void)
-{
-        int i;
-        int min = 0;
-        if (cpu_is_omap34xx())
-                min = 1;
-        for (i = min; i < gpio_bank_count; i++) {
-                struct gpio_bank *bank = &gpio_bank[i];
-                u32 l, gen, gen0, gen1;
-                if (bank->dbck_enable_mask)
-                        clk_enable(bank->dbck);
-                if (!workaround_enabled)
-                        continue;
-                if (!(bank->enabled_non_wakeup_gpios))
-                        continue;
-                if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-                        __raw_writel(bank->saved_fallingdetect,
-                                 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
-                        __raw_writel(bank->saved_risingdetect,
-                                 bank->base + OMAP24XX_GPIO_RISINGDETECT);
-                        l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
-                }
-                if (cpu_is_omap44xx()) {
-                        __raw_writel(bank->saved_fallingdetect,
-                                 bank->base + OMAP4_GPIO_FALLINGDETECT);
-                        __raw_writel(bank->saved_risingdetect,
-                                 bank->base + OMAP4_GPIO_RISINGDETECT);
-                        l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
-                }
-                /* Check if any of the non-wakeup interrupt GPIOs have changed
-                 * state.  If so, generate an IRQ by software.  This is
-                 * horribly racy, but it's the best we can do to work around
-                 * this silicon bug. */
-                l ^= bank->saved_datain;
-                l &= bank->enabled_non_wakeup_gpios;
-                /*
-                 * No need to generate IRQs for the rising edge for gpio IRQs
-                 * configured with falling edge only; and vice versa.
-                 */
-                gen0 = l & bank->saved_fallingdetect;
-                gen0 &= bank->saved_datain;
-                gen1 = l & bank->saved_risingdetect;
-                gen1 &= ~(bank->saved_datain);
-                /* FIXME: Consider GPIO IRQs with level detections properly! */
-                gen = l & (~(bank->saved_fallingdetect) &
-                                ~(bank->saved_risingdetect));
-                /* Consider all GPIO IRQs needed to be updated */
-                gen |= gen0 | gen1;
-                if (gen) {
-                        u32 old0, old1;
-                        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-                                old0 = __raw_readl(bank->base +
-                                        OMAP24XX_GPIO_LEVELDETECT0);
-                                old1 = __raw_readl(bank->base +
-                                        OMAP24XX_GPIO_LEVELDETECT1);
-                                __raw_writel(old0 | gen, bank->base +
-                                        OMAP24XX_GPIO_LEVELDETECT0);
-                                __raw_writel(old1 | gen, bank->base +
-                                        OMAP24XX_GPIO_LEVELDETECT1);
-                                __raw_writel(old0, bank->base +
-                                        OMAP24XX_GPIO_LEVELDETECT0);
-                                __raw_writel(old1, bank->base +
-                                        OMAP24XX_GPIO_LEVELDETECT1);
-                        }
-                        if (cpu_is_omap44xx()) {
-                                old0 = __raw_readl(bank->base +
-                                                OMAP4_GPIO_LEVELDETECT0);
-                                old1 = __raw_readl(bank->base +
-                                                OMAP4_GPIO_LEVELDETECT1);
-                                __raw_writel(old0 | l, bank->base +
-                                                OMAP4_GPIO_LEVELDETECT0);
-                                __raw_writel(old1 | l, bank->base +
-                                                OMAP4_GPIO_LEVELDETECT1);
-                                __raw_writel(old0, bank->base +
-                                                OMAP4_GPIO_LEVELDETECT0);
-                                __raw_writel(old1, bank->base +
-                                                OMAP4_GPIO_LEVELDETECT1);
-                        }
-                }
-        }
-}
-#endif
-#ifdef CONFIG_ARCH_OMAP3
-/* save the registers of bank 2-6 */
-void omap_gpio_save_context(void)
-{
-        int i;
-        /* saving banks from 2-6 only since GPIO1 is in WKUP */
-        for (i = 1; i < gpio_bank_count; i++) {
-                struct gpio_bank *bank = &gpio_bank[i];
-                gpio_context[i].sysconfig =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
-                gpio_context[i].irqenable1 =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
-                gpio_context[i].irqenable2 =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
-                gpio_context[i].wake_en =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
-                gpio_context[i].ctrl =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
-                gpio_context[i].oe =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_OE);
-                gpio_context[i].leveldetect0 =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
-                gpio_context[i].leveldetect1 =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
-                gpio_context[i].risingdetect =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
-                gpio_context[i].fallingdetect =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
-                gpio_context[i].dataout =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
-        }
-}
-/* restore the required registers of bank 2-6 */
-void omap_gpio_restore_context(void)
-{
-        int i;
-        for (i = 1; i < gpio_bank_count; i++) {
-                struct gpio_bank *bank = &gpio_bank[i];
-                __raw_writel(gpio_context[i].sysconfig,
-                                bank->base + OMAP24XX_GPIO_SYSCONFIG);
-                __raw_writel(gpio_context[i].irqenable1,
-                                bank->base + OMAP24XX_GPIO_IRQENABLE1);
-                __raw_writel(gpio_context[i].irqenable2,
-                                bank->base + OMAP24XX_GPIO_IRQENABLE2);
-                __raw_writel(gpio_context[i].wake_en,
-                                bank->base + OMAP24XX_GPIO_WAKE_EN);
-                __raw_writel(gpio_context[i].ctrl,
-                                bank->base + OMAP24XX_GPIO_CTRL);
-                __raw_writel(gpio_context[i].oe,
-                                bank->base + OMAP24XX_GPIO_OE);
-                __raw_writel(gpio_context[i].leveldetect0,
-                                bank->base + OMAP24XX_GPIO_LEVELDETECT0);
-                __raw_writel(gpio_context[i].leveldetect1,
-                                bank->base + OMAP24XX_GPIO_LEVELDETECT1);
-                __raw_writel(gpio_context[i].risingdetect,
-                                bank->base + OMAP24XX_GPIO_RISINGDETECT);
-                __raw_writel(gpio_context[i].fallingdetect,
-                                bank->base + OMAP24XX_GPIO_FALLINGDETECT);
-                __raw_writel(gpio_context[i].dataout,
-                                bank->base + OMAP24XX_GPIO_DATAOUT);
-        }
-}
-#endif
-/*
- * This may get called early from board specific init
- * for boards that have interrupts routed via FPGA.
- */
-int __init omap_gpio_init(void)
-{
-        if (!initialized)
-                return _omap_gpio_init();
-        else
-                return 0;
-}
-static int __init omap_gpio_sysinit(void)
-{
-        int ret = 0;
-        if (!initialized)
-                ret = _omap_gpio_init();
-        mpuio_init();
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
-        if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
-                if (ret == 0) {
-                        ret = sysdev_class_register(&omap_gpio_sysclass);
-                        if (ret == 0)
-                                ret = sysdev_register(&omap_gpio_device);
-                }
-        }
-#endif
-        return ret;
-}
-arch_initcall(omap_gpio_sysinit);
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index a5ce4f0aad35..3341ca4703e9 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -27,20 +27,20 @@
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
 #include <linux/i2c-omap.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/clk.h>
 #include <mach/irqs.h>
 #include <plat/mux.h>
 #include <plat/i2c.h>
 #include <plat/omap-pm.h>
+#include <plat/omap_device.h>
 #define OMAP_I2C_SIZE           0x3f
 #define OMAP1_I2C_BASE          0xfffb3800
-#define OMAP2_I2C_BASE1         0x48070000
-#define OMAP2_I2C_BASE2         0x48072000
-#define OMAP2_I2C_BASE3         0x48060000
-#define OMAP4_I2C_BASE4         0x48350000
-static const char name[] = "i2c_omap";
+static const char name[] = "omap_i2c";
 #define I2C_RESOURCE_BUILDER(base, irq)                 \
        {                                               \
@@ -55,15 +55,6 @@ static const char name[] = "i2c_omap";
 static struct resource i2c_resources[][2] = {
        { I2C_RESOURCE_BUILDER(0, 0) },
-#if     defined(CONFIG_ARCH_OMAP2PLUS)
-        { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, 0) },
-#endif
-#if     defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-        { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, 0) },
-#endif
-#if     defined(CONFIG_ARCH_OMAP4)
-        { I2C_RESOURCE_BUILDER(OMAP4_I2C_BASE4, 0) },
-#endif
 };
 #define I2C_DEV_BUILDER(bus_id, res, data)              \
@@ -77,18 +68,11 @@ static struct resource i2c_resources[][2] = {
                },                                      \
        }
-static struct omap_i2c_bus_platform_data i2c_pdata[ARRAY_SIZE(i2c_resources)];
+#define MAX_OMAP_I2C_HWMOD_NAME_LEN     16
+#define OMAP_I2C_MAX_CONTROLLERS 4
+static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS];
 static struct platform_device omap_i2c_devices[] = {
        I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]),
-#if     defined(CONFIG_ARCH_OMAP2PLUS)
-        I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_pdata[1]),
-#endif
-#if     defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-        I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_pdata[2]),
-#endif
-#if     defined(CONFIG_ARCH_OMAP4)
-        I2C_DEV_BUILDER(4, i2c_resources[3], &i2c_pdata[3]),
-#endif
 };
 #define OMAP_I2C_CMDLINE_SETUP  (BIT(31))
@@ -109,35 +93,26 @@ static int __init omap_i2c_nr_ports(void)
        return ports;
 }
-/* Shared between omap2 and 3 */
+static inline int omap1_i2c_add_bus(int bus_id)
-static resource_size_t omap2_i2c_irq[3] __initdata = {
-        INT_24XX_I2C1_IRQ,
-        INT_24XX_I2C2_IRQ,
-        INT_34XX_I2C3_IRQ,
-};
-static resource_size_t omap4_i2c_irq[4] __initdata = {
-        OMAP44XX_IRQ_I2C1,
-        OMAP44XX_IRQ_I2C2,
-        OMAP44XX_IRQ_I2C3,
-        OMAP44XX_IRQ_I2C4,
-};
-static inline int omap1_i2c_add_bus(struct platform_device *pdev, int bus_id)
 {
-        struct omap_i2c_bus_platform_data *pd;
+        struct platform_device *pdev;
+        struct omap_i2c_bus_platform_data *pdata;
        struct resource *res;
-        pd = pdev->dev.platform_data;
+        omap1_i2c_mux_pins(bus_id);
+        pdev = &omap_i2c_devices[bus_id - 1];
        res = pdev->resource;
        res[0].start = OMAP1_I2C_BASE;
        res[0].end = res[0].start + OMAP_I2C_SIZE;
        res[1].start = INT_I2C;
-        omap1_i2c_mux_pins(bus_id);
+        pdata = &i2c_pdata[bus_id - 1];
        return platform_device_register(pdev);
 }
+#ifdef CONFIG_ARCH_OMAP2PLUS
 /*
 * XXX This function is a temporary compatibility wrapper - only
 * needed until the I2C driver can be converted to call
@@ -148,52 +123,63 @@ static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
        omap_pm_set_max_mpu_wakeup_lat(dev, t);
 }
-static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id)
+static struct omap_device_pm_latency omap_i2c_latency[] = {
-{
+        [0] = {
-        struct resource *res;
+                .deactivate_func        = omap_device_idle_hwmods,
-        resource_size_t *irq;
+                .activate_func          = omap_device_enable_hwmods,
+                .flags                  = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        },
+};
-        res = pdev->resource;
+static inline int omap2_i2c_add_bus(int bus_id)
+{
+        int l;
+        struct omap_hwmod *oh;
+        struct omap_device *od;
+        char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
+        struct omap_i2c_bus_platform_data *pdata;
-        if (!cpu_is_omap44xx())
+        omap2_i2c_mux_pins(bus_id);
-                irq = omap2_i2c_irq;
-        else
-                irq = omap4_i2c_irq;
-        if (bus_id == 1) {
+        l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);
-                res[0].start = OMAP2_I2C_BASE1;
+        WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN,
-                res[0].end = res[0].start + OMAP_I2C_SIZE;
+                "String buffer overflow in I2C%d device setup\n", bus_id);
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                        pr_err("Could not look up %s\n", oh_name);
+                        return -EEXIST;
        }
-        res[1].start = irq[bus_id - 1];
+        pdata = &i2c_pdata[bus_id - 1];
-        omap2_i2c_mux_pins(bus_id);
        /*
         * When waiting for completion of a i2c transfer, we need to
         * set a wake up latency constraint for the MPU. This is to
         * ensure quick enough wakeup from idle, when transfer
         * completes.
+         * Only omap3 has support for constraints
         */
-        if (cpu_is_omap34xx()) {
+        if (cpu_is_omap34xx())
-                struct omap_i2c_bus_platform_data *pd;
+                pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
+        od = omap_device_build(name, bus_id, oh, pdata,
-                pd = pdev->dev.platform_data;
+                        sizeof(struct omap_i2c_bus_platform_data),
-                pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
+                        omap_i2c_latency, ARRAY_SIZE(omap_i2c_latency), 0);
-        }
+        WARN(IS_ERR(od), "Could not build omap_device for %s\n", name);
-        return platform_device_register(pdev);
+        return PTR_ERR(od);
 }
+#else
+static inline int omap2_i2c_add_bus(int bus_id)
+{
+        return 0;
+}
+#endif
 static int __init omap_i2c_add_bus(int bus_id)
 {
-        struct platform_device *pdev;
-        pdev = &omap_i2c_devices[bus_id - 1];
        if (cpu_class_is_omap1())
-                return omap1_i2c_add_bus(pdev, bus_id);
+                return omap1_i2c_add_bus(bus_id);
        else
-                return omap2_i2c_add_bus(pdev, bus_id);
+                return omap2_i2c_add_bus(bus_id);
 }
 /**
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index 3cf4fa25ab3d..97126dfd2888 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -151,14 +151,14 @@ struct omap_board_config_kernel {
        const void *data;
 };
-extern const void *__omap_get_config(u16 tag, size_t len, int nr);
+extern const void *__init __omap_get_config(u16 tag, size_t len, int nr);
 #define omap_get_config(tag, type) \
        ((const type *) __omap_get_config((tag), sizeof(type), 0))
 #define omap_get_nr_config(tag, type, nr) \
        ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
-extern const void *omap_get_var_config(u16 tag, size_t *len);
+extern const void *__init omap_get_var_config(u16 tag, size_t *len);
 extern struct omap_board_config_kernel *omap_board_config;
 extern int omap_board_config_size;
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index bb937f3fabed..f1899a3e4174 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -8,7 +8,7 @@
 #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
 #define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 struct omap_clk {
        u16                             cpu;
@@ -31,18 +31,19 @@ struct omap_clk {
 #define CK_1510         (1 << 2)
 #define CK_16XX         (1 << 3)        /* 16xx, 17xx, 5912 */
 #define CK_242X         (1 << 4)
-#define CK_243X         (1 << 5)
+#define CK_243X         (1 << 5)        /* 243x, 253x */
-#define CK_3XXX         (1 << 6)        /* OMAP3 + AM3 common clocks*/
+#define CK_3430ES1      (1 << 6)        /* 34xxES1 only */
-#define CK_343X         (1 << 7)        /* OMAP34xx common clocks */
+#define CK_3430ES2PLUS  (1 << 7)        /* 34xxES2, ES3, non-Sitara 35xx only */
-#define CK_3430ES1      (1 << 8)        /* 34xxES1 only */
+#define CK_3505         (1 << 8)
-#define CK_3430ES2      (1 << 9)        /* 34xxES2, ES3, non-Sitara 35xx only */
+#define CK_3517         (1 << 9)
-#define CK_3505         (1 << 10)
+#define CK_36XX         (1 << 10)       /* 36xx/37xx-specific clocks */
-#define CK_3517         (1 << 11)
+#define CK_443X         (1 << 11)
-#define CK_36XX         (1 << 12)       /* OMAP36xx/37xx-specific clocks */
+#define CK_TI816X       (1 << 12)
-#define CK_443X         (1 << 13)
-#define CK_AM35XX       (CK_3505 | CK_3517)     /* all Sitara AM35xx */
+#define CK_34XX         (CK_3430ES1 | CK_3430ES2PLUS)
+#define CK_AM35XX       (CK_3505 | CK_3517)     /* all Sitara AM35xx */
+#define CK_3XXX         (CK_34XX | CK_AM35XX | CK_36XX)
 #endif
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index fef4696dcf67..006e599c6613 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -25,6 +25,8 @@ struct clockdomain;
 * @disable: fn ptr that enables the current clock in hardware
 * @find_idlest: function returning the IDLEST register for the clock's IP blk
 * @find_companion: function returning the "companion" clk reg for the clock
+ * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
+ * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
 *
 * A "companion" clk is an accompanying clock to the one being queried
 * that must be enabled for the IP module connected to the clock to
@@ -42,6 +44,8 @@ struct clkops {
                                               u8 *, u8 *);
        void                    (*find_companion)(struct clk *, void __iomem **,
                                                  u8 *);
+        void                    (*allow_idle)(struct clk *);
+        void                    (*deny_idle)(struct clk *);
 };
 #ifdef CONFIG_ARCH_OMAP2PLUS
@@ -49,13 +53,19 @@ struct clkops {
 /* struct clksel_rate.flags possibilities */
 #define RATE_IN_242X            (1 << 0)
 #define RATE_IN_243X            (1 << 1)
-#define RATE_IN_3XXX            (1 << 2)        /* rates common to all OMAP3 */
+#define RATE_IN_3430ES1         (1 << 2)        /* 3430ES1 rates only */
-#define RATE_IN_3430ES2         (1 << 3)        /* 3430ES2 rates only */
+#define RATE_IN_3430ES2PLUS     (1 << 3)        /* 3430 ES >= 2 rates only */
 #define RATE_IN_36XX            (1 << 4)
 #define RATE_IN_4430            (1 << 5)
+#define RATE_IN_TI816X          (1 << 6)
 #define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
-#define RATE_IN_3430ES2PLUS     (RATE_IN_3430ES2 | RATE_IN_36XX)
+#define RATE_IN_34XX            (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
+#define RATE_IN_3XXX            (RATE_IN_34XX | RATE_IN_36XX)
+/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
+#define RATE_IN_3430ES2PLUS_36XX        (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
 /**
 * struct clksel_rate - register bitfield values corresponding to clk divisors
@@ -99,7 +109,6 @@ struct clksel {
 * @clk_ref: struct clk pointer to the clock's reference clock input
 * @control_reg: register containing the DPLL mode bitfield
 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
- * @rate_tolerance: maximum variance allowed from target rate (in Hz)
 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
@@ -119,19 +128,15 @@ struct clksel {
 *
 * Possible values for @flags:
 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
- * NO_DCO_SEL: don't program DCO (only for some J-type DPLLs)
+ *
 * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
 *
 * XXX Some DPLLs have multiple bypass inputs, so it's not technically
 * correct to only have one @clk_bypass pointer.
 *
- * XXX @rate_tolerance should probably be deprecated - currently there
- * don't seem to be any usecases for DPLL rounding that is not exact.
- *
 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
 * @last_rounded_n) should be separated from the runtime-fixed fields
- * and placed into a differenct structure, so that the runtime-fixed data
+ * and placed into a different structure, so that the runtime-fixed data
 * can be placed into read-only space.
 */
 struct dpll_data {
@@ -142,7 +147,6 @@ struct dpll_data {
        struct clk              *clk_ref;
        void __iomem            *control_reg;
        u32                     enable_mask;
-        unsigned int            rate_tolerance;
        unsigned long           last_rounded_rate;
        u16                     last_rounded_m;
        u16                     max_multiplier;
@@ -156,6 +160,8 @@ struct dpll_data {
        u32                     autoidle_mask;
        u32                     freqsel_mask;
        u32                     idlest_mask;
+        u32                     dco_mask;
+        u32                     sddiv_mask;
        u8                      auto_recal_bit;
        u8                      recal_en_bit;
        u8                      recal_st_bit;
@@ -165,12 +171,24 @@ struct dpll_data {
 #endif
-/* struct clk.flags possibilities */
+/*
+ * struct clk.flags possibilities
+ *
+ * XXX document the rest of the clock flags here
+ *
+ * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
+ *     bits share the same register.  This flag allows the
+ *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
+ *     should be used.  This is a temporary solution - a better approach
+ *     would be to associate clock type-specific data with the clock,
+ *     similar to the struct dpll_data approach.
+ */
 #define ENABLE_REG_32BIT        (1 << 0)        /* Use 32-bit access */
 #define CLOCK_IDLE_CONTROL      (1 << 1)
 #define CLOCK_NO_IDLE_PARENT    (1 << 2)
 #define ENABLE_ON_INIT          (1 << 3)        /* Enable upon framework init */
 #define INVERT_ENABLE           (1 << 4)        /* 0 enables, 1 disables */
+#define CLOCK_CLKOUTX2          (1 << 5)
 /**
 * struct clk - OMAP struct clk
@@ -286,6 +304,8 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
 #endif
 extern struct clk *omap_clk_get_by_name(const char *name);
+extern int omap_clk_enable_autoidle_all(void);
+extern int omap_clk_disable_autoidle_all(void);
 extern const struct clkops clkops_null;
diff --git a/arch/arm/plat-omap/include/plat/clockdomain.h b/arch/arm/plat-omap/include/plat/clockdomain.h
deleted file mode 100644
index ba0a6c07c0fe..000000000000
--- a/arch/arm/plat-omap/include/plat/clockdomain.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/clockdomain.h
- *
- * OMAP2/3 clockdomain framework functions
- *
- * Copyright (C) 2008 Texas Instruments, Inc.
- * Copyright (C) 2008-2009 Nokia Corporation
- *
- * Written by Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
-#define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
-#include <plat/powerdomain.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-/* Clockdomain capability flags */
-#define CLKDM_CAN_FORCE_SLEEP                   (1 << 0)
-#define CLKDM_CAN_FORCE_WAKEUP                  (1 << 1)
-#define CLKDM_CAN_ENABLE_AUTO                   (1 << 2)
-#define CLKDM_CAN_DISABLE_AUTO                  (1 << 3)
-#define CLKDM_CAN_HWSUP         (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
-#define CLKDM_CAN_SWSUP         (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
-#define CLKDM_CAN_HWSUP_SWSUP   (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP)
-/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
-#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO         0x0
-#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO          0x1
-/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
-#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO         0x0
-#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP          0x1
-#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP         0x2
-#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO          0x3
-/**
- * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode
- * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only
- * @omap_chip: OMAP chip types that this autodep is valid on
- *
- * A clockdomain that should have wkdeps and sleepdeps added when a
- * clockdomain should stay active in hwsup mode; and conversely,
- * removed when the clockdomain should be allowed to go inactive in
- * hwsup mode.
- *
- * Autodeps are deprecated and should be removed after
- * omap_hwmod-based fine-grained module idle control is added.
- */
-struct clkdm_autodep {
-        union {
-                const char *name;
-                struct clockdomain *ptr;
-        } clkdm;
-        const struct omap_chip_id omap_chip;
-};
-/**
- * struct clkdm_dep - encode dependencies between clockdomains
- * @clkdm_name: clockdomain name
- * @clkdm: pointer to the struct clockdomain of @clkdm_name
- * @omap_chip: OMAP chip types that this dependency is valid on
- * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake
- * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle
- *
- * Statically defined.  @clkdm is resolved from @clkdm_name at runtime and
- * should not be pre-initialized.
- *
- * XXX Should also include hardware (fixed) dependencies.
- */
-struct clkdm_dep {
-        const char *clkdm_name;
-        struct clockdomain *clkdm;
-        atomic_t wkdep_usecount;
-        atomic_t sleepdep_usecount;
-        const struct omap_chip_id omap_chip;
-};
-/**
- * struct clockdomain - OMAP clockdomain
- * @name: clockdomain name
- * @pwrdm: powerdomain containing this clockdomain
- * @clktrctrl_reg: CLKSTCTRL reg for the given clock domain
- * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg
- * @flags: Clockdomain capability flags
- * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit
- * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up
- * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact
- * @omap_chip: OMAP chip types that this clockdomain is valid on
- * @usecount: Usecount tracking
- * @node: list_head to link all clockdomains together
- */
-struct clockdomain {
-        const char *name;
-        union {
-                const char *name;
-                struct powerdomain *ptr;
-        } pwrdm;
-        void __iomem *clkstctrl_reg;
-        const u16 clktrctrl_mask;
-        const u8 flags;
-        const u8 dep_bit;
-        struct clkdm_dep *wkdep_srcs;
-        struct clkdm_dep *sleepdep_srcs;
-        const struct omap_chip_id omap_chip;
-        atomic_t usecount;
-        struct list_head node;
-};
-void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps);
-struct clockdomain *clkdm_lookup(const char *name);
-int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
-                        void *user);
-struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm);
-int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
-int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
-int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
-int clkdm_clear_all_wkdeps(struct clockdomain *clkdm);
-int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
-int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
-int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
-int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
-void omap2_clkdm_allow_idle(struct clockdomain *clkdm);
-void omap2_clkdm_deny_idle(struct clockdomain *clkdm);
-int omap2_clkdm_wakeup(struct clockdomain *clkdm);
-int omap2_clkdm_sleep(struct clockdomain *clkdm);
-int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
-int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
-#endif
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 9776b41ad76f..5288130be96e 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -27,12 +27,17 @@
 #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
 #define __ARCH_ARM_MACH_OMAP_COMMON_H
+#include <linux/delay.h>
 #include <plat/i2c.h>
 struct sys_timer;
 extern void omap_map_common_io(void);
 extern struct sys_timer omap_timer;
+extern bool omap_32k_timer_init(void);
+extern int __init omap_init_clocksource_32k(void);
+extern unsigned long long notrace omap_32k_sched_clock(void);
 extern void omap_reserve(void);
@@ -47,26 +52,23 @@ struct omap_globals {
        unsigned long   sdrc;           /* SDRAM Controller */
        unsigned long   sms;            /* SDRAM Memory Scheduler */
        unsigned long   ctrl;           /* System Control Module */
+        unsigned long   ctrl_pad;       /* PAD Control Module */
        unsigned long   prm;            /* Power and Reset Management */
        unsigned long   cm;             /* Clock Management */
        unsigned long   cm2;
-        unsigned long   uart1_phys;
-        unsigned long   uart2_phys;
-        unsigned long   uart3_phys;
-        unsigned long   uart4_phys;
 };
 void omap2_set_globals_242x(void);
 void omap2_set_globals_243x(void);
 void omap2_set_globals_3xxx(void);
 void omap2_set_globals_443x(void);
+void omap2_set_globals_ti816x(void);
 /* These get called from omap2_set_globals_xxxx(), do not call these */
 void omap2_set_globals_tap(struct omap_globals *);
 void omap2_set_globals_sdrc(struct omap_globals *);
 void omap2_set_globals_control(struct omap_globals *);
 void omap2_set_globals_prcm(struct omap_globals *);
-void omap2_set_globals_uart(struct omap_globals *);
 void omap3_map_io(void);
@@ -91,7 +93,8 @@ void omap3_map_io(void);
 })
 extern struct device *omap2_get_mpuss_device(void);
-extern struct device *omap2_get_dsp_device(void);
+extern struct device *omap2_get_iva_device(void);
 extern struct device *omap2_get_l3_device(void);
+extern struct device *omap4_get_dsp_device(void);
 #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
deleted file mode 100644
index 131bf405c2f6..000000000000
--- a/arch/arm/plat-omap/include/plat/control.h
+++ /dev/null
@@ -1,381 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/control.h
- *
- * OMAP2/3/4 System Control Module definitions
- *
- * Copyright (C) 2007-2009 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
- *
- * Written by Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_CONTROL_H
-#define __ASM_ARCH_CONTROL_H
-#include <mach/io.h>
-#ifndef __ASSEMBLY__
-#define OMAP242X_CTRL_REGADDR(reg)                                      \
-                OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
-#define OMAP243X_CTRL_REGADDR(reg)                                      \
-                OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
-#define OMAP343X_CTRL_REGADDR(reg)                                      \
-                OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
-#else
-#define OMAP242X_CTRL_REGADDR(reg)                                      \
-                OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
-#define OMAP243X_CTRL_REGADDR(reg)                                      \
-                OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
-#define OMAP343X_CTRL_REGADDR(reg)                                      \
-                OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
-#endif /* __ASSEMBLY__ */
-/*
- * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
- * OMAP24XX and OMAP34XX.
- */
-/* Control submodule offsets */
-#define OMAP2_CONTROL_INTERFACE         0x000
-#define OMAP2_CONTROL_PADCONFS          0x030
-#define OMAP2_CONTROL_GENERAL           0x270
-#define OMAP343X_CONTROL_MEM_WKUP       0x600
-#define OMAP343X_CONTROL_PADCONFS_WKUP  0xa00
-#define OMAP343X_CONTROL_GENERAL_WKUP   0xa60
-/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
-#define OMAP2_CONTROL_SYSCONFIG         (OMAP2_CONTROL_INTERFACE + 0x10)
-/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
-#define OMAP2_CONTROL_DEVCONF0          (OMAP2_CONTROL_GENERAL + 0x0004)
-#define OMAP2_CONTROL_MSUSPENDMUX_0     (OMAP2_CONTROL_GENERAL + 0x0020)
-#define OMAP2_CONTROL_MSUSPENDMUX_1     (OMAP2_CONTROL_GENERAL + 0x0024)
-#define OMAP2_CONTROL_MSUSPENDMUX_2     (OMAP2_CONTROL_GENERAL + 0x0028)
-#define OMAP2_CONTROL_MSUSPENDMUX_3     (OMAP2_CONTROL_GENERAL + 0x002c)
-#define OMAP2_CONTROL_MSUSPENDMUX_4     (OMAP2_CONTROL_GENERAL + 0x0030)
-#define OMAP2_CONTROL_MSUSPENDMUX_5     (OMAP2_CONTROL_GENERAL + 0x0034)
-#define OMAP2_CONTROL_SEC_CTRL          (OMAP2_CONTROL_GENERAL + 0x0040)
-#define OMAP2_CONTROL_RPUB_KEY_H_0      (OMAP2_CONTROL_GENERAL + 0x0090)
-#define OMAP2_CONTROL_RPUB_KEY_H_1      (OMAP2_CONTROL_GENERAL + 0x0094)
-#define OMAP2_CONTROL_RPUB_KEY_H_2      (OMAP2_CONTROL_GENERAL + 0x0098)
-#define OMAP2_CONTROL_RPUB_KEY_H_3      (OMAP2_CONTROL_GENERAL + 0x009c)
-/* 242x-only CONTROL_GENERAL register offsets */
-#define OMAP242X_CONTROL_DEVCONF        OMAP2_CONTROL_DEVCONF0 /* match TRM */
-#define OMAP242X_CONTROL_OCM_RAM_PERM   (OMAP2_CONTROL_GENERAL + 0x0068)
-/* 243x-only CONTROL_GENERAL register offsets */
-/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
-#define OMAP243X_CONTROL_DEVCONF1       (OMAP2_CONTROL_GENERAL + 0x0078)
-#define OMAP243X_CONTROL_CSIRXFE        (OMAP2_CONTROL_GENERAL + 0x007c)
-#define OMAP243X_CONTROL_IVA2_BOOTADDR  (OMAP2_CONTROL_GENERAL + 0x0190)
-#define OMAP243X_CONTROL_IVA2_BOOTMOD   (OMAP2_CONTROL_GENERAL + 0x0194)
-#define OMAP243X_CONTROL_IVA2_GEMCFG    (OMAP2_CONTROL_GENERAL + 0x0198)
-#define OMAP243X_CONTROL_PBIAS_LITE     (OMAP2_CONTROL_GENERAL + 0x0230)
-/* 24xx-only CONTROL_GENERAL register offsets */
-#define OMAP24XX_CONTROL_DEBOBS         (OMAP2_CONTROL_GENERAL + 0x0000)
-#define OMAP24XX_CONTROL_EMU_SUPPORT    (OMAP2_CONTROL_GENERAL + 0x0008)
-#define OMAP24XX_CONTROL_SEC_TEST       (OMAP2_CONTROL_GENERAL + 0x0044)
-#define OMAP24XX_CONTROL_PSA_CTRL       (OMAP2_CONTROL_GENERAL + 0x0048)
-#define OMAP24XX_CONTROL_PSA_CMD        (OMAP2_CONTROL_GENERAL + 0x004c)
-#define OMAP24XX_CONTROL_PSA_VALUE      (OMAP2_CONTROL_GENERAL + 0x0050)
-#define OMAP24XX_CONTROL_SEC_EMU        (OMAP2_CONTROL_GENERAL + 0x0060)
-#define OMAP24XX_CONTROL_SEC_TAP        (OMAP2_CONTROL_GENERAL + 0x0064)
-#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD        (OMAP2_CONTROL_GENERAL + 0x006c)
-#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD  (OMAP2_CONTROL_GENERAL + 0x0070)
-#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD   (OMAP2_CONTROL_GENERAL + 0x0074)
-#define OMAP24XX_CONTROL_SEC_STATUS             (OMAP2_CONTROL_GENERAL + 0x0080)
-#define OMAP24XX_CONTROL_SEC_ERR_STATUS         (OMAP2_CONTROL_GENERAL + 0x0084)
-#define OMAP24XX_CONTROL_STATUS                 (OMAP2_CONTROL_GENERAL + 0x0088)
-#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
-#define OMAP24XX_CONTROL_RAND_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00a0)
-#define OMAP24XX_CONTROL_RAND_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00a4)
-#define OMAP24XX_CONTROL_RAND_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00a8)
-#define OMAP24XX_CONTROL_RAND_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00ac)
-#define OMAP24XX_CONTROL_CUST_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00b0)
-#define OMAP24XX_CONTROL_CUST_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00b4)
-#define OMAP24XX_CONTROL_TEST_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00c0)
-#define OMAP24XX_CONTROL_TEST_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00c4)
-#define OMAP24XX_CONTROL_TEST_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00c8)
-#define OMAP24XX_CONTROL_TEST_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00cc)
-#define OMAP24XX_CONTROL_TEST_KEY_4     (OMAP2_CONTROL_GENERAL + 0x00d0)
-#define OMAP24XX_CONTROL_TEST_KEY_5     (OMAP2_CONTROL_GENERAL + 0x00d4)
-#define OMAP24XX_CONTROL_TEST_KEY_6     (OMAP2_CONTROL_GENERAL + 0x00d8)
-#define OMAP24XX_CONTROL_TEST_KEY_7     (OMAP2_CONTROL_GENERAL + 0x00dc)
-#define OMAP24XX_CONTROL_TEST_KEY_8     (OMAP2_CONTROL_GENERAL + 0x00e0)
-#define OMAP24XX_CONTROL_TEST_KEY_9     (OMAP2_CONTROL_GENERAL + 0x00e4)
-#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
-/* 34xx-only CONTROL_GENERAL register offsets */
-#define OMAP343X_CONTROL_PADCONF_OFF    (OMAP2_CONTROL_GENERAL + 0x0000)
-#define OMAP343X_CONTROL_MEM_DFTRW0     (OMAP2_CONTROL_GENERAL + 0x0008)
-#define OMAP343X_CONTROL_MEM_DFTRW1     (OMAP2_CONTROL_GENERAL + 0x000c)
-#define OMAP343X_CONTROL_DEVCONF1       (OMAP2_CONTROL_GENERAL + 0x0068)
-#define OMAP343X_CONTROL_CSIRXFE                (OMAP2_CONTROL_GENERAL + 0x006c)
-#define OMAP343X_CONTROL_SEC_STATUS             (OMAP2_CONTROL_GENERAL + 0x0070)
-#define OMAP343X_CONTROL_SEC_ERR_STATUS         (OMAP2_CONTROL_GENERAL + 0x0074)
-#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG   (OMAP2_CONTROL_GENERAL + 0x0078)
-#define OMAP343X_CONTROL_STATUS                 (OMAP2_CONTROL_GENERAL + 0x0080)
-#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
-#define OMAP343X_CONTROL_RPUB_KEY_H_4   (OMAP2_CONTROL_GENERAL + 0x00a0)
-#define OMAP343X_CONTROL_RAND_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00a8)
-#define OMAP343X_CONTROL_RAND_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00ac)
-#define OMAP343X_CONTROL_RAND_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00b0)
-#define OMAP343X_CONTROL_RAND_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00b4)
-#define OMAP343X_CONTROL_TEST_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00c8)
-#define OMAP343X_CONTROL_TEST_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00cc)
-#define OMAP343X_CONTROL_TEST_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00d0)
-#define OMAP343X_CONTROL_TEST_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00d4)
-#define OMAP343X_CONTROL_TEST_KEY_4     (OMAP2_CONTROL_GENERAL + 0x00d8)
-#define OMAP343X_CONTROL_TEST_KEY_5     (OMAP2_CONTROL_GENERAL + 0x00dc)
-#define OMAP343X_CONTROL_TEST_KEY_6     (OMAP2_CONTROL_GENERAL + 0x00e0)
-#define OMAP343X_CONTROL_TEST_KEY_7     (OMAP2_CONTROL_GENERAL + 0x00e4)
-#define OMAP343X_CONTROL_TEST_KEY_8     (OMAP2_CONTROL_GENERAL + 0x00e8)
-#define OMAP343X_CONTROL_TEST_KEY_9     (OMAP2_CONTROL_GENERAL + 0x00ec)
-#define OMAP343X_CONTROL_TEST_KEY_10    (OMAP2_CONTROL_GENERAL + 0x00f0)
-#define OMAP343X_CONTROL_TEST_KEY_11    (OMAP2_CONTROL_GENERAL + 0x00f4)
-#define OMAP343X_CONTROL_TEST_KEY_12    (OMAP2_CONTROL_GENERAL + 0x00f8)
-#define OMAP343X_CONTROL_TEST_KEY_13    (OMAP2_CONTROL_GENERAL + 0x00fc)
-#define OMAP343X_CONTROL_IVA2_BOOTADDR  (OMAP2_CONTROL_GENERAL + 0x0190)
-#define OMAP343X_CONTROL_IVA2_BOOTMOD   (OMAP2_CONTROL_GENERAL + 0x0194)
-#define OMAP343X_CONTROL_DEBOBS(i)      (OMAP2_CONTROL_GENERAL + 0x01B0 \
-                                        + ((i) >> 1) * 4 + (!((i) & 1)) * 2)
-#define OMAP343X_CONTROL_PROG_IO0       (OMAP2_CONTROL_GENERAL + 0x01D4)
-#define OMAP343X_CONTROL_PROG_IO1       (OMAP2_CONTROL_GENERAL + 0x01D8)
-#define OMAP343X_CONTROL_DSS_DPLL_SPREADING     (OMAP2_CONTROL_GENERAL + 0x01E0)
-#define OMAP343X_CONTROL_CORE_DPLL_SPREADING    (OMAP2_CONTROL_GENERAL + 0x01E4)
-#define OMAP343X_CONTROL_PER_DPLL_SPREADING     (OMAP2_CONTROL_GENERAL + 0x01E8)
-#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
-#define OMAP343X_CONTROL_PBIAS_LITE     (OMAP2_CONTROL_GENERAL + 0x02B0)
-#define OMAP343X_CONTROL_TEMP_SENSOR    (OMAP2_CONTROL_GENERAL + 0x02B4)
-#define OMAP343X_CONTROL_SRAMLDO4       (OMAP2_CONTROL_GENERAL + 0x02B8)
-#define OMAP343X_CONTROL_SRAMLDO5       (OMAP2_CONTROL_GENERAL + 0x02C0)
-#define OMAP343X_CONTROL_CSI            (OMAP2_CONTROL_GENERAL + 0x02C4)
-/* AM35XX only CONTROL_GENERAL register offsets */
-#define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)
-#define AM35XX_CONTROL_DEVCONF2         (OMAP2_CONTROL_GENERAL + 0x0310)
-#define AM35XX_CONTROL_DEVCONF3         (OMAP2_CONTROL_GENERAL + 0x0314)
-#define AM35XX_CONTROL_CBA_PRIORITY     (OMAP2_CONTROL_GENERAL + 0x0320)
-#define AM35XX_CONTROL_LVL_INTR_CLEAR   (OMAP2_CONTROL_GENERAL + 0x0324)
-#define AM35XX_CONTROL_IP_SW_RESET      (OMAP2_CONTROL_GENERAL + 0x0328)
-#define AM35XX_CONTROL_IPSS_CLK_CTRL    (OMAP2_CONTROL_GENERAL + 0x032C)
-/* 34xx PADCONF register offsets */
-#define OMAP343X_PADCONF_ETK(i)         (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
-                                                (i)*2)
-#define OMAP343X_PADCONF_ETK_CLK        OMAP343X_PADCONF_ETK(0)
-#define OMAP343X_PADCONF_ETK_CTL        OMAP343X_PADCONF_ETK(1)
-#define OMAP343X_PADCONF_ETK_D0         OMAP343X_PADCONF_ETK(2)
-#define OMAP343X_PADCONF_ETK_D1         OMAP343X_PADCONF_ETK(3)
-#define OMAP343X_PADCONF_ETK_D2         OMAP343X_PADCONF_ETK(4)
-#define OMAP343X_PADCONF_ETK_D3         OMAP343X_PADCONF_ETK(5)
-#define OMAP343X_PADCONF_ETK_D4         OMAP343X_PADCONF_ETK(6)
-#define OMAP343X_PADCONF_ETK_D5         OMAP343X_PADCONF_ETK(7)
-#define OMAP343X_PADCONF_ETK_D6         OMAP343X_PADCONF_ETK(8)
-#define OMAP343X_PADCONF_ETK_D7         OMAP343X_PADCONF_ETK(9)
-#define OMAP343X_PADCONF_ETK_D8         OMAP343X_PADCONF_ETK(10)
-#define OMAP343X_PADCONF_ETK_D9         OMAP343X_PADCONF_ETK(11)
-#define OMAP343X_PADCONF_ETK_D10        OMAP343X_PADCONF_ETK(12)
-#define OMAP343X_PADCONF_ETK_D11        OMAP343X_PADCONF_ETK(13)
-#define OMAP343X_PADCONF_ETK_D12        OMAP343X_PADCONF_ETK(14)
-#define OMAP343X_PADCONF_ETK_D13        OMAP343X_PADCONF_ETK(15)
-#define OMAP343X_PADCONF_ETK_D14        OMAP343X_PADCONF_ETK(16)
-#define OMAP343X_PADCONF_ETK_D15        OMAP343X_PADCONF_ETK(17)
-/* 34xx GENERAL_WKUP regist offsets */
-#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
-                                                0x008 + (i))
-#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
-#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
-#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
-#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
-#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
-/* 34xx D2D idle-related pins, handled by PM core */
-#define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
-#define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
-/* 44xx control status register offset */
-#define OMAP44XX_CONTROL_STATUS         0x2c4
-/* 44xx-only CONTROL_GENERAL register offsets */
-#define OMAP44XX_CONTROL_MMC1                   0x628
-#define OMAP44XX_CONTROL_PBIAS_LITE             0x600
-/*
- * REVISIT: This list of registers is not comprehensive - there are more
- * that should be added.
- */
-/*
- * Control module register bit defines - these should eventually go into
- * their own regbits file.  Some of these will be complicated, depending
- * on the device type (general-purpose, emulator, test, secure, bad, other)
- * and the security mode (secure, non-secure, don't care)
- */
-/* CONTROL_DEVCONF0 bits */
-#define OMAP2_MMCSDIO1ADPCLKISEL        (1 << 24) /* MMC1 loop back clock */
-#define OMAP24XX_USBSTANDBYCTRL         (1 << 15)
-#define OMAP2_MCBSP2_CLKS_MASK          (1 << 6)
-#define OMAP2_MCBSP1_CLKS_MASK          (1 << 2)
-/* CONTROL_DEVCONF1 bits */
-#define OMAP243X_MMC1_ACTIVE_OVERWRITE  (1 << 31)
-#define OMAP2_MMCSDIO2ADPCLKISEL        (1 << 6) /* MMC2 loop back clock */
-#define OMAP2_MCBSP5_CLKS_MASK          (1 << 4) /* > 242x */
-#define OMAP2_MCBSP4_CLKS_MASK          (1 << 2) /* > 242x */
-#define OMAP2_MCBSP3_CLKS_MASK          (1 << 0) /* > 242x */
-/* CONTROL_STATUS bits */
-#define OMAP2_DEVICETYPE_MASK           (0x7 << 8)
-#define OMAP2_SYSBOOT_5_MASK            (1 << 5)
-#define OMAP2_SYSBOOT_4_MASK            (1 << 4)
-#define OMAP2_SYSBOOT_3_MASK            (1 << 3)
-#define OMAP2_SYSBOOT_2_MASK            (1 << 2)
-#define OMAP2_SYSBOOT_1_MASK            (1 << 1)
-#define OMAP2_SYSBOOT_0_MASK            (1 << 0)
-/* CONTROL_PBIAS_LITE bits */
-#define OMAP343X_PBIASLITESUPPLY_HIGH1  (1 << 15)
-#define OMAP343X_PBIASLITEVMODEERROR1   (1 << 11)
-#define OMAP343X_PBIASSPEEDCTRL1        (1 << 10)
-#define OMAP343X_PBIASLITEPWRDNZ1       (1 << 9)
-#define OMAP343X_PBIASLITEVMODE1        (1 << 8)
-#define OMAP343X_PBIASLITESUPPLY_HIGH0  (1 << 7)
-#define OMAP343X_PBIASLITEVMODEERROR0   (1 << 3)
-#define OMAP2_PBIASSPEEDCTRL0           (1 << 2)
-#define OMAP2_PBIASLITEPWRDNZ0          (1 << 1)
-#define OMAP2_PBIASLITEVMODE0           (1 << 0)
-/* CONTROL_PBIAS_LITE bits for OMAP4 */
-#define OMAP4_MMC1_PWRDNZ                       (1 << 26)
-#define OMAP4_MMC1_PBIASLITE_HIZ_MODE           (1 << 25)
-#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT      (1 << 24)
-#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR        (1 << 23)
-#define OMAP4_MMC1_PBIASLITE_PWRDNZ             (1 << 22)
-#define OMAP4_MMC1_PBIASLITE_VMODE              (1 << 21)
-#define OMAP4_USBC1_ICUSB_PWRDNZ                (1 << 20)
-#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0     (1 << 31)
-#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1     (1 << 30)
-#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2     (1 << 29)
-#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3     (1 << 28)
-#define OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL      (1 << 27)
-#define OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL      (1 << 26)
-#define OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL      (1 << 25)
-/* CONTROL_PROG_IO1 bits */
-#define OMAP3630_PRG_SDMMC1_SPEEDCTRL   (1 << 20)
-/* CONTROL_IVA2_BOOTMOD bits */
-#define OMAP3_IVA2_BOOTMOD_SHIFT        0
-#define OMAP3_IVA2_BOOTMOD_MASK         (0xf << 0)
-#define OMAP3_IVA2_BOOTMOD_IDLE         (0x1 << 0)
-/* CONTROL_PADCONF_X bits */
-#define OMAP3_PADCONF_WAKEUPEVENT0      (1 << 15)
-#define OMAP3_PADCONF_WAKEUPENABLE0     (1 << 14)
-#define OMAP343X_SCRATCHPAD_ROM         (OMAP343X_CTRL_BASE + 0x860)
-#define OMAP343X_SCRATCHPAD             (OMAP343X_CTRL_BASE + 0x910)
-#define OMAP343X_SCRATCHPAD_ROM_OFFSET  0x19C
-/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
-#define AM35XX_USBOTG_VBUSP_CLK_SHIFT   0
-#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT   1
-#define AM35XX_VPFE_VBUSP_CLK_SHIFT     2
-#define AM35XX_HECC_VBUSP_CLK_SHIFT     3
-#define AM35XX_USBOTG_FCLK_SHIFT        8
-#define AM35XX_CPGMAC_FCLK_SHIFT        9
-#define AM35XX_VPFE_FCLK_SHIFT          10
-/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/
-#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
-#define AM35XX_CPGMAC_C0_RX_PULSE_CLR   BIT(1)
-#define AM35XX_CPGMAC_C0_RX_THRESH_CLR  BIT(2)
-#define AM35XX_CPGMAC_C0_TX_PULSE_CLR   BIT(3)
-#define AM35XX_USBOTGSS_INT_CLR         BIT(4)
-#define AM35XX_VPFE_CCDC_VD0_INT_CLR    BIT(5)
-#define AM35XX_VPFE_CCDC_VD1_INT_CLR    BIT(6)
-#define AM35XX_VPFE_CCDC_VD2_INT_CLR    BIT(7)
-/*AM35XX CONTROL_IP_SW_RESET bits*/
-#define AM35XX_USBOTGSS_SW_RST          BIT(0)
-#define AM35XX_CPGMACSS_SW_RST          BIT(1)
-#define AM35XX_VPFE_VBUSP_SW_RST        BIT(2)
-#define AM35XX_HECC_SW_RST              BIT(3)
-#define AM35XX_VPFE_PCLK_SW_RST         BIT(4)
-/*
- * CONTROL OMAP STATUS register to identify OMAP3 features
- */
-#define OMAP3_CONTROL_OMAP_STATUS       0x044c
-#define OMAP3_SGX_SHIFT                 13
-#define OMAP3_SGX_MASK                  (3 << OMAP3_SGX_SHIFT)
-#define         FEAT_SGX_FULL           0
-#define         FEAT_SGX_HALF           1
-#define         FEAT_SGX_NONE           2
-#define OMAP3_IVA_SHIFT                 12
-#define OMAP3_IVA_MASK                  (1 << OMAP3_SGX_SHIFT)
-#define         FEAT_IVA                0
-#define         FEAT_IVA_NONE           1
-#define OMAP3_L2CACHE_SHIFT             10
-#define OMAP3_L2CACHE_MASK              (3 << OMAP3_L2CACHE_SHIFT)
-#define         FEAT_L2CACHE_NONE       0
-#define         FEAT_L2CACHE_64KB       1
-#define         FEAT_L2CACHE_128KB      2
-#define         FEAT_L2CACHE_256KB      3
-#define OMAP3_ISP_SHIFT                 5
-#define OMAP3_ISP_MASK                  (1<< OMAP3_ISP_SHIFT)
-#define         FEAT_ISP                0
-#define         FEAT_ISP_NONE           1
-#define OMAP3_NEON_SHIFT                4
-#define OMAP3_NEON_MASK                 (1<< OMAP3_NEON_SHIFT)
-#define         FEAT_NEON               0
-#define         FEAT_NEON_NONE          1
-#ifndef __ASSEMBLY__
-#ifdef CONFIG_ARCH_OMAP2PLUS
-extern void __iomem *omap_ctrl_base_get(void);
-extern u8 omap_ctrl_readb(u16 offset);
-extern u16 omap_ctrl_readw(u16 offset);
-extern u32 omap_ctrl_readl(u16 offset);
-extern void omap_ctrl_writeb(u8 val, u16 offset);
-extern void omap_ctrl_writew(u16 val, u16 offset);
-extern void omap_ctrl_writel(u32 val, u16 offset);
-extern void omap3_save_scratchpad_contents(void);
-extern void omap3_clear_scratchpad_contents(void);
-extern u32 *get_restore_pointer(void);
-extern u32 *get_es3_restore_pointer(void);
-extern u32 omap3_arm_context[128];
-extern void omap3_control_save_context(void);
-extern void omap3_control_restore_context(void);
-#else
-#define omap_ctrl_base_get()            0
-#define omap_ctrl_readb(x)              0
-#define omap_ctrl_readw(x)              0
-#define omap_ctrl_readl(x)              0
-#define omap_ctrl_writeb(x, y)          WARN_ON(1)
-#define omap_ctrl_writew(x, y)          WARN_ON(1)
-#define omap_ctrl_writel(x, y)          WARN_ON(1)
-#endif
-#endif  /* __ASSEMBLY__ */
-#endif /* __ASM_ARCH_CONTROL_H */
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 2e2ae530fced..8198bb6cdb5e 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -5,7 +5,7 @@
 *
 * Copyright (C) 2004, 2008 Nokia Corporation
 *
- * Copyright (C) 2009 Texas Instruments.
+ * Copyright (C) 2009-11 Texas Instruments.
 *
 * Written by Tony Lindgren <tony.lindgren@nokia.com>
 *
@@ -68,10 +68,9 @@ unsigned int omap_rev(void);
 #define OMAP_REVBITS_00         0x00
 #define OMAP_REVBITS_01         0x01
 #define OMAP_REVBITS_02         0x02
-#define OMAP_REVBITS_10         0x10
+#define OMAP_REVBITS_03         0x03
-#define OMAP_REVBITS_20         0x20
+#define OMAP_REVBITS_04         0x04
-#define OMAP_REVBITS_30         0x30
+#define OMAP_REVBITS_05         0x05
-#define OMAP_REVBITS_40         0x40
 /*
 * Get the CPU revision for OMAP devices
@@ -106,6 +105,12 @@ static inline int is_omap ##subclass (void)		\
        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
 }
+#define IS_TI_SUBCLASS(subclass, id)                    \
+static inline int is_ti ##subclass (void)               \
+{                                                       \
+        return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;     \
+}
 IS_OMAP_CLASS(7xx, 0x07)
 IS_OMAP_CLASS(15xx, 0x15)
 IS_OMAP_CLASS(16xx, 0x16)
@@ -119,6 +124,8 @@ IS_OMAP_SUBCLASS(343x, 0x343)
 IS_OMAP_SUBCLASS(363x, 0x363)
 IS_OMAP_SUBCLASS(443x, 0x443)
+IS_TI_SUBCLASS(816x, 0x816)
 #define cpu_is_omap7xx()                0
 #define cpu_is_omap15xx()               0
 #define cpu_is_omap16xx()               0
@@ -127,6 +134,7 @@ IS_OMAP_SUBCLASS(443x, 0x443)
 #define cpu_is_omap243x()               0
 #define cpu_is_omap34xx()               0
 #define cpu_is_omap343x()               0
+#define cpu_is_ti816x()                 0
 #define cpu_is_omap44xx()               0
 #define cpu_is_omap443x()               0
@@ -171,11 +179,11 @@ IS_OMAP_SUBCLASS(443x, 0x443)
 #  undef  cpu_is_omap24xx
 #  define cpu_is_omap24xx()             is_omap24xx()
 # endif
-# if defined (CONFIG_ARCH_OMAP2420)
+# if defined (CONFIG_SOC_OMAP2420)
 #  undef  cpu_is_omap242x
 #  define cpu_is_omap242x()             is_omap242x()
 # endif
-# if defined (CONFIG_ARCH_OMAP2430)
+# if defined (CONFIG_SOC_OMAP2430)
 #  undef  cpu_is_omap243x
 #  define cpu_is_omap243x()             is_omap243x()
 # endif
@@ -190,11 +198,11 @@ IS_OMAP_SUBCLASS(443x, 0x443)
 #  undef  cpu_is_omap24xx
 #  define cpu_is_omap24xx()             1
 # endif
-# if defined(CONFIG_ARCH_OMAP2420)
+# if defined(CONFIG_SOC_OMAP2420)
 #  undef  cpu_is_omap242x
 #  define cpu_is_omap242x()             1
 # endif
-# if defined(CONFIG_ARCH_OMAP2430)
+# if defined(CONFIG_SOC_OMAP2430)
 #  undef  cpu_is_omap243x
 #  define cpu_is_omap243x()             1
 # endif
@@ -202,7 +210,7 @@ IS_OMAP_SUBCLASS(443x, 0x443)
 #  undef  cpu_is_omap34xx
 #  define cpu_is_omap34xx()             1
 # endif
-# if defined(CONFIG_ARCH_OMAP3430)
+# if defined(CONFIG_SOC_OMAP3430)
 #  undef  cpu_is_omap343x
 #  define cpu_is_omap343x()             1
 # endif
@@ -331,6 +339,7 @@ IS_OMAP_TYPE(3517, 0x3517)
 # undef cpu_is_omap3530
 # undef cpu_is_omap3505
 # undef cpu_is_omap3517
+# undef cpu_is_ti816x
 # define cpu_is_omap3430()              is_omap3430()
 # define cpu_is_omap3503()              (cpu_is_omap3430() &&           \
                                                (!omap3_has_iva()) &&   \
@@ -346,6 +355,7 @@ IS_OMAP_TYPE(3517, 0x3517)
 # define cpu_is_omap3517()              is_omap3517()
 # undef cpu_is_omap3630
 # define cpu_is_omap3630()              is_omap363x()
+# define cpu_is_ti816x()                is_ti816x()
 #endif
 # if defined(CONFIG_ARCH_OMAP4)
@@ -363,23 +373,24 @@ IS_OMAP_TYPE(3517, 0x3517)
 /* Various silicon revisions for omap2 */
 #define OMAP242X_CLASS          0x24200024
-#define OMAP2420_REV_ES1_0      0x24200024
+#define OMAP2420_REV_ES1_0      OMAP242X_CLASS
-#define OMAP2420_REV_ES2_0      0x24201024
+#define OMAP2420_REV_ES2_0      (OMAP242X_CLASS | (OMAP_REVBITS_01 << 8))
 #define OMAP243X_CLASS          0x24300024
-#define OMAP2430_REV_ES1_0      0x24300024
+#define OMAP2430_REV_ES1_0      OMAP243X_CLASS
 #define OMAP343X_CLASS          0x34300034
-#define OMAP3430_REV_ES1_0      0x34300034
+#define OMAP3430_REV_ES1_0      OMAP343X_CLASS
-#define OMAP3430_REV_ES2_0      0x34301034
+#define OMAP3430_REV_ES2_0      (OMAP343X_CLASS | (OMAP_REVBITS_01 << 8))
-#define OMAP3430_REV_ES2_1      0x34302034
+#define OMAP3430_REV_ES2_1      (OMAP343X_CLASS | (OMAP_REVBITS_02 << 8))
-#define OMAP3430_REV_ES3_0      0x34303034
+#define OMAP3430_REV_ES3_0      (OMAP343X_CLASS | (OMAP_REVBITS_03 << 8))
-#define OMAP3430_REV_ES3_1      0x34304034
+#define OMAP3430_REV_ES3_1      (OMAP343X_CLASS | (OMAP_REVBITS_04 << 8))
-#define OMAP3430_REV_ES3_1_2    0x34305034
+#define OMAP3430_REV_ES3_1_2    (OMAP343X_CLASS | (OMAP_REVBITS_05 << 8))
-#define OMAP3630_REV_ES1_0      0x36300034
+#define OMAP363X_CLASS          0x36300034
-#define OMAP3630_REV_ES1_1      0x36300134
+#define OMAP3630_REV_ES1_0      OMAP363X_CLASS
-#define OMAP3630_REV_ES1_2      0x36300234
+#define OMAP3630_REV_ES1_1      (OMAP363X_CLASS | (OMAP_REVBITS_01 << 8))
+#define OMAP3630_REV_ES1_2      (OMAP363X_CLASS | (OMAP_REVBITS_02 << 8))
 #define OMAP35XX_CLASS          0x35000034
 #define OMAP3503_REV(v)         (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
@@ -389,8 +400,15 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define OMAP3505_REV(v)         (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
 #define OMAP3517_REV(v)         (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
+#define TI816X_CLASS            0x81600034
+#define TI8168_REV_ES1_0        TI816X_CLASS
+#define TI8168_REV_ES1_1        (TI816X_CLASS | (OMAP_REVBITS_01 << 8))
 #define OMAP443X_CLASS          0x44300044
-#define OMAP4430_REV_ES1_0      0x44300044
+#define OMAP4430_REV_ES1_0      (OMAP443X_CLASS | (0x10 << 8))
+#define OMAP4430_REV_ES2_0      (OMAP443X_CLASS | (0x20 << 8))
+#define OMAP4430_REV_ES2_1      (OMAP443X_CLASS | (0x21 << 8))
+#define OMAP4430_REV_ES2_2      (OMAP443X_CLASS | (0x22 << 8))
 /*
 * omap_chip bits
@@ -417,10 +435,17 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define CHIP_IS_OMAP4430ES1             (1 << 8)
 #define CHIP_IS_OMAP3630ES1_1           (1 << 9)
 #define CHIP_IS_OMAP3630ES1_2           (1 << 10)
+#define CHIP_IS_OMAP4430ES2             (1 << 11)
+#define CHIP_IS_OMAP4430ES2_1           (1 << 12)
+#define CHIP_IS_OMAP4430ES2_2           (1 << 13)
+#define CHIP_IS_TI816X                  (1 << 14)
 #define CHIP_IS_OMAP24XX                (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
-#define CHIP_IS_OMAP4430                (CHIP_IS_OMAP4430ES1)
+#define CHIP_IS_OMAP4430                (CHIP_IS_OMAP4430ES1 |          \
+                                         CHIP_IS_OMAP4430ES2 |          \
+                                         CHIP_IS_OMAP4430ES2_1 |        \
+                                         CHIP_IS_OMAP4430ES2_2)
 /*
 * "GE" here represents "greater than or equal to" in terms of ES
@@ -452,6 +477,7 @@ extern u32 omap3_features;
 #define OMAP3_HAS_ISP                   BIT(4)
 #define OMAP3_HAS_192MHZ_CLK            BIT(5)
 #define OMAP3_HAS_IO_WAKEUP             BIT(6)
+#define OMAP3_HAS_SDRC                  BIT(7)
 #define OMAP3_HAS_FEATURE(feat,flag)                    \
 static inline unsigned int omap3_has_ ##feat(void)      \
@@ -466,5 +492,6 @@ OMAP3_HAS_FEATURE(neon, NEON)
 OMAP3_HAS_FEATURE(isp, ISP)
 OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
 OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
+OMAP3_HAS_FEATURE(sdrc, SDRC)
 #endif
diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h
deleted file mode 100644
index 8bd15bdb4132..000000000000
--- a/arch/arm/plat-omap/include/plat/display.h
+++ /dev/null
@@ -1,591 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/display.h
- *
- * Copyright (C) 2008 Nokia Corporation
- * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#ifndef __ASM_ARCH_OMAP_DISPLAY_H
-#define __ASM_ARCH_OMAP_DISPLAY_H
-#include <linux/list.h>
-#include <linux/kobject.h>
-#include <linux/device.h>
-#include <asm/atomic.h>
-#define DISPC_IRQ_FRAMEDONE             (1 << 0)
-#define DISPC_IRQ_VSYNC                 (1 << 1)
-#define DISPC_IRQ_EVSYNC_EVEN           (1 << 2)
-#define DISPC_IRQ_EVSYNC_ODD            (1 << 3)
-#define DISPC_IRQ_ACBIAS_COUNT_STAT     (1 << 4)
-#define DISPC_IRQ_PROG_LINE_NUM         (1 << 5)
-#define DISPC_IRQ_GFX_FIFO_UNDERFLOW    (1 << 6)
-#define DISPC_IRQ_GFX_END_WIN           (1 << 7)
-#define DISPC_IRQ_PAL_GAMMA_MASK        (1 << 8)
-#define DISPC_IRQ_OCP_ERR               (1 << 9)
-#define DISPC_IRQ_VID1_FIFO_UNDERFLOW   (1 << 10)
-#define DISPC_IRQ_VID1_END_WIN          (1 << 11)
-#define DISPC_IRQ_VID2_FIFO_UNDERFLOW   (1 << 12)
-#define DISPC_IRQ_VID2_END_WIN          (1 << 13)
-#define DISPC_IRQ_SYNC_LOST             (1 << 14)
-#define DISPC_IRQ_SYNC_LOST_DIGIT       (1 << 15)
-#define DISPC_IRQ_WAKEUP                (1 << 16)
-struct omap_dss_device;
-struct omap_overlay_manager;
-enum omap_display_type {
-        OMAP_DISPLAY_TYPE_NONE          = 0,
-        OMAP_DISPLAY_TYPE_DPI           = 1 << 0,
-        OMAP_DISPLAY_TYPE_DBI           = 1 << 1,
-        OMAP_DISPLAY_TYPE_SDI           = 1 << 2,
-        OMAP_DISPLAY_TYPE_DSI           = 1 << 3,
-        OMAP_DISPLAY_TYPE_VENC          = 1 << 4,
-};
-enum omap_plane {
-        OMAP_DSS_GFX    = 0,
-        OMAP_DSS_VIDEO1 = 1,
-        OMAP_DSS_VIDEO2 = 2
-};
-enum omap_channel {
-        OMAP_DSS_CHANNEL_LCD    = 0,
-        OMAP_DSS_CHANNEL_DIGIT  = 1,
-};
-enum omap_color_mode {
-        OMAP_DSS_COLOR_CLUT1    = 1 << 0,  /* BITMAP 1 */
-        OMAP_DSS_COLOR_CLUT2    = 1 << 1,  /* BITMAP 2 */
-        OMAP_DSS_COLOR_CLUT4    = 1 << 2,  /* BITMAP 4 */
-        OMAP_DSS_COLOR_CLUT8    = 1 << 3,  /* BITMAP 8 */
-        OMAP_DSS_COLOR_RGB12U   = 1 << 4,  /* RGB12, 16-bit container */
-        OMAP_DSS_COLOR_ARGB16   = 1 << 5,  /* ARGB16 */
-        OMAP_DSS_COLOR_RGB16    = 1 << 6,  /* RGB16 */
-        OMAP_DSS_COLOR_RGB24U   = 1 << 7,  /* RGB24, 32-bit container */
-        OMAP_DSS_COLOR_RGB24P   = 1 << 8,  /* RGB24, 24-bit container */
-        OMAP_DSS_COLOR_YUV2     = 1 << 9,  /* YUV2 4:2:2 co-sited */
-        OMAP_DSS_COLOR_UYVY     = 1 << 10, /* UYVY 4:2:2 co-sited */
-        OMAP_DSS_COLOR_ARGB32   = 1 << 11, /* ARGB32 */
-        OMAP_DSS_COLOR_RGBA32   = 1 << 12, /* RGBA32 */
-        OMAP_DSS_COLOR_RGBX32   = 1 << 13, /* RGBx32 */
-        OMAP_DSS_COLOR_GFX_OMAP2 =
-                OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
-                OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
-                OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
-                OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
-        OMAP_DSS_COLOR_VID_OMAP2 =
-                OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
-                OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
-                OMAP_DSS_COLOR_UYVY,
-        OMAP_DSS_COLOR_GFX_OMAP3 =
-                OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
-                OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
-                OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
-                OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
-                OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
-                OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
-        OMAP_DSS_COLOR_VID1_OMAP3 =
-                OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
-                OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
-                OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
-        OMAP_DSS_COLOR_VID2_OMAP3 =
-                OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
-                OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
-                OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
-                OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
-                OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
-};
-enum omap_lcd_display_type {
-        OMAP_DSS_LCD_DISPLAY_STN,
-        OMAP_DSS_LCD_DISPLAY_TFT,
-};
-enum omap_dss_load_mode {
-        OMAP_DSS_LOAD_CLUT_AND_FRAME    = 0,
-        OMAP_DSS_LOAD_CLUT_ONLY         = 1,
-        OMAP_DSS_LOAD_FRAME_ONLY        = 2,
-        OMAP_DSS_LOAD_CLUT_ONCE_FRAME   = 3,
-};
-enum omap_dss_trans_key_type {
-        OMAP_DSS_COLOR_KEY_GFX_DST = 0,
-        OMAP_DSS_COLOR_KEY_VID_SRC = 1,
-};
-enum omap_rfbi_te_mode {
-        OMAP_DSS_RFBI_TE_MODE_1 = 1,
-        OMAP_DSS_RFBI_TE_MODE_2 = 2,
-};
-enum omap_panel_config {
-        OMAP_DSS_LCD_IVS                = 1<<0,
-        OMAP_DSS_LCD_IHS                = 1<<1,
-        OMAP_DSS_LCD_IPC                = 1<<2,
-        OMAP_DSS_LCD_IEO                = 1<<3,
-        OMAP_DSS_LCD_RF                 = 1<<4,
-        OMAP_DSS_LCD_ONOFF              = 1<<5,
-        OMAP_DSS_LCD_TFT                = 1<<20,
-};
-enum omap_dss_venc_type {
-        OMAP_DSS_VENC_TYPE_COMPOSITE,
-        OMAP_DSS_VENC_TYPE_SVIDEO,
-};
-enum omap_display_caps {
-        OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE      = 1 << 0,
-        OMAP_DSS_DISPLAY_CAP_TEAR_ELIM          = 1 << 1,
-};
-enum omap_dss_update_mode {
-        OMAP_DSS_UPDATE_DISABLED = 0,
-        OMAP_DSS_UPDATE_AUTO,
-        OMAP_DSS_UPDATE_MANUAL,
-};
-enum omap_dss_display_state {
-        OMAP_DSS_DISPLAY_DISABLED = 0,
-        OMAP_DSS_DISPLAY_ACTIVE,
-        OMAP_DSS_DISPLAY_SUSPENDED,
-};
-/* XXX perhaps this should be removed */
-enum omap_dss_overlay_managers {
-        OMAP_DSS_OVL_MGR_LCD,
-        OMAP_DSS_OVL_MGR_TV,
-};
-enum omap_dss_rotation_type {
-        OMAP_DSS_ROT_DMA = 0,
-        OMAP_DSS_ROT_VRFB = 1,
-};
-/* clockwise rotation angle */
-enum omap_dss_rotation_angle {
-        OMAP_DSS_ROT_0   = 0,
-        OMAP_DSS_ROT_90  = 1,
-        OMAP_DSS_ROT_180 = 2,
-        OMAP_DSS_ROT_270 = 3,
-};
-enum omap_overlay_caps {
-        OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
-        OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
-};
-enum omap_overlay_manager_caps {
-        OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
-};
-/* RFBI */
-struct rfbi_timings {
-        int cs_on_time;
-        int cs_off_time;
-        int we_on_time;
-        int we_off_time;
-        int re_on_time;
-        int re_off_time;
-        int we_cycle_time;
-        int re_cycle_time;
-        int cs_pulse_width;
-        int access_time;
-        int clk_div;
-        u32 tim[5];             /* set by rfbi_convert_timings() */
-        int converted;
-};
-void omap_rfbi_write_command(const void *buf, u32 len);
-void omap_rfbi_read_data(void *buf, u32 len);
-void omap_rfbi_write_data(const void *buf, u32 len);
-void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
-                u16 x, u16 y,
-                u16 w, u16 h);
-int omap_rfbi_enable_te(bool enable, unsigned line);
-int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
-                             unsigned hs_pulse_time, unsigned vs_pulse_time,
-                             int hs_pol_inv, int vs_pol_inv, int extif_div);
-/* DSI */
-void dsi_bus_lock(void);
-void dsi_bus_unlock(void);
-int dsi_vc_dcs_write(int channel, u8 *data, int len);
-int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd);
-int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param);
-int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
-int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
-int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data);
-int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2);
-int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
-int dsi_vc_send_null(int channel);
-int dsi_vc_send_bta_sync(int channel);
-/* Board specific data */
-struct omap_dss_board_info {
-        int (*get_last_off_on_transaction_id)(struct device *dev);
-        int num_devices;
-        struct omap_dss_device **devices;
-        struct omap_dss_device *default_device;
-};
-struct omap_video_timings {
-        /* Unit: pixels */
-        u16 x_res;
-        /* Unit: pixels */
-        u16 y_res;
-        /* Unit: KHz */
-        u32 pixel_clock;
-        /* Unit: pixel clocks */
-        u16 hsw;        /* Horizontal synchronization pulse width */
-        /* Unit: pixel clocks */
-        u16 hfp;        /* Horizontal front porch */
-        /* Unit: pixel clocks */
-        u16 hbp;        /* Horizontal back porch */
-        /* Unit: line clocks */
-        u16 vsw;        /* Vertical synchronization pulse width */
-        /* Unit: line clocks */
-        u16 vfp;        /* Vertical front porch */
-        /* Unit: line clocks */
-        u16 vbp;        /* Vertical back porch */
-};
-#ifdef CONFIG_OMAP2_DSS_VENC
-/* Hardcoded timings for tv modes. Venc only uses these to
- * identify the mode, and does not actually use the configs
- * itself. However, the configs should be something that
- * a normal monitor can also show */
-extern const struct omap_video_timings omap_dss_pal_timings;
-extern const struct omap_video_timings omap_dss_ntsc_timings;
-#endif
-struct omap_overlay_info {
-        bool enabled;
-        u32 paddr;
-        void __iomem *vaddr;
-        u16 screen_width;
-        u16 width;
-        u16 height;
-        enum omap_color_mode color_mode;
-        u8 rotation;
-        enum omap_dss_rotation_type rotation_type;
-        bool mirror;
-        u16 pos_x;
-        u16 pos_y;
-        u16 out_width;  /* if 0, out_width == width */
-        u16 out_height; /* if 0, out_height == height */
-        u8 global_alpha;
-};
-struct omap_overlay {
-        struct kobject kobj;
-        struct list_head list;
-        /* static fields */
-        const char *name;
-        int id;
-        enum omap_color_mode supported_modes;
-        enum omap_overlay_caps caps;
-        /* dynamic fields */
-        struct omap_overlay_manager *manager;
-        struct omap_overlay_info info;
-        /* if true, info has been changed, but not applied() yet */
-        bool info_dirty;
-        int (*set_manager)(struct omap_overlay *ovl,
-                struct omap_overlay_manager *mgr);
-        int (*unset_manager)(struct omap_overlay *ovl);
-        int (*set_overlay_info)(struct omap_overlay *ovl,
-                        struct omap_overlay_info *info);
-        void (*get_overlay_info)(struct omap_overlay *ovl,
-                        struct omap_overlay_info *info);
-        int (*wait_for_go)(struct omap_overlay *ovl);
-};
-struct omap_overlay_manager_info {
-        u32 default_color;
-        enum omap_dss_trans_key_type trans_key_type;
-        u32 trans_key;
-        bool trans_enabled;
-        bool alpha_enabled;
-};
-struct omap_overlay_manager {
-        struct kobject kobj;
-        struct list_head list;
-        /* static fields */
-        const char *name;
-        int id;
-        enum omap_overlay_manager_caps caps;
-        int num_overlays;
-        struct omap_overlay **overlays;
-        enum omap_display_type supported_displays;
-        /* dynamic fields */
-        struct omap_dss_device *device;
-        struct omap_overlay_manager_info info;
-        bool device_changed;
-        /* if true, info has been changed but not applied() yet */
-        bool info_dirty;
-        int (*set_device)(struct omap_overlay_manager *mgr,
-                struct omap_dss_device *dssdev);
-        int (*unset_device)(struct omap_overlay_manager *mgr);
-        int (*set_manager_info)(struct omap_overlay_manager *mgr,
-                        struct omap_overlay_manager_info *info);
-        void (*get_manager_info)(struct omap_overlay_manager *mgr,
-                        struct omap_overlay_manager_info *info);
-        int (*apply)(struct omap_overlay_manager *mgr);
-        int (*wait_for_go)(struct omap_overlay_manager *mgr);
-        int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
-        int (*enable)(struct omap_overlay_manager *mgr);
-        int (*disable)(struct omap_overlay_manager *mgr);
-};
-struct omap_dss_device {
-        struct device dev;
-        enum omap_display_type type;
-        union {
-                struct {
-                        u8 data_lines;
-                } dpi;
-                struct {
-                        u8 channel;
-                        u8 data_lines;
-                } rfbi;
-                struct {
-                        u8 datapairs;
-                } sdi;
-                struct {
-                        u8 clk_lane;
-                        u8 clk_pol;
-                        u8 data1_lane;
-                        u8 data1_pol;
-                        u8 data2_lane;
-                        u8 data2_pol;
-                        struct {
-                                u16 regn;
-                                u16 regm;
-                                u16 regm3;
-                                u16 regm4;
-                                u16 lp_clk_div;
-                                u16 lck_div;
-                                u16 pck_div;
-                        } div;
-                        bool ext_te;
-                        u8 ext_te_gpio;
-                } dsi;
-                struct {
-                        enum omap_dss_venc_type type;
-                        bool invert_polarity;
-                } venc;
-        } phy;
-        struct {
-                struct omap_video_timings timings;
-                int acbi;       /* ac-bias pin transitions per interrupt */
-                /* Unit: line clocks */
-                int acb;        /* ac-bias pin frequency */
-                enum omap_panel_config config;
-        } panel;
-        struct {
-                u8 pixel_size;
-                struct rfbi_timings rfbi_timings;
-        } ctrl;
-        int reset_gpio;
-        int max_backlight_level;
-        const char *name;
-        /* used to match device to driver */
-        const char *driver_name;
-        void *data;
-        struct omap_dss_driver *driver;
-        /* helper variable for driver suspend/resume */
-        bool activate_after_resume;
-        enum omap_display_caps caps;
-        struct omap_overlay_manager *manager;
-        enum omap_dss_display_state state;
-        /* platform specific  */
-        int (*platform_enable)(struct omap_dss_device *dssdev);
-        void (*platform_disable)(struct omap_dss_device *dssdev);
-        int (*set_backlight)(struct omap_dss_device *dssdev, int level);
-        int (*get_backlight)(struct omap_dss_device *dssdev);
-};
-struct omap_dss_driver {
-        struct device_driver driver;
-        int (*probe)(struct omap_dss_device *);
-        void (*remove)(struct omap_dss_device *);
-        int (*enable)(struct omap_dss_device *display);
-        void (*disable)(struct omap_dss_device *display);
-        int (*suspend)(struct omap_dss_device *display);
-        int (*resume)(struct omap_dss_device *display);
-        int (*run_test)(struct omap_dss_device *display, int test);
-        int (*set_update_mode)(struct omap_dss_device *dssdev,
-                        enum omap_dss_update_mode);
-        enum omap_dss_update_mode (*get_update_mode)(
-                        struct omap_dss_device *dssdev);
-        int (*update)(struct omap_dss_device *dssdev,
-                               u16 x, u16 y, u16 w, u16 h);
-        int (*sync)(struct omap_dss_device *dssdev);
-        int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
-        int (*get_te)(struct omap_dss_device *dssdev);
-        u8 (*get_rotate)(struct omap_dss_device *dssdev);
-        int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
-        bool (*get_mirror)(struct omap_dss_device *dssdev);
-        int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
-        int (*memory_read)(struct omap_dss_device *dssdev,
-                        void *buf, size_t size,
-                        u16 x, u16 y, u16 w, u16 h);
-        void (*get_resolution)(struct omap_dss_device *dssdev,
-                        u16 *xres, u16 *yres);
-        int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
-        int (*check_timings)(struct omap_dss_device *dssdev,
-                        struct omap_video_timings *timings);
-        void (*set_timings)(struct omap_dss_device *dssdev,
-                        struct omap_video_timings *timings);
-        void (*get_timings)(struct omap_dss_device *dssdev,
-                        struct omap_video_timings *timings);
-        int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
-        u32 (*get_wss)(struct omap_dss_device *dssdev);
-};
-int omap_dss_register_driver(struct omap_dss_driver *);
-void omap_dss_unregister_driver(struct omap_dss_driver *);
-int omap_dss_register_device(struct omap_dss_device *);
-void omap_dss_unregister_device(struct omap_dss_device *);
-void omap_dss_get_device(struct omap_dss_device *dssdev);
-void omap_dss_put_device(struct omap_dss_device *dssdev);
-#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
-struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
-struct omap_dss_device *omap_dss_find_device(void *data,
-                int (*match)(struct omap_dss_device *dssdev, void *data));
-int omap_dss_start_device(struct omap_dss_device *dssdev);
-void omap_dss_stop_device(struct omap_dss_device *dssdev);
-int omap_dss_get_num_overlay_managers(void);
-struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
-int omap_dss_get_num_overlays(void);
-struct omap_overlay *omap_dss_get_overlay(int num);
-void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
-                u16 *xres, u16 *yres);
-int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
-typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
-int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
-int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
-int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
-int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
-                unsigned long timeout);
-#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
-#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
-void omapdss_dsi_vc_enable_hs(int channel, bool enable);
-int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
-int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
-                                    u16 *x, u16 *y, u16 *w, u16 *h,
-                                    bool enlarge_update_area);
-int omap_dsi_update(struct omap_dss_device *dssdev,
-                int channel,
-                u16 x, u16 y, u16 w, u16 h,
-                void (*callback)(int, void *), void *data);
-int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
-void omapdss_dsi_display_disable(struct omap_dss_device *dssdev);
-int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
-void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
-void dpi_set_timings(struct omap_dss_device *dssdev,
-                        struct omap_video_timings *timings);
-int dpi_check_timings(struct omap_dss_device *dssdev,
-                        struct omap_video_timings *timings);
-int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
-void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
-int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
-void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
-int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
-                u16 *x, u16 *y, u16 *w, u16 *h);
-int omap_rfbi_update(struct omap_dss_device *dssdev,
-                u16 x, u16 y, u16 w, u16 h,
-                void (*callback)(void *), void *data);
-#endif
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index af3a03941add..d1c916fcf770 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -21,141 +21,15 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H
-/* Move omap4 specific defines to dma-44xx.h */
+#include <linux/platform_device.h>
-#include "dma-44xx.h"
-/* Hardware registers for omap1 */
+/*
-#define OMAP1_DMA_BASE                  (0xfffed800)
+ * TODO: These dma channel defines should go away once all
+ * the omap drivers hwmod adapted.
-#define OMAP1_DMA_GCR                   0x400
+ */
-#define OMAP1_DMA_GSCR                  0x404
-#define OMAP1_DMA_GRST                  0x408
-#define OMAP1_DMA_HW_ID                 0x442
-#define OMAP1_DMA_PCH2_ID               0x444
-#define OMAP1_DMA_PCH0_ID               0x446
-#define OMAP1_DMA_PCH1_ID               0x448
-#define OMAP1_DMA_PCHG_ID               0x44a
-#define OMAP1_DMA_PCHD_ID               0x44c
-#define OMAP1_DMA_CAPS_0_U              0x44e
-#define OMAP1_DMA_CAPS_0_L              0x450
-#define OMAP1_DMA_CAPS_1_U              0x452
-#define OMAP1_DMA_CAPS_1_L              0x454
-#define OMAP1_DMA_CAPS_2                0x456
-#define OMAP1_DMA_CAPS_3                0x458
-#define OMAP1_DMA_CAPS_4                0x45a
-#define OMAP1_DMA_PCH2_SR               0x460
-#define OMAP1_DMA_PCH0_SR               0x480
-#define OMAP1_DMA_PCH1_SR               0x482
-#define OMAP1_DMA_PCHD_SR               0x4c0
-/* Hardware registers for omap2 and omap3 */
-#define OMAP24XX_DMA4_BASE              (L4_24XX_BASE + 0x56000)
-#define OMAP34XX_DMA4_BASE              (L4_34XX_BASE + 0x56000)
-#define OMAP44XX_DMA4_BASE              (L4_44XX_BASE + 0x56000)
-#define OMAP_DMA4_REVISION              0x00
-#define OMAP_DMA4_GCR                   0x78
-#define OMAP_DMA4_IRQSTATUS_L0          0x08
-#define OMAP_DMA4_IRQSTATUS_L1          0x0c
-#define OMAP_DMA4_IRQSTATUS_L2          0x10
-#define OMAP_DMA4_IRQSTATUS_L3          0x14
-#define OMAP_DMA4_IRQENABLE_L0          0x18
-#define OMAP_DMA4_IRQENABLE_L1          0x1c
-#define OMAP_DMA4_IRQENABLE_L2          0x20
-#define OMAP_DMA4_IRQENABLE_L3          0x24
-#define OMAP_DMA4_SYSSTATUS             0x28
-#define OMAP_DMA4_OCP_SYSCONFIG         0x2c
-#define OMAP_DMA4_CAPS_0                0x64
-#define OMAP_DMA4_CAPS_2                0x6c
-#define OMAP_DMA4_CAPS_3                0x70
-#define OMAP_DMA4_CAPS_4                0x74
-#define OMAP1_LOGICAL_DMA_CH_COUNT      17
-#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT  32      /* REVISIT: Is this 32 + 2? */
-/* Common channel specific registers for omap1 */
-#define OMAP1_DMA_CH_BASE(n)            (0x40 * (n) + 0x00)
-#define OMAP1_DMA_CSDP(n)               (0x40 * (n) + 0x00)
-#define OMAP1_DMA_CCR(n)                (0x40 * (n) + 0x02)
-#define OMAP1_DMA_CICR(n)               (0x40 * (n) + 0x04)
-#define OMAP1_DMA_CSR(n)                (0x40 * (n) + 0x06)
-#define OMAP1_DMA_CEN(n)                (0x40 * (n) + 0x10)
-#define OMAP1_DMA_CFN(n)                (0x40 * (n) + 0x12)
-#define OMAP1_DMA_CSFI(n)               (0x40 * (n) + 0x14)
-#define OMAP1_DMA_CSEI(n)               (0x40 * (n) + 0x16)
-#define OMAP1_DMA_CPC(n)                (0x40 * (n) + 0x18)     /* 15xx only */
-#define OMAP1_DMA_CSAC(n)               (0x40 * (n) + 0x18)
-#define OMAP1_DMA_CDAC(n)               (0x40 * (n) + 0x1a)
-#define OMAP1_DMA_CDEI(n)               (0x40 * (n) + 0x1c)
-#define OMAP1_DMA_CDFI(n)               (0x40 * (n) + 0x1e)
-#define OMAP1_DMA_CLNK_CTRL(n)          (0x40 * (n) + 0x28)
-/* Common channel specific registers for omap2 */
-#define OMAP_DMA4_CH_BASE(n)            (0x60 * (n) + 0x80)
-#define OMAP_DMA4_CCR(n)                (0x60 * (n) + 0x80)
-#define OMAP_DMA4_CLNK_CTRL(n)          (0x60 * (n) + 0x84)
-#define OMAP_DMA4_CICR(n)               (0x60 * (n) + 0x88)
-#define OMAP_DMA4_CSR(n)                (0x60 * (n) + 0x8c)
-#define OMAP_DMA4_CSDP(n)               (0x60 * (n) + 0x90)
-#define OMAP_DMA4_CEN(n)                (0x60 * (n) + 0x94)
-#define OMAP_DMA4_CFN(n)                (0x60 * (n) + 0x98)
-#define OMAP_DMA4_CSEI(n)               (0x60 * (n) + 0xa4)
-#define OMAP_DMA4_CSFI(n)               (0x60 * (n) + 0xa8)
-#define OMAP_DMA4_CDEI(n)               (0x60 * (n) + 0xac)
-#define OMAP_DMA4_CDFI(n)               (0x60 * (n) + 0xb0)
-#define OMAP_DMA4_CSAC(n)               (0x60 * (n) + 0xb4)
-#define OMAP_DMA4_CDAC(n)               (0x60 * (n) + 0xb8)
-/* Channel specific registers only on omap1 */
-#define OMAP1_DMA_CSSA_L(n)             (0x40 * (n) + 0x08)
-#define OMAP1_DMA_CSSA_U(n)             (0x40 * (n) + 0x0a)
-#define OMAP1_DMA_CDSA_L(n)             (0x40 * (n) + 0x0c)
-#define OMAP1_DMA_CDSA_U(n)             (0x40 * (n) + 0x0e)
-#define OMAP1_DMA_COLOR_L(n)            (0x40 * (n) + 0x20)
-#define OMAP1_DMA_COLOR_U(n)            (0x40 * (n) + 0x22)
-#define OMAP1_DMA_CCR2(n)               (0x40 * (n) + 0x24)
-#define OMAP1_DMA_LCH_CTRL(n)           (0x40 * (n) + 0x2a)     /* not on 15xx */
-#define OMAP1_DMA_CCEN(n)               0
-#define OMAP1_DMA_CCFN(n)               0
-/* Channel specific registers only on omap2 */
-#define OMAP_DMA4_CSSA(n)               (0x60 * (n) + 0x9c)
-#define OMAP_DMA4_CDSA(n)               (0x60 * (n) + 0xa0)
-#define OMAP_DMA4_CCEN(n)               (0x60 * (n) + 0xbc)
-#define OMAP_DMA4_CCFN(n)               (0x60 * (n) + 0xc0)
-#define OMAP_DMA4_COLOR(n)              (0x60 * (n) + 0xc4)
-/* Additional registers available on OMAP4 */
-#define OMAP_DMA4_CDP(n)                (0x60 * (n) + 0xd0)
-#define OMAP_DMA4_CNDP(n)               (0x60 * (n) + 0xd4)
-#define OMAP_DMA4_CCDN(n)               (0x60 * (n) + 0xd8)
-/* Dummy defines to keep multi-omap compiles happy */
-#define OMAP1_DMA_REVISION              0
-#define OMAP1_DMA_IRQSTATUS_L0          0
-#define OMAP1_DMA_IRQENABLE_L0          0
-#define OMAP1_DMA_OCP_SYSCONFIG         0
-#define OMAP_DMA4_HW_ID                 0
-#define OMAP_DMA4_CAPS_0_L              0
-#define OMAP_DMA4_CAPS_0_U              0
-#define OMAP_DMA4_CAPS_1_L              0
-#define OMAP_DMA4_CAPS_1_U              0
-#define OMAP_DMA4_GSCR                  0
-#define OMAP_DMA4_CPC(n)                0
-#define OMAP_DMA4_LCH_CTRL(n)           0
-#define OMAP_DMA4_COLOR_L(n)            0
-#define OMAP_DMA4_COLOR_U(n)            0
-#define OMAP_DMA4_CCR2(n)               0
-#define OMAP1_DMA_CSSA(n)               0
-#define OMAP1_DMA_CDSA(n)               0
-#define OMAP_DMA4_CSSA_L(n)             0
-#define OMAP_DMA4_CSSA_U(n)             0
-#define OMAP_DMA4_CDSA_L(n)             0
-#define OMAP_DMA4_CDSA_U(n)             0
-#define OMAP1_DMA_COLOR(n)              0
-/*----------------------------------------------------------------------------*/
+/* Move omap4 specific defines to dma-44xx.h */
+#include "dma-44xx.h"
 /* DMA channels for omap1 */
 #define OMAP_DMA_NO_DEVICE              0
@@ -319,6 +193,8 @@
 #define OMAP34XX_DMA_USIM_TX            79      /* S_DMA_78 */
 #define OMAP34XX_DMA_USIM_RX            80      /* S_DMA_79 */
+#define OMAP36XX_DMA_UART4_TX           81      /* S_DMA_80 */
+#define OMAP36XX_DMA_UART4_RX           82      /* S_DMA_81 */
 /*----------------------------------------------------------------------------*/
 #define OMAP1_DMA_TOUT_IRQ              (1 << 0)
@@ -335,6 +211,10 @@
 #define OMAP2_DMA_MISALIGNED_ERR_IRQ    (1 << 11)
 #define OMAP_DMA_CCR_EN                 (1 << 7)
+#define OMAP_DMA_CCR_RD_ACTIVE          (1 << 9)
+#define OMAP_DMA_CCR_WR_ACTIVE          (1 << 10)
+#define OMAP_DMA_CCR_SEL_SRC_DST_SYNC   (1 << 24)
+#define OMAP_DMA_CCR_BUFFERING_DISABLE  (1 << 25)
 #define OMAP_DMA_DATA_TYPE_S8           0x00
 #define OMAP_DMA_DATA_TYPE_S16          0x01
@@ -399,6 +279,63 @@
 #define DMA_CH_PRIO_HIGH                0x1
 #define DMA_CH_PRIO_LOW                 0x0 /* Def */
+/* Errata handling */
+#define IS_DMA_ERRATA(id)               (errata & (id))
+#define SET_DMA_ERRATA(id)              (errata |= (id))
+#define DMA_ERRATA_IFRAME_BUFFERING     BIT(0x0)
+#define DMA_ERRATA_PARALLEL_CHANNELS    BIT(0x1)
+#define DMA_ERRATA_i378                 BIT(0x2)
+#define DMA_ERRATA_i541                 BIT(0x3)
+#define DMA_ERRATA_i88                  BIT(0x4)
+#define DMA_ERRATA_3_3                  BIT(0x5)
+#define DMA_ROMCODE_BUG                 BIT(0x6)
+/* Attributes for OMAP DMA Contrller */
+#define DMA_LINKED_LCH                  BIT(0x0)
+#define GLOBAL_PRIORITY                 BIT(0x1)
+#define RESERVE_CHANNEL                 BIT(0x2)
+#define IS_CSSA_32                      BIT(0x3)
+#define IS_CDSA_32                      BIT(0x4)
+#define IS_RW_PRIORITY                  BIT(0x5)
+#define ENABLE_1510_MODE                BIT(0x6)
+#define SRC_PORT                        BIT(0x7)
+#define DST_PORT                        BIT(0x8)
+#define SRC_INDEX                       BIT(0x9)
+#define DST_INDEX                       BIT(0xA)
+#define IS_BURST_ONLY4                  BIT(0xB)
+#define CLEAR_CSR_ON_READ               BIT(0xC)
+#define IS_WORD_16                      BIT(0xD)
+enum omap_reg_offsets {
+GCR,            GSCR,           GRST1,          HW_ID,
+PCH2_ID,        PCH0_ID,        PCH1_ID,        PCHG_ID,
+PCHD_ID,        CAPS_0,         CAPS_1,         CAPS_2,
+CAPS_3,         CAPS_4,         PCH2_SR,        PCH0_SR,
+PCH1_SR,        PCHD_SR,        REVISION,       IRQSTATUS_L0,
+IRQSTATUS_L1,   IRQSTATUS_L2,   IRQSTATUS_L3,   IRQENABLE_L0,
+IRQENABLE_L1,   IRQENABLE_L2,   IRQENABLE_L3,   SYSSTATUS,
+OCP_SYSCONFIG,
+/* omap1+ specific */
+CPC, CCR2, LCH_CTRL,
+/* Common registers for all omap's */
+CSDP,           CCR,            CICR,           CSR,
+CEN,            CFN,            CSFI,           CSEI,
+CSAC,           CDAC,           CDEI,
+CDFI,           CLNK_CTRL,
+/* Channel specific registers */
+CSSA,           CDSA,           COLOR,
+CCEN,           CCFN,
+/* omap3630 and omap4 specific */
+CDP,            CNDP,           CCDN,
+};
 enum omap_dma_burst_mode {
        OMAP_DMA_DATA_BURST_DIS = 0,
        OMAP_DMA_DATA_BURST_4,
@@ -464,6 +401,41 @@ struct omap_dma_channel_params {
 #endif
 };
+struct omap_dma_lch {
+        int next_lch;
+        int dev_id;
+        u16 saved_csr;
+        u16 enabled_irqs;
+        const char *dev_name;
+        void (*callback)(int lch, u16 ch_status, void *data);
+        void *data;
+        long flags;
+        /* required for Dynamic chaining */
+        int prev_linked_ch;
+        int next_linked_ch;
+        int state;
+        int chain_id;
+        int status;
+};
+struct omap_dma_dev_attr {
+        u32 dev_caps;
+        u16 lch_count;
+        u16 chan_count;
+        struct omap_dma_lch *chan;
+};
+/* System DMA platform data structure */
+struct omap_system_dma_plat_info {
+        struct omap_dma_dev_attr *dma_attr;
+        u32 errata;
+        void (*disable_irq_lch)(int lch);
+        void (*show_dma_caps)(void);
+        void (*clear_lch_regs)(int lch);
+        void (*clear_dma)(int lch);
+        void (*dma_write)(u32 val, int reg, int lch);
+        u32 (*dma_read)(int reg, int lch);
+};
 extern void omap_set_dma_priority(int lch, int dst_port, int priority);
 extern int omap_request_dma(int dev_id, const char *dev_name,
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 20f1054c0a80..d6c70d2f4030 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -3,6 +3,12 @@
 *
 * OMAP Dual-Mode Timers
 *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Tarun Kanti DebBarma <tarun.kanti@ti.com>
+ * Thara Gopinath <thara@ti.com>
+ *
+ * Platform device conversion and hwmod support.
+ *
 * Copyright (C) 2005 Nokia Corporation
 * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
 * PWM and clock framwork support by Timo Teras.
@@ -44,7 +50,14 @@
 #define OMAP_TIMER_TRIGGER_OVERFLOW             0x01
 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
+/*
+ * IP revision identifier so that Highlander IP
+ * in OMAP4 can be distinguished.
+ */
+#define OMAP_TIMER_IP_VERSION_1                        0x1
 struct omap_dm_timer;
+extern struct omap_dm_timer *gptimer_wakeup;
+extern struct sys_timer omap_timer;
 struct clk;
 int omap_dm_timer_init(void);
diff --git a/arch/arm/plat-omap/include/plat/dsp.h b/arch/arm/plat-omap/include/plat/dsp.h
new file mode 100644
index 000000000000..9c604b390f9f
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/dsp.h
@@ -0,0 +1,31 @@
+#ifndef __OMAP_DSP_H__
+#define __OMAP_DSP_H__
+#include <linux/types.h>
+struct omap_dsp_platform_data {
+        void (*dsp_set_min_opp) (u8 opp_id);
+        u8 (*dsp_get_opp) (void);
+        void (*cpu_set_freq) (unsigned long f);
+        unsigned long (*cpu_get_freq) (void);
+        unsigned long mpu_speed[6];
+        /* functions to write and read PRCM registers */
+        void (*dsp_prm_write)(u32, s16 , u16);
+        u32 (*dsp_prm_read)(s16 , u16);
+        u32 (*dsp_prm_rmw_bits)(u32, u32, s16, s16);
+        void (*dsp_cm_write)(u32, s16 , u16);
+        u32 (*dsp_cm_read)(s16 , u16);
+        u32 (*dsp_cm_rmw_bits)(u32, u32, s16, s16);
+        phys_addr_t phys_mempool_base;
+        phys_addr_t phys_mempool_size;
+};
+#if defined(CONFIG_TIDSPBRIDGE) || defined(CONFIG_TIDSPBRIDGE_MODULE)
+extern void omap_dsp_reserve_sdram_memblock(void);
+#else
+static inline void omap_dsp_reserve_sdram_memblock(void) { }
+#endif
+#endif
diff --git a/arch/arm/plat-omap/include/plat/flash.h b/arch/arm/plat-omap/include/plat/flash.h
index 3e6327016b40..0d88499b79e9 100644
--- a/arch/arm/plat-omap/include/plat/flash.h
+++ b/arch/arm/plat-omap/include/plat/flash.h
@@ -11,6 +11,7 @@
 #include <linux/mtd/map.h>
-extern void omap1_set_vpp(struct map_info *map, int enable);
+struct platform_device;
+extern void omap1_set_vpp(struct platform_device *pdev, int enable);
 #endif
diff --git a/arch/arm/plat-omap/include/plat/fpga.h b/arch/arm/plat-omap/include/plat/fpga.h
index f1864a652f7a..bd3c6324ae1f 100644
--- a/arch/arm/plat-omap/include/plat/fpga.h
+++ b/arch/arm/plat-omap/include/plat/fpga.h
@@ -19,11 +19,7 @@
 #ifndef __ASM_ARCH_OMAP_FPGA_H
 #define __ASM_ARCH_OMAP_FPGA_H
-#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
 extern void omap1510_fpga_init_irq(void);
-#else
-#define omap1510_fpga_init_irq()        (0)
-#endif
 #define fpga_read(reg)                  __raw_readb(reg)
 #define fpga_write(val, reg)            __raw_writeb(val, reg)
@@ -34,18 +30,18 @@ extern void omap1510_fpga_init_irq(void);
 * ---------------------------------------------------------------------------
 */
 /* maps in the FPGA registers and the ETHR registers */
-#define H2P2_DBG_FPGA_BASE              IOMEM(0xE8000000)       /* VA */
+#define H2P2_DBG_FPGA_BASE              0xE8000000              /* VA */
 #define H2P2_DBG_FPGA_SIZE              SZ_4K                   /* SIZE */
 #define H2P2_DBG_FPGA_START             0x04000000              /* PA */
 #define H2P2_DBG_FPGA_ETHR_START        (H2P2_DBG_FPGA_START + 0x300)
-#define H2P2_DBG_FPGA_FPGA_REV          (H2P2_DBG_FPGA_BASE + 0x10)     /* FPGA Revision */
+#define H2P2_DBG_FPGA_FPGA_REV          IOMEM(H2P2_DBG_FPGA_BASE + 0x10)        /* FPGA Revision */
-#define H2P2_DBG_FPGA_BOARD_REV         (H2P2_DBG_FPGA_BASE + 0x12)     /* Board Revision */
+#define H2P2_DBG_FPGA_BOARD_REV         IOMEM(H2P2_DBG_FPGA_BASE + 0x12)        /* Board Revision */
-#define H2P2_DBG_FPGA_GPIO              (H2P2_DBG_FPGA_BASE + 0x14)     /* GPIO outputs */
+#define H2P2_DBG_FPGA_GPIO              IOMEM(H2P2_DBG_FPGA_BASE + 0x14)        /* GPIO outputs */
-#define H2P2_DBG_FPGA_LEDS              (H2P2_DBG_FPGA_BASE + 0x16)     /* LEDs outputs */
+#define H2P2_DBG_FPGA_LEDS              IOMEM(H2P2_DBG_FPGA_BASE + 0x16)        /* LEDs outputs */
-#define H2P2_DBG_FPGA_MISC_INPUTS       (H2P2_DBG_FPGA_BASE + 0x18)     /* Misc inputs */
+#define H2P2_DBG_FPGA_MISC_INPUTS       IOMEM(H2P2_DBG_FPGA_BASE + 0x18)        /* Misc inputs */
-#define H2P2_DBG_FPGA_LAN_STATUS        (H2P2_DBG_FPGA_BASE + 0x1A)     /* LAN Status line */
+#define H2P2_DBG_FPGA_LAN_STATUS        IOMEM(H2P2_DBG_FPGA_BASE + 0x1A)        /* LAN Status line */
-#define H2P2_DBG_FPGA_LAN_RESET         (H2P2_DBG_FPGA_BASE + 0x1C)     /* LAN Reset line */
+#define H2P2_DBG_FPGA_LAN_RESET         IOMEM(H2P2_DBG_FPGA_BASE + 0x1C)        /* LAN Reset line */
 /* NOTE:  most boards don't have a static mapping for the FPGA ... */
 struct h2p2_dbg_fpga {
@@ -85,55 +81,55 @@ struct h2p2_dbg_fpga {
 *  OMAP-1510 FPGA
 * ---------------------------------------------------------------------------
 */
-#define OMAP1510_FPGA_BASE              IOMEM(0xE8000000)       /* VA */
+#define OMAP1510_FPGA_BASE              0xE8000000              /* VA */
 #define OMAP1510_FPGA_SIZE              SZ_4K
 #define OMAP1510_FPGA_START             0x08000000              /* PA */
 /* Revision */
-#define OMAP1510_FPGA_REV_LOW                   (OMAP1510_FPGA_BASE + 0x0)
+#define OMAP1510_FPGA_REV_LOW                   IOMEM(OMAP1510_FPGA_BASE + 0x0)
-#define OMAP1510_FPGA_REV_HIGH                  (OMAP1510_FPGA_BASE + 0x1)
+#define OMAP1510_FPGA_REV_HIGH                  IOMEM(OMAP1510_FPGA_BASE + 0x1)
-#define OMAP1510_FPGA_LCD_PANEL_CONTROL         (OMAP1510_FPGA_BASE + 0x2)
+#define OMAP1510_FPGA_LCD_PANEL_CONTROL         IOMEM(OMAP1510_FPGA_BASE + 0x2)
-#define OMAP1510_FPGA_LED_DIGIT                 (OMAP1510_FPGA_BASE + 0x3)
+#define OMAP1510_FPGA_LED_DIGIT                 IOMEM(OMAP1510_FPGA_BASE + 0x3)
-#define INNOVATOR_FPGA_HID_SPI                  (OMAP1510_FPGA_BASE + 0x4)
+#define INNOVATOR_FPGA_HID_SPI                  IOMEM(OMAP1510_FPGA_BASE + 0x4)
-#define OMAP1510_FPGA_POWER                     (OMAP1510_FPGA_BASE + 0x5)
+#define OMAP1510_FPGA_POWER                     IOMEM(OMAP1510_FPGA_BASE + 0x5)
 /* Interrupt status */
-#define OMAP1510_FPGA_ISR_LO                    (OMAP1510_FPGA_BASE + 0x6)
+#define OMAP1510_FPGA_ISR_LO                    IOMEM(OMAP1510_FPGA_BASE + 0x6)
-#define OMAP1510_FPGA_ISR_HI                    (OMAP1510_FPGA_BASE + 0x7)
+#define OMAP1510_FPGA_ISR_HI                    IOMEM(OMAP1510_FPGA_BASE + 0x7)
 /* Interrupt mask */
-#define OMAP1510_FPGA_IMR_LO                    (OMAP1510_FPGA_BASE + 0x8)
+#define OMAP1510_FPGA_IMR_LO                    IOMEM(OMAP1510_FPGA_BASE + 0x8)
-#define OMAP1510_FPGA_IMR_HI                    (OMAP1510_FPGA_BASE + 0x9)
+#define OMAP1510_FPGA_IMR_HI                    IOMEM(OMAP1510_FPGA_BASE + 0x9)
 /* Reset registers */
-#define OMAP1510_FPGA_HOST_RESET                (OMAP1510_FPGA_BASE + 0xa)
+#define OMAP1510_FPGA_HOST_RESET                IOMEM(OMAP1510_FPGA_BASE + 0xa)
-#define OMAP1510_FPGA_RST                       (OMAP1510_FPGA_BASE + 0xb)
+#define OMAP1510_FPGA_RST                       IOMEM(OMAP1510_FPGA_BASE + 0xb)
-#define OMAP1510_FPGA_AUDIO                     (OMAP1510_FPGA_BASE + 0xc)
+#define OMAP1510_FPGA_AUDIO                     IOMEM(OMAP1510_FPGA_BASE + 0xc)
-#define OMAP1510_FPGA_DIP                       (OMAP1510_FPGA_BASE + 0xe)
+#define OMAP1510_FPGA_DIP                       IOMEM(OMAP1510_FPGA_BASE + 0xe)
-#define OMAP1510_FPGA_FPGA_IO                   (OMAP1510_FPGA_BASE + 0xf)
+#define OMAP1510_FPGA_FPGA_IO                   IOMEM(OMAP1510_FPGA_BASE + 0xf)
-#define OMAP1510_FPGA_UART1                     (OMAP1510_FPGA_BASE + 0x14)
+#define OMAP1510_FPGA_UART1                     IOMEM(OMAP1510_FPGA_BASE + 0x14)
-#define OMAP1510_FPGA_UART2                     (OMAP1510_FPGA_BASE + 0x15)
+#define OMAP1510_FPGA_UART2                     IOMEM(OMAP1510_FPGA_BASE + 0x15)
-#define OMAP1510_FPGA_OMAP1510_STATUS           (OMAP1510_FPGA_BASE + 0x16)
+#define OMAP1510_FPGA_OMAP1510_STATUS           IOMEM(OMAP1510_FPGA_BASE + 0x16)
-#define OMAP1510_FPGA_BOARD_REV                 (OMAP1510_FPGA_BASE + 0x18)
+#define OMAP1510_FPGA_BOARD_REV                 IOMEM(OMAP1510_FPGA_BASE + 0x18)
-#define OMAP1510P1_PPT_DATA                     (OMAP1510_FPGA_BASE + 0x100)
+#define OMAP1510P1_PPT_DATA                     IOMEM(OMAP1510_FPGA_BASE + 0x100)
-#define OMAP1510P1_PPT_STATUS                   (OMAP1510_FPGA_BASE + 0x101)
+#define OMAP1510P1_PPT_STATUS                   IOMEM(OMAP1510_FPGA_BASE + 0x101)
-#define OMAP1510P1_PPT_CONTROL                  (OMAP1510_FPGA_BASE + 0x102)
+#define OMAP1510P1_PPT_CONTROL                  IOMEM(OMAP1510_FPGA_BASE + 0x102)
-#define OMAP1510_FPGA_TOUCHSCREEN               (OMAP1510_FPGA_BASE + 0x204)
+#define OMAP1510_FPGA_TOUCHSCREEN               IOMEM(OMAP1510_FPGA_BASE + 0x204)
-#define INNOVATOR_FPGA_INFO                     (OMAP1510_FPGA_BASE + 0x205)
+#define INNOVATOR_FPGA_INFO                     IOMEM(OMAP1510_FPGA_BASE + 0x205)
-#define INNOVATOR_FPGA_LCD_BRIGHT_LO            (OMAP1510_FPGA_BASE + 0x206)
+#define INNOVATOR_FPGA_LCD_BRIGHT_LO            IOMEM(OMAP1510_FPGA_BASE + 0x206)
-#define INNOVATOR_FPGA_LCD_BRIGHT_HI            (OMAP1510_FPGA_BASE + 0x207)
+#define INNOVATOR_FPGA_LCD_BRIGHT_HI            IOMEM(OMAP1510_FPGA_BASE + 0x207)
-#define INNOVATOR_FPGA_LED_GRN_LO               (OMAP1510_FPGA_BASE + 0x208)
+#define INNOVATOR_FPGA_LED_GRN_LO               IOMEM(OMAP1510_FPGA_BASE + 0x208)
-#define INNOVATOR_FPGA_LED_GRN_HI               (OMAP1510_FPGA_BASE + 0x209)
+#define INNOVATOR_FPGA_LED_GRN_HI               IOMEM(OMAP1510_FPGA_BASE + 0x209)
-#define INNOVATOR_FPGA_LED_RED_LO               (OMAP1510_FPGA_BASE + 0x20a)
+#define INNOVATOR_FPGA_LED_RED_LO               IOMEM(OMAP1510_FPGA_BASE + 0x20a)
-#define INNOVATOR_FPGA_LED_RED_HI               (OMAP1510_FPGA_BASE + 0x20b)
+#define INNOVATOR_FPGA_LED_RED_HI               IOMEM(OMAP1510_FPGA_BASE + 0x20b)
-#define INNOVATOR_FPGA_CAM_USB_CONTROL          (OMAP1510_FPGA_BASE + 0x20c)
+#define INNOVATOR_FPGA_CAM_USB_CONTROL          IOMEM(OMAP1510_FPGA_BASE + 0x20c)
-#define INNOVATOR_FPGA_EXP_CONTROL              (OMAP1510_FPGA_BASE + 0x20d)
+#define INNOVATOR_FPGA_EXP_CONTROL              IOMEM(OMAP1510_FPGA_BASE + 0x20d)
-#define INNOVATOR_FPGA_ISR2                     (OMAP1510_FPGA_BASE + 0x20e)
+#define INNOVATOR_FPGA_ISR2                     IOMEM(OMAP1510_FPGA_BASE + 0x20e)
-#define INNOVATOR_FPGA_IMR2                     (OMAP1510_FPGA_BASE + 0x210)
+#define INNOVATOR_FPGA_IMR2                     IOMEM(OMAP1510_FPGA_BASE + 0x210)
 #define OMAP1510_FPGA_ETHR_START                (OMAP1510_FPGA_START + 0x300)
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index de1c604962eb..ec97e00cb581 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -27,26 +27,15 @@
 #define __ASM_ARCH_OMAP_GPIO_H
 #include <linux/io.h>
+#include <linux/platform_device.h>
 #include <mach/irqs.h>
 #define OMAP1_MPUIO_BASE                        0xfffb5000
-#if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850))
+/*
+ * These are the omap15xx/16xx offsets. The omap7xx offset are
-#define OMAP_MPUIO_INPUT_LATCH          0x00
+ * OMAP_MPUIO_ / 2 offsets below.
-#define OMAP_MPUIO_OUTPUT               0x02
+ */
-#define OMAP_MPUIO_IO_CNTL              0x04
-#define OMAP_MPUIO_KBR_LATCH            0x08
-#define OMAP_MPUIO_KBC                  0x0a
-#define OMAP_MPUIO_GPIO_EVENT_MODE      0x0c
-#define OMAP_MPUIO_GPIO_INT_EDGE        0x0e
-#define OMAP_MPUIO_KBD_INT              0x10
-#define OMAP_MPUIO_GPIO_INT             0x12
-#define OMAP_MPUIO_KBD_MASKIT           0x14
-#define OMAP_MPUIO_GPIO_MASKIT          0x16
-#define OMAP_MPUIO_GPIO_DEBOUNCING      0x18
-#define OMAP_MPUIO_LATCH                0x1a
-#else
 #define OMAP_MPUIO_INPUT_LATCH          0x00
 #define OMAP_MPUIO_OUTPUT               0x04
 #define OMAP_MPUIO_IO_CNTL              0x08
@@ -60,10 +49,112 @@
 #define OMAP_MPUIO_GPIO_MASKIT          0x2c
 #define OMAP_MPUIO_GPIO_DEBOUNCING      0x30
 #define OMAP_MPUIO_LATCH                0x34
-#endif
 #define OMAP34XX_NR_GPIOS               6
+/*
+ * OMAP1510 GPIO registers
+ */
+#define OMAP1510_GPIO_DATA_INPUT        0x00
+#define OMAP1510_GPIO_DATA_OUTPUT       0x04
+#define OMAP1510_GPIO_DIR_CONTROL       0x08
+#define OMAP1510_GPIO_INT_CONTROL       0x0c
+#define OMAP1510_GPIO_INT_MASK          0x10
+#define OMAP1510_GPIO_INT_STATUS        0x14
+#define OMAP1510_GPIO_PIN_CONTROL       0x18
+#define OMAP1510_IH_GPIO_BASE           64
+/*
+ * OMAP1610 specific GPIO registers
+ */
+#define OMAP1610_GPIO_REVISION          0x0000
+#define OMAP1610_GPIO_SYSCONFIG         0x0010
+#define OMAP1610_GPIO_SYSSTATUS         0x0014
+#define OMAP1610_GPIO_IRQSTATUS1        0x0018
+#define OMAP1610_GPIO_IRQENABLE1        0x001c
+#define OMAP1610_GPIO_WAKEUPENABLE      0x0028
+#define OMAP1610_GPIO_DATAIN            0x002c
+#define OMAP1610_GPIO_DATAOUT           0x0030
+#define OMAP1610_GPIO_DIRECTION         0x0034
+#define OMAP1610_GPIO_EDGE_CTRL1        0x0038
+#define OMAP1610_GPIO_EDGE_CTRL2        0x003c
+#define OMAP1610_GPIO_CLEAR_IRQENABLE1  0x009c
+#define OMAP1610_GPIO_CLEAR_WAKEUPENA   0x00a8
+#define OMAP1610_GPIO_CLEAR_DATAOUT     0x00b0
+#define OMAP1610_GPIO_SET_IRQENABLE1    0x00dc
+#define OMAP1610_GPIO_SET_WAKEUPENA     0x00e8
+#define OMAP1610_GPIO_SET_DATAOUT       0x00f0
+/*
+ * OMAP7XX specific GPIO registers
+ */
+#define OMAP7XX_GPIO_DATA_INPUT         0x00
+#define OMAP7XX_GPIO_DATA_OUTPUT        0x04
+#define OMAP7XX_GPIO_DIR_CONTROL        0x08
+#define OMAP7XX_GPIO_INT_CONTROL        0x0c
+#define OMAP7XX_GPIO_INT_MASK           0x10
+#define OMAP7XX_GPIO_INT_STATUS         0x14
+/*
+ * omap2+ specific GPIO registers
+ */
+#define OMAP24XX_GPIO_REVISION          0x0000
+#define OMAP24XX_GPIO_IRQSTATUS1        0x0018
+#define OMAP24XX_GPIO_IRQSTATUS2        0x0028
+#define OMAP24XX_GPIO_IRQENABLE2        0x002c
+#define OMAP24XX_GPIO_IRQENABLE1        0x001c
+#define OMAP24XX_GPIO_WAKE_EN           0x0020
+#define OMAP24XX_GPIO_CTRL              0x0030
+#define OMAP24XX_GPIO_OE                0x0034
+#define OMAP24XX_GPIO_DATAIN            0x0038
+#define OMAP24XX_GPIO_DATAOUT           0x003c
+#define OMAP24XX_GPIO_LEVELDETECT0      0x0040
+#define OMAP24XX_GPIO_LEVELDETECT1      0x0044
+#define OMAP24XX_GPIO_RISINGDETECT      0x0048
+#define OMAP24XX_GPIO_FALLINGDETECT     0x004c
+#define OMAP24XX_GPIO_DEBOUNCE_EN       0x0050
+#define OMAP24XX_GPIO_DEBOUNCE_VAL      0x0054
+#define OMAP24XX_GPIO_CLEARIRQENABLE1   0x0060
+#define OMAP24XX_GPIO_SETIRQENABLE1     0x0064
+#define OMAP24XX_GPIO_CLEARWKUENA       0x0080
+#define OMAP24XX_GPIO_SETWKUENA         0x0084
+#define OMAP24XX_GPIO_CLEARDATAOUT      0x0090
+#define OMAP24XX_GPIO_SETDATAOUT        0x0094
+#define OMAP4_GPIO_REVISION             0x0000
+#define OMAP4_GPIO_EOI                  0x0020
+#define OMAP4_GPIO_IRQSTATUSRAW0        0x0024
+#define OMAP4_GPIO_IRQSTATUSRAW1        0x0028
+#define OMAP4_GPIO_IRQSTATUS0           0x002c
+#define OMAP4_GPIO_IRQSTATUS1           0x0030
+#define OMAP4_GPIO_IRQSTATUSSET0        0x0034
+#define OMAP4_GPIO_IRQSTATUSSET1        0x0038
+#define OMAP4_GPIO_IRQSTATUSCLR0        0x003c
+#define OMAP4_GPIO_IRQSTATUSCLR1        0x0040
+#define OMAP4_GPIO_IRQWAKEN0            0x0044
+#define OMAP4_GPIO_IRQWAKEN1            0x0048
+#define OMAP4_GPIO_IRQENABLE1           0x011c
+#define OMAP4_GPIO_WAKE_EN              0x0120
+#define OMAP4_GPIO_IRQSTATUS2           0x0128
+#define OMAP4_GPIO_IRQENABLE2           0x012c
+#define OMAP4_GPIO_CTRL                 0x0130
+#define OMAP4_GPIO_OE                   0x0134
+#define OMAP4_GPIO_DATAIN               0x0138
+#define OMAP4_GPIO_DATAOUT              0x013c
+#define OMAP4_GPIO_LEVELDETECT0         0x0140
+#define OMAP4_GPIO_LEVELDETECT1         0x0144
+#define OMAP4_GPIO_RISINGDETECT         0x0148
+#define OMAP4_GPIO_FALLINGDETECT        0x014c
+#define OMAP4_GPIO_DEBOUNCENABLE        0x0150
+#define OMAP4_GPIO_DEBOUNCINGTIME       0x0154
+#define OMAP4_GPIO_CLEARIRQENABLE1      0x0160
+#define OMAP4_GPIO_SETIRQENABLE1        0x0164
+#define OMAP4_GPIO_CLEARWKUENA          0x0180
+#define OMAP4_GPIO_SETWKUENA            0x0184
+#define OMAP4_GPIO_CLEARDATAOUT         0x0190
+#define OMAP4_GPIO_SETDATAOUT           0x0194
 #define OMAP_MPUIO(nr)          (OMAP_MAX_GPIO_LINES + (nr))
 #define OMAP_GPIO_IS_MPUIO(nr)  ((nr) >= OMAP_MAX_GPIO_LINES)
@@ -71,8 +162,30 @@
                                 IH_MPUIO_BASE + ((nr) & 0x0f) : \
                                 IH_GPIO_BASE + (nr))
-extern int omap_gpio_init(void);        /* Call from board init only */
+#define METHOD_MPUIO            0
-extern void omap2_gpio_prepare_for_idle(int power_state);
+#define METHOD_GPIO_1510        1
+#define METHOD_GPIO_1610        2
+#define METHOD_GPIO_7XX         3
+#define METHOD_GPIO_24XX        5
+#define METHOD_GPIO_44XX        6
+struct omap_gpio_dev_attr {
+        int bank_width;         /* GPIO bank width */
+        bool dbck_flag;         /* dbck required or not - True for OMAP3&4 */
+};
+struct omap_gpio_platform_data {
+        u16 virtual_irq_start;
+        int bank_type;
+        int bank_width;         /* GPIO bank width */
+        int bank_stride;        /* Only needed for omap1 MPUIO */
+        bool dbck_flag;         /* dbck required or not - True for OMAP3&4 */
+};
+/* TODO: Analyze removing gpio_bank_count usage from driver code */
+extern int gpio_bank_count;
+extern void omap2_gpio_prepare_for_idle(int off_mode);
 extern void omap2_gpio_resume_after_idle(void);
 extern void omap_set_gpio_debounce(int gpio, int enable);
 extern void omap_set_gpio_debounce_time(int gpio, int enable);
@@ -83,7 +196,7 @@ extern void omap_gpio_restore_context(void);
 /* Wrappers for "new style" GPIO calls, using the new infrastructure
 * which lets us plug in FPGA, I2C, and other implementations.
 * *
- * The original OMAP-specfic calls should eventually be removed.
+ * The original OMAP-specific calls should eventually be removed.
 */
 #include <linux/errno.h>
diff --git a/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h b/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
new file mode 100644
index 000000000000..ea6c9c88c725
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
+ *
+ * Copyright (C) 2009 Li-Pro.Net
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * Modified from arch/arm/plat-omap/include/plat/gpmc-smc91x.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_OMAP_GPMC_SMSC911X_H__
+struct omap_smsc911x_platform_data {
+        int     id;
+        int     cs;
+        int     gpio_irq;
+        int     gpio_reset;
+        u32     flags;
+};
+#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+extern void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d);
+#else
+static inline void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d)
+{
+}
+#endif
+#endif
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 9fd99b9e40ab..1527929b445a 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -41,6 +41,8 @@
 #define GPMC_NAND_ADDRESS       0x0000000b
 #define GPMC_NAND_DATA          0x0000000c
+#define GPMC_ENABLE_IRQ         0x0000000d
 /* ECC commands */
 #define GPMC_ECC_READ           0 /* Reset Hardware ECC for read */
 #define GPMC_ECC_WRITE          1 /* Reset Hardware ECC for write */
@@ -78,14 +80,27 @@
 #define WR_RD_PIN_MONITORING            0x00600000
 #define GPMC_PREFETCH_STATUS_FIFO_CNT(val)      ((val >> 24) & 0x7F)
 #define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
+#define GPMC_IRQ_FIFOEVENTENABLE        0x01
+#define GPMC_IRQ_COUNT_EVENT            0x02
+#define PREFETCH_FIFOTHRESHOLD_MAX      0x40
+#define PREFETCH_FIFOTHRESHOLD(val)     ((val) << 8)
+enum omap_ecc {
+                /* 1-bit ecc: stored at end of spare area */
+        OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
+        OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
+                /* 1-bit ecc: stored at beginning of spare area as romcode */
+        OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
+};
 /*
- * Note that all values in this struct are in nanoseconds, while
+ * Note that all values in this struct are in nanoseconds except sync_clk
- * the register values are in gpmc_fck cycles.
+ * (which is in picoseconds), while the register values are in gpmc_fck cycles.
 */
 struct gpmc_timings {
-        /* Minimum clock period for synchronous mode */
+        /* Minimum clock period for synchronous mode (in picoseconds) */
-        u16 sync_clk;
+        u32 sync_clk;
        /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
        u16 cs_on;              /* Assertion time */
@@ -117,6 +132,7 @@ struct gpmc_timings {
 };
 extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
+extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
 extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
 extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
 extern unsigned long gpmc_get_fclk_period(void);
@@ -129,12 +145,11 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
 extern void gpmc_cs_free(int cs);
 extern int gpmc_cs_set_reserved(int cs, int reserved);
 extern int gpmc_cs_reserved(int cs);
-extern int gpmc_prefetch_enable(int cs, int dma_mode,
+extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
                                        unsigned int u32_count, int is_write);
 extern int gpmc_prefetch_reset(int cs);
 extern void omap3_gpmc_save_context(void);
 extern void omap3_gpmc_restore_context(void);
-extern void gpmc_init(void);
 extern int gpmc_read_status(int cmd);
 extern int gpmc_cs_configure(int cs, int cmd, int wval);
 extern int gpmc_nand_read(int cs, int cmd);
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index d5b26adfb890..e87efe1499b8 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -286,5 +286,6 @@
 #include <plat/omap24xx.h>
 #include <plat/omap34xx.h>
 #include <plat/omap44xx.h>
+#include <plat/ti816x.h>
 #endif  /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
index 87f6bf2ea4fa..878d632c4092 100644
--- a/arch/arm/plat-omap/include/plat/i2c.h
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -18,6 +18,8 @@
 * 02110-1301 USA
 *
 */
+#ifndef __ASM__ARCH_OMAP_I2C_H
+#define __ASM__ARCH_OMAP_I2C_H
 #include <linux/i2c.h>
@@ -34,5 +36,20 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
 }
 #endif
+/**
+ * i2c_dev_attr - OMAP I2C controller device attributes for omap_hwmod
+ * @fifo_depth: total controller FIFO size (in bytes)
+ * @flags: differences in hardware support capability
+ *
+ * @fifo_depth represents what exists on the hardware, not what is
+ * actually configured at runtime by the device driver.
+ */
+struct omap_i2c_dev_attr {
+        u8      fifo_depth;
+        u8      flags;
+};
 void __init omap1_i2c_mux_pins(int bus_id);
 void __init omap2_i2c_mux_pins(int bus_id);
+#endif /* __ASM__ARCH_OMAP_I2C_H */
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index 128b549c2796..d72ec85c97e6 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -259,7 +259,7 @@ struct omap_sdrc_params;
 extern void omap1_map_common_io(void);
 extern void omap1_init_common_hw(void);
-#ifdef CONFIG_ARCH_OMAP2420
+#ifdef CONFIG_SOC_OMAP2420
 extern void omap242x_map_common_io(void);
 #else
 static inline void omap242x_map_common_io(void)
@@ -267,7 +267,7 @@ static inline void omap242x_map_common_io(void)
 }
 #endif
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 extern void omap243x_map_common_io(void);
 #else
 static inline void omap243x_map_common_io(void)
@@ -283,6 +283,14 @@ static inline void omap34xx_map_common_io(void)
 }
 #endif
+#ifdef CONFIG_SOC_OMAPTI816X
+extern void omapti816x_map_common_io(void);
+#else
+static inline void omapti816x_map_common_io(void)
+{
+}
+#endif
 #ifdef CONFIG_ARCH_OMAP4
 extern void omap44xx_map_common_io(void);
 #else
@@ -291,11 +299,12 @@ static inline void omap44xx_map_common_io(void)
 }
 #endif
-extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
+extern void omap2_init_common_infrastructure(void);
-                                 struct omap_sdrc_params *sdrc_cs1);
+extern void omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
+                                      struct omap_sdrc_params *sdrc_cs1);
-#define __arch_ioremap(p,s,t)   omap_ioremap(p,s,t)
+#define __arch_ioremap  omap_ioremap
-#define __arch_iounmap(v)       omap_iounmap(v)
+#define __arch_iounmap  omap_iounmap
 void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
 void omap_iounmap(volatile void __iomem *addr);
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 33c7d41cb6a5..174f1b9c8c03 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -31,6 +31,7 @@ struct iommu {
        struct clk      *clk;
        void __iomem    *regbase;
        struct device   *dev;
+        void            *isr_priv;
        unsigned int    refcount;
        struct mutex    iommu_lock;     /* global for this whole object */
@@ -47,9 +48,11 @@ struct iommu {
        struct list_head        mmap;
        struct mutex            mmap_lock; /* protect mmap */
-        int (*isr)(struct iommu *obj);
+        int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, void *priv);
        void *ctx; /* iommu context: registres saved area */
+        u32 da_start;
+        u32 da_end;
 };
 struct cr_regs {
@@ -103,8 +106,17 @@ struct iommu_platform_data {
        const char *name;
        const char *clk_name;
        const int nr_tlb_entries;
+        u32 da_start;
+        u32 da_end;
 };
+/* IOMMU errors */
+#define OMAP_IOMMU_ERR_TLB_MISS         (1 << 0)
+#define OMAP_IOMMU_ERR_TRANS_FAULT      (1 << 1)
+#define OMAP_IOMMU_ERR_EMU_MISS         (1 << 2)
+#define OMAP_IOMMU_ERR_TBLWALK_FAULT    (1 << 3)
+#define OMAP_IOMMU_ERR_MULTIHIT_FAULT   (1 << 4)
 #if defined(CONFIG_ARCH_OMAP1)
 #error "iommu for this processor not implemented yet"
 #else
@@ -150,10 +162,17 @@ extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
 extern void flush_iotlb_all(struct iommu *obj);
 extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e);
+extern void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd,
+                                   u32 **ppte);
 extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
+extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end);
 extern struct iommu *iommu_get(const char *name);
 extern void iommu_put(struct iommu *obj);
+extern int iommu_set_isr(const char *name,
+                         int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs,
+                                    void *priv),
+                         void *isr_priv);
 extern void iommu_save_ctx(struct iommu *obj);
 extern void iommu_restore_ctx(struct iommu *obj);
diff --git a/arch/arm/plat-omap/include/plat/iovmm.h b/arch/arm/plat-omap/include/plat/iovmm.h
index bdc7ce5d7a4a..e992b9655fbc 100644
--- a/arch/arm/plat-omap/include/plat/iovmm.h
+++ b/arch/arm/plat-omap/include/plat/iovmm.h
@@ -29,9 +29,6 @@ struct iovm_struct {
 * lower 16 bit is used for h/w and upper 16 bit is for s/w.
 */
 #define IOVMF_SW_SHIFT          16
-#define IOVMF_HW_SIZE           (1 << IOVMF_SW_SHIFT)
-#define IOVMF_HW_MASK           (IOVMF_HW_SIZE - 1)
-#define IOVMF_SW_MASK           (~IOVMF_HW_MASK)UL
 /*
 * iovma: h/w flags derived from cam and ram attribute
@@ -71,8 +68,6 @@ struct iovm_struct {
 #define IOVMF_LINEAR_MASK       (3 << (2 + IOVMF_SW_SHIFT))
 #define IOVMF_DA_FIXED          (1 << (4 + IOVMF_SW_SHIFT))
-#define IOVMF_DA_ANON           (2 << (4 + IOVMF_SW_SHIFT))
-#define IOVMF_DA_MASK           (3 << (4 + IOVMF_SW_SHIFT))
 extern struct iovm_struct *find_iovm_area(struct iommu *obj, u32 da);
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index c01d9f08a198..5a25098ea7ea 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -77,7 +77,7 @@
 /*
 * OMAP-1610 specific IRQ numbers for interrupt handler 1
 */
-#define INT_1610_IH2_IRQ        0
+#define INT_1610_IH2_IRQ        INT_1510_IH2_IRQ
 #define INT_1610_IH2_FIQ        2
 #define INT_1610_McBSP2_TX      4
 #define INT_1610_McBSP2_RX      5
@@ -315,9 +315,12 @@
 #define INT_34XX_SSM_ABORT_IRQ  6
 #define INT_34XX_SYS_NIRQ       7
 #define INT_34XX_D2D_FW_IRQ     8
+#define INT_34XX_L3_DBG_IRQ     9
+#define INT_34XX_L3_APP_IRQ     10
 #define INT_34XX_PRCM_MPU_IRQ   11
 #define INT_34XX_MCBSP1_IRQ     16
 #define INT_34XX_MCBSP2_IRQ     17
+#define INT_34XX_GPMC_IRQ       20
 #define INT_34XX_MCBSP3_IRQ     22
 #define INT_34XX_MCBSP4_IRQ     23
 #define INT_34XX_CAM_IRQ        24
@@ -345,6 +348,8 @@
 #define INT_34XX_MMC3_IRQ       94
 #define INT_34XX_GPT12_IRQ      95
+#define INT_36XX_UART4_IRQ      80
 #define INT_35XX_HECC0_IRQ              24
 #define INT_35XX_HECC1_IRQ              28
 #define INT_35XX_EMAC_C0_RXTHRESH_IRQ   67
@@ -409,7 +414,13 @@
 #define TWL_IRQ_END             TWL6030_IRQ_END
 #endif
-#define NR_IRQS                 TWL_IRQ_END
+/* GPMC related */
+#define OMAP_GPMC_IRQ_BASE      (TWL_IRQ_END)
+#define OMAP_GPMC_NR_IRQS       8
+#define OMAP_GPMC_IRQ_END       (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
+#define NR_IRQS                 OMAP_GPMC_IRQ_END
 #define OMAP_IRQ_BIT(irq)       (1 << ((irq) % 32))
diff --git a/arch/arm/plat-omap/include/plat/keypad.h b/arch/arm/plat-omap/include/plat/keypad.h
index 3ae52ccc793c..793ce9d53294 100644
--- a/arch/arm/plat-omap/include/plat/keypad.h
+++ b/arch/arm/plat-omap/include/plat/keypad.h
@@ -10,16 +10,18 @@
 #ifndef ASMARM_ARCH_KEYPAD_H
 #define ASMARM_ARCH_KEYPAD_H
-#warning: Please update the board to use matrix_keypad.h instead
+#ifndef CONFIG_ARCH_OMAP1
+#warning Please update the board to use matrix-keypad driver
+#endif
+#include <linux/input/matrix_keypad.h>
 struct omap_kp_platform_data {
        int rows;
        int cols;
-        int *keymap;
+        const struct matrix_keymap_data *keymap_data;
-        unsigned int keymapsize;
+        bool rep;
-        unsigned int rep:1;
        unsigned long delay;
-        unsigned int dbounce:1;
+        bool dbounce;
        /* specific to OMAP242x*/
        unsigned int *row_gpios;
        unsigned int *col_gpios;
@@ -28,18 +30,21 @@ struct omap_kp_platform_data {
 /* Group (0..3) -- when multiple keys are pressed, only the
 * keys pressed in the same group are considered as pressed. This is
 * in order to workaround certain crappy HW designs that produce ghost
- * keypresses. */
+ * keypresses. Two free bits, not used by neither row/col nor keynum,
-#define GROUP_0         (0 << 16)
+ * must be available for use as group bits. The below GROUP_SHIFT
-#define GROUP_1         (1 << 16)
+ * macro definition is based on some prior knowledge of the
-#define GROUP_2         (2 << 16)
+ * matrix_keypad defined KEY() macro internals.
-#define GROUP_3         (3 << 16)
+ */
+#define GROUP_SHIFT     14
+#define GROUP_0         (0 << GROUP_SHIFT)
+#define GROUP_1         (1 << GROUP_SHIFT)
+#define GROUP_2         (2 << GROUP_SHIFT)
+#define GROUP_3         (3 << GROUP_SHIFT)
 #define GROUP_MASK      GROUP_3
+#if KEY_MAX & GROUP_MASK
+#error Group bits in conflict with keynum bits
+#endif
-#define KEY_PERSISTENT          0x00800000
-#define KEYNUM_MASK             0x00EFFFFF
-#define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val))
-#define PERSISTENT_KEY(col, row) (((col) << 28) | ((row) << 24) | \
-                                                KEY_PERSISTENT)
 #endif
diff --git a/arch/arm/plat-omap/include/plat/l3_2xxx.h b/arch/arm/plat-omap/include/plat/l3_2xxx.h
new file mode 100644
index 000000000000..b8b5641379b0
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/l3_2xxx.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Sumit Semwal
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
+/* L3 CONNIDs */
+/* Display Sub system (DSS) */
+#define OMAP2_L3_CORE_FW_CONNID_DSS                     8
+#endif
diff --git a/arch/arm/plat-omap/include/plat/l3_3xxx.h b/arch/arm/plat-omap/include/plat/l3_3xxx.h
new file mode 100644
index 000000000000..cde1938c5f82
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/l3_3xxx.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/plat-omap/include/plat/l3_3xxx.h - L3 firewall definitions
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Sumit Semwal
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H
+/* L3 Initiator IDs */
+/* Display Sub system (DSS) */
+#define OMAP3_L3_CORE_FW_INIT_ID_DSS                    29
+#endif
diff --git a/arch/arm/plat-omap/include/plat/l4_2xxx.h b/arch/arm/plat-omap/include/plat/l4_2xxx.h
new file mode 100644
index 000000000000..3f39cf8a35c6
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/l4_2xxx.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/plat-omap/include/plat/l4_2xxx.h - L4 firewall definitions
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Sumit Semwal
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
+/* L4 CORE */
+/* Display Sub system (DSS) */
+#define OMAP2420_L4_CORE_FW_DSS_CORE_REGION                     28
+#define OMAP2420_L4_CORE_FW_DSS_DISPC_REGION                    29
+#define OMAP2420_L4_CORE_FW_DSS_RFBI_REGION                     30
+#define OMAP2420_L4_CORE_FW_DSS_VENC_REGION                     31
+#define OMAP2420_L4_CORE_FW_DSS_TA_REGION                       32
+#endif
diff --git a/arch/arm/plat-omap/include/plat/l4_3xxx.h b/arch/arm/plat-omap/include/plat/l4_3xxx.h
new file mode 100644
index 000000000000..881a858b1ffc
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/l4_3xxx.h
@@ -0,0 +1,34 @@
+/*
+ * arch/arm/plat-omap/include/mach/l4_3xxx.h - L4 firewall definitions
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H
+/* L4 CORE */
+#define OMAP3_L4_CORE_FW_I2C1_REGION                            21
+#define OMAP3_L4_CORE_FW_I2C1_TA_REGION                         22
+#define OMAP3_L4_CORE_FW_I2C2_REGION                            23
+#define OMAP3_L4_CORE_FW_I2C2_TA_REGION                         24
+#define OMAP3_L4_CORE_FW_I2C3_REGION                            73
+#define OMAP3_L4_CORE_FW_I2C3_TA_REGION                         74
+/* Display Sub system (DSS) */
+#define OMAP3_L4_CORE_FW_DSS_PROT_GROUP                         2
+#define OMAP3_L4_CORE_FW_DSS_DSI_REGION                         104
+#define OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION                     3
+#define OMAP3_L4_CORE_FW_DSS_CORE_REGION                        4
+#define OMAP3_L4_CORE_FW_DSS_DISPC_REGION                       4
+#define OMAP3_L4_CORE_FW_DSS_RFBI_REGION                        5
+#define OMAP3_L4_CORE_FW_DSS_VENC_REGION                        6
+#define OMAP3_L4_CORE_FW_DSS_TA_REGION                          7
+#endif
diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h
index 997656552109..cc3921e9059c 100644
--- a/arch/arm/plat-omap/include/plat/mailbox.h
+++ b/arch/arm/plat-omap/include/plat/mailbox.h
@@ -46,8 +46,8 @@ struct omap_mbox_queue {
        struct kfifo            fifo;
        struct work_struct      work;
        struct tasklet_struct   tasklet;
-        int     (*callback)(void *);
        struct omap_mbox        *mbox;
+        bool full;
 };
 struct omap_mbox {
@@ -57,13 +57,15 @@ struct omap_mbox {
        struct omap_mbox_ops    *ops;
        struct device           *dev;
        void                    *priv;
+        int                     use_count;
+        struct blocking_notifier_head   notifier;
 };
 int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
 void omap_mbox_init_seq(struct omap_mbox *);
-struct omap_mbox *omap_mbox_get(const char *);
+struct omap_mbox *omap_mbox_get(const char *, struct notifier_block *nb);
-void omap_mbox_put(struct omap_mbox *);
+void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb);
 int omap_mbox_register(struct device *parent, struct omap_mbox **);
 int omap_mbox_unregister(void);
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index b4ff6a11a8f2..f8f690ab2997 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -30,6 +30,17 @@
 #include <mach/hardware.h>
 #include <plat/clock.h>
+/* macro for building platform_device for McBSP ports */
+#define OMAP_MCBSP_PLATFORM_DEVICE(port_nr)             \
+static struct platform_device omap_mcbsp##port_nr = {   \
+        .name   = "omap-mcbsp-dai",                     \
+        .id     = OMAP_MCBSP##port_nr,                  \
+}
+#define MCBSP_CONFIG_TYPE2      0x2
+#define MCBSP_CONFIG_TYPE3      0x3
+#define MCBSP_CONFIG_TYPE4      0x4
 #define OMAP7XX_MCBSP1_BASE     0xfffb1000
 #define OMAP7XX_MCBSP2_BASE     0xfffb1800
@@ -41,32 +52,14 @@
 #define OMAP1610_MCBSP2_BASE    0xfffb1000
 #define OMAP1610_MCBSP3_BASE    0xe1017000
-#define OMAP24XX_MCBSP1_BASE    0x48074000
+#ifdef CONFIG_ARCH_OMAP1
-#define OMAP24XX_MCBSP2_BASE    0x48076000
-#define OMAP2430_MCBSP3_BASE    0x4808c000
-#define OMAP2430_MCBSP4_BASE    0x4808e000
-#define OMAP2430_MCBSP5_BASE    0x48096000
-#define OMAP34XX_MCBSP1_BASE    0x48074000
-#define OMAP34XX_MCBSP2_BASE    0x49022000
-#define OMAP34XX_MCBSP2_ST_BASE 0x49028000
-#define OMAP34XX_MCBSP3_BASE    0x49024000
-#define OMAP34XX_MCBSP3_ST_BASE 0x4902A000
-#define OMAP34XX_MCBSP3_BASE    0x49024000
-#define OMAP34XX_MCBSP4_BASE    0x49026000
-#define OMAP34XX_MCBSP5_BASE    0x48096000
-#define OMAP44XX_MCBSP1_BASE    0x49022000
-#define OMAP44XX_MCBSP2_BASE    0x49024000
-#define OMAP44XX_MCBSP3_BASE    0x49026000
-#define OMAP44XX_MCBSP4_BASE    0x48096000
-#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 #define OMAP_MCBSP_REG_DRR2     0x00
 #define OMAP_MCBSP_REG_DRR1     0x02
 #define OMAP_MCBSP_REG_DXR2     0x04
 #define OMAP_MCBSP_REG_DXR1     0x06
+#define OMAP_MCBSP_REG_DRR      0x02
+#define OMAP_MCBSP_REG_DXR      0x06
 #define OMAP_MCBSP_REG_SPCR2    0x08
 #define OMAP_MCBSP_REG_SPCR1    0x0a
 #define OMAP_MCBSP_REG_RCR2     0x0c
@@ -99,13 +92,6 @@
 #define OMAP_MCBSP_REG_XCCR     0x00
 #define OMAP_MCBSP_REG_RCCR     0x00
-#define AUDIO_MCBSP_DATAWRITE   (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
-#define AUDIO_MCBSP_DATAREAD    (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
-#define AUDIO_MCBSP             OMAP_MCBSP1
-#define AUDIO_DMA_TX            OMAP_DMA_MCBSP1_TX
-#define AUDIO_DMA_RX            OMAP_DMA_MCBSP1_RX
 #else
 #define OMAP_MCBSP_REG_DRR2     0x00
@@ -161,13 +147,6 @@
 #define OMAP_ST_REG_SFIRCR      0x28
 #define OMAP_ST_REG_SSELCR      0x2C
-#define AUDIO_MCBSP_DATAWRITE   (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
-#define AUDIO_MCBSP_DATAREAD    (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
-#define AUDIO_MCBSP             OMAP_MCBSP2
-#define AUDIO_DMA_TX            OMAP24XX_DMA_MCBSP2_TX
-#define AUDIO_DMA_RX            OMAP24XX_DMA_MCBSP2_RX
 #endif
 /************************** McBSP SPCR1 bit definitions ***********************/
@@ -312,6 +291,18 @@
 #define RFSREN                  0x0002
 #define RSYNCERREN              0x0001
+/* CLKR signal muxing options */
+#define CLKR_SRC_CLKR           0
+#define CLKR_SRC_CLKX           1
+/* FSR signal muxing options */
+#define FSR_SRC_FSR             0
+#define FSR_SRC_FSX             1
+/* McBSP functional clock sources */
+#define MCBSP_CLKS_PRCM_SRC     0
+#define MCBSP_CLKS_PAD_SRC      1
 /* we don't do multichannel for now */
 struct omap_mcbsp_reg_cfg {
        u16 spcr2;
@@ -398,6 +389,7 @@ struct omap_mcbsp_spi_cfg {
 struct omap_mcbsp_ops {
        void (*request)(unsigned int);
        void (*free)(unsigned int);
+        int (*set_clks_src)(u8, u8);
 };
 struct omap_mcbsp_platform_data {
@@ -408,8 +400,9 @@ struct omap_mcbsp_platform_data {
 #ifdef CONFIG_ARCH_OMAP3
        /* Sidetone block for McBSP 2 and 3 */
        unsigned long phys_base_st;
-        u16 buffer_size;
 #endif
+        u16 buffer_size;
+        unsigned int mcbsp_config_type;
 };
 struct omap_mcbsp_st_data {
@@ -425,6 +418,7 @@ struct omap_mcbsp_st_data {
 struct omap_mcbsp {
        struct device *dev;
        unsigned long phys_base;
+        unsigned long phys_dma_base;
        void __iomem *io_base;
        u8 id;
        u8 free;
@@ -451,7 +445,6 @@ struct omap_mcbsp {
        /* Protect the field .free, while checking if the mcbsp is in use */
        spinlock_t lock;
        struct omap_mcbsp_platform_data *pdata;
-        struct clk *iclk;
        struct clk *fclk;
 #ifdef CONFIG_ARCH_OMAP3
        struct omap_mcbsp_st_data *st_data;
@@ -460,13 +453,26 @@ struct omap_mcbsp {
        u16 max_rx_thres;
 #endif
        void *reg_cache;
+        unsigned int mcbsp_config_type;
+};
+/**
+ * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod
+ * @sidetone: name of the sidetone device
+ */
+struct omap_mcbsp_dev_attr {
+        const char *sidetone;
 };
 extern struct omap_mcbsp **mcbsp_ptr;
 extern int omap_mcbsp_count, omap_mcbsp_cache_size;
+#define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
+#define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
 int omap_mcbsp_init(void);
-void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
+void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
-                                        int size);
+                        struct omap_mcbsp_platform_data *config, int size);
 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
 #ifdef CONFIG_ARCH_OMAP3
 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
@@ -502,6 +508,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
+/* McBSP functional clock source changing function */
+extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
 /* SPI specific API */
 void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
@@ -510,6 +518,13 @@ int omap_mcbsp_pollread(unsigned int id, u16 * buf);
 int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
+/* McBSP signal muxing API */
+void omap2_mcbsp1_mux_clkr_src(u8 mux);
+void omap2_mcbsp1_mux_fsr_src(u8 mux);
+int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream);
+int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream);
 #ifdef CONFIG_ARCH_OMAP3
 /* Sidetone specific API */
 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
index 1254e4945b6f..3d51b18131cc 100644
--- a/arch/arm/plat-omap/include/plat/mcspi.h
+++ b/arch/arm/plat-omap/include/plat/mcspi.h
@@ -1,8 +1,19 @@
 #ifndef _OMAP2_MCSPI_H
 #define _OMAP2_MCSPI_H
+#define OMAP2_MCSPI_REV 0
+#define OMAP3_MCSPI_REV 1
+#define OMAP4_MCSPI_REV 2
+#define OMAP4_MCSPI_REG_OFFSET 0x100
 struct omap2_mcspi_platform_config {
        unsigned short  num_cs;
+        unsigned int regs_offset;
+};
+struct omap2_mcspi_dev_attr {
+        unsigned short num_chipselect;
 };
 struct omap2_mcspi_device_config {
diff --git a/arch/arm/plat-omap/include/plat/memory.h b/arch/arm/plat-omap/include/plat/memory.h
index d5306bee44b2..e6720aa2d553 100644
--- a/arch/arm/plat-omap/include/plat/memory.h
+++ b/arch/arm/plat-omap/include/plat/memory.h
@@ -37,9 +37,9 @@
 * Physical DRAM offset.
 */
 #if defined(CONFIG_ARCH_OMAP1)
-#define PHYS_OFFSET             UL(0x10000000)
+#define PLAT_PHYS_OFFSET                UL(0x10000000)
 #else
-#define PHYS_OFFSET             UL(0x80000000)
+#define PLAT_PHYS_OFFSET                UL(0x80000000)
 #endif
 /*
@@ -61,17 +61,17 @@
 #define lbus_to_virt(x)         ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
 #define is_lbus_device(dev)     (cpu_is_omap15xx() && dev && (strncmp(dev_name(dev), "ohci", 4) == 0))
-#define __arch_page_to_dma(dev, page)   \
+#define __arch_pfn_to_dma(dev, pfn)     \
-        ({ dma_addr_t __dma = page_to_phys(page); \
+        ({ dma_addr_t __dma = __pfn_to_phys(pfn); \
           if (is_lbus_device(dev)) \
                __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \
           __dma; })
-#define __arch_dma_to_page(dev, addr)   \
+#define __arch_dma_to_pfn(dev, addr)    \
        ({ dma_addr_t __dma = addr;                             \
           if (is_lbus_device(dev))                             \
                __dma += PHYS_OFFSET - OMAP1510_LB_OFFSET;      \
-           phys_to_page(__dma);                                 \
+           __phys_to_pfn(__dma);                                \
        })
 #define __arch_dma_to_virt(dev, addr)   ({ (void *) (is_lbus_device(dev) ? \
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index 9b89ec601ee2..c7b874186c27 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -24,25 +24,19 @@
 #define OMAP1_MMC2_BASE         0xfffb7c00      /* omap16xx only */
 #define OMAP24XX_NR_MMC         2
-#define OMAP34XX_NR_MMC         3
-#define OMAP44XX_NR_MMC         5
 #define OMAP2420_MMC_SIZE       OMAP1_MMC_SIZE
-#define OMAP3_HSMMC_SIZE        0x200
-#define OMAP4_HSMMC_SIZE        0x1000
 #define OMAP2_MMC1_BASE         0x4809c000
-#define OMAP2_MMC2_BASE         0x480b4000
-#define OMAP3_MMC3_BASE         0x480ad000
-#define OMAP4_MMC4_BASE         0x480d1000
-#define OMAP4_MMC5_BASE         0x480d5000
 #define OMAP4_MMC_REG_OFFSET    0x100
-#define HSMMC5                  (1 << 4)
-#define HSMMC4                  (1 << 3)
-#define HSMMC3                  (1 << 2)
-#define HSMMC2                  (1 << 1)
-#define HSMMC1                  (1 << 0)
 #define OMAP_MMC_MAX_SLOTS      2
+#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT   BIT(1)
+struct omap_mmc_dev_attr {
+        u8 flags;
+};
 struct omap_mmc_platform_data {
        /* back-link to device */
        struct device *dev;
@@ -71,12 +65,20 @@ struct omap_mmc_platform_data {
        u64 dma_mask;
+        /* Integrating attributes from the omap_hwmod layer */
+        u8 controller_flags;
+        /* Register offset deviation */
+        u16 reg_offset;
        struct omap_mmc_slot_data {
-                /* 4 wire signaling is optional, and is used for SD/SDIO/HSMMC;
+                /*
-                 * 8 wire signaling is also optional, and is used with HSMMC
+                 * 4/8 wires and any additional host capabilities
+                 * need to OR'd all capabilities (ref. linux/mmc/host.h)
                 */
-                u8 wires;
+                u8  wires;      /* Used for the MMC driver on omap1 and 2420 */
+                u32 caps;       /* Used for the MMC driver on 2430 and later */
                /*
                 * nomux means "standard" muxing is wrong on this board, and
@@ -99,11 +101,15 @@ struct omap_mmc_platform_data {
                /* If using power_saving and the MMC power is not to go off */
                unsigned no_off:1;
+                /* eMMC does not handle power off when not in sleep state */
+                unsigned no_regulator_off_init:1;
                /* Regulator off remapped to sleep */
                unsigned vcc_aux_disable_is_sleep:1;
                /* we can put the features above into this variable */
 #define HSMMC_HAS_PBIAS         (1 << 0)
+#define HSMMC_HAS_UPDATED_RESET (1 << 1)
                unsigned features;
                int switch_pin;                 /* gpio (card detect) */
@@ -153,8 +159,7 @@ extern void omap_mmc_notify_cover_event(struct device *dev, int slot,
        defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
                                int nr_controllers);
-void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
+void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data);
-                                int nr_controllers);
 int omap_mmc_add(const char *name, int id, unsigned long base,
                                unsigned long size, unsigned int irq,
                                struct omap_mmc_platform_data *data);
@@ -163,8 +168,7 @@ static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
                                int nr_controllers)
 {
 }
-static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
+static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
-                                int nr_controllers)
 {
 }
 static inline int omap_mmc_add(const char *name, int id, unsigned long base,
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
index ffd909fa5287..999ffba2690c 100644
--- a/arch/arm/plat-omap/include/plat/multi.h
+++ b/arch/arm/plat-omap/include/plat/multi.h
@@ -66,7 +66,7 @@
 #  error "OMAP1 and OMAP2PLUS can't be selected at the same time"
 # endif
 #endif
-#ifdef CONFIG_ARCH_OMAP2420
+#ifdef CONFIG_SOC_OMAP2420
 # ifdef OMAP_NAME
 #  undef  MULTI_OMAP2
 #  define MULTI_OMAP2
@@ -74,7 +74,7 @@
 #  define OMAP_NAME omap2420
 # endif
 #endif
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
 # ifdef OMAP_NAME
 #  undef  MULTI_OMAP2
 #  define MULTI_OMAP2
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index 6562cd082bb1..d86d1ecf0068 100644
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -8,8 +8,16 @@
 * published by the Free Software Foundation.
 */
+#include <plat/gpmc.h>
 #include <linux/mtd/partitions.h>
+enum nand_io {
+        NAND_OMAP_PREFETCH_POLLED = 0,  /* prefetch polled mode, default */
+        NAND_OMAP_POLLED,               /* polled mode, without prefetch */
+        NAND_OMAP_PREFETCH_DMA,         /* prefetch enabled sDMA mode */
+        NAND_OMAP_PREFETCH_IRQ          /* prefetch enabled irq mode */
+};
 struct omap_nand_platform_data {
        unsigned int            options;
        int                     cs;
@@ -20,8 +28,11 @@ struct omap_nand_platform_data {
        int                     (*nand_setup)(void);
        int                     (*dev_ready)(struct omap_nand_platform_data *);
        int                     dma_channel;
+        int                     gpmc_irq;
+        enum nand_io            xfer_type;
        unsigned long           phys_base;
        int                     devsize;
+        enum omap_ecc           ecc_opt;
 };
 /* minimum size for IO mapping */
diff --git a/arch/arm/plat-omap/include/plat/nokia-dsi-panel.h b/arch/arm/plat-omap/include/plat/nokia-dsi-panel.h
deleted file mode 100644
index 01ab6572ccbb..000000000000
--- a/arch/arm/plat-omap/include/plat/nokia-dsi-panel.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef __ARCH_ARM_PLAT_OMAP_NOKIA_DSI_PANEL_H
-#define __ARCH_ARM_PLAT_OMAP_NOKIA_DSI_PANEL_H
-#include "display.h"
-/**
- * struct nokia_dsi_panel_data - Nokia DSI panel driver configuration
- * @name: panel name
- * @use_ext_te: use external TE
- * @ext_te_gpio: external TE GPIO
- * @use_esd_check: perform ESD checks
- * @max_backlight_level: maximum backlight level
- * @set_backlight: pointer to backlight set function
- * @get_backlight: pointer to backlight get function
- */
-struct nokia_dsi_panel_data {
-        const char *name;
-        int reset_gpio;
-        bool use_ext_te;
-        int ext_te_gpio;
-        bool use_esd_check;
-        int max_backlight_level;
-        int (*set_backlight)(struct omap_dss_device *dssdev, int level);
-        int (*get_backlight)(struct omap_dss_device *dssdev);
-};
-#endif /* __ARCH_ARM_PLAT_OMAP_NOKIA_DSI_PANEL_H */
diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h
index 728fbb9dd549..c0a752053039 100644
--- a/arch/arm/plat-omap/include/plat/omap-pm.h
+++ b/arch/arm/plat-omap/include/plat/omap-pm.h
@@ -17,26 +17,7 @@
 #include <linux/device.h>
 #include <linux/cpufreq.h>
 #include <linux/clk.h>
+#include <linux/opp.h>
-#include "powerdomain.h"
-/**
- * struct omap_opp - clock frequency-to-OPP ID table for DSP, MPU
- * @rate: target clock rate
- * @opp_id: OPP ID
- * @min_vdd: minimum VDD1 voltage (in millivolts) for this OPP
- *
- * Operating performance point data.  Can vary by OMAP chip and board.
- */
-struct omap_opp {
-        unsigned long rate;
-        u8 opp_id;
-        u16 min_vdd;
-};
-extern struct omap_opp *mpu_opps;
-extern struct omap_opp *dsp_opps;
-extern struct omap_opp *l3_opps;
 /*
 * agent_id values for use with omap_pm_set_min_bus_tput():
@@ -59,9 +40,11 @@ extern struct omap_opp *l3_opps;
 * framework starts.  The "_if_" is to avoid name collisions with the
 * PM idle-loop code.
 */
-int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
+#ifdef CONFIG_OMAP_PM_NONE
-                                 struct omap_opp *dsp_opp_table,
+#define omap_pm_if_early_init() 0
-                                 struct omap_opp *l3_opp_table);
+#else
+int __init omap_pm_if_early_init(void);
+#endif
 /**
 * omap_pm_if_init - OMAP PM init code called after clock fw init
@@ -69,7 +52,11 @@ int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
 * The main initialization code.  OPP tables are passed in here.  The
 * "_if_" is to avoid name collisions with the PM idle-loop code.
 */
+#ifdef CONFIG_OMAP_PM_NONE
+#define omap_pm_if_init() 0
+#else
 int __init omap_pm_if_init(void);
+#endif
 /**
 * omap_pm_if_exit - OMAP PM exit code
@@ -363,9 +350,11 @@ unsigned long omap_pm_cpu_get_freq(void);
 * driver must restore device context.   If the number of context losses
 * exceeds the maximum positive integer, the function will wrap to 0 and
 * continue counting.  Returns the number of context losses for this device,
- * or -EINVAL upon error.
+ * or zero upon error.
 */
-int omap_pm_get_dev_context_loss_count(struct device *dev);
+u32 omap_pm_get_dev_context_loss_count(struct device *dev);
+void omap_pm_enable_off_mode(void);
+void omap_pm_disable_off_mode(void);
 #endif
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
new file mode 100644
index 000000000000..2682043f5a5b
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -0,0 +1,116 @@
+/*
+ * Driver for OMAP-UART controller.
+ * Based on drivers/serial/8250.c
+ *
+ * Copyright (C) 2010 Texas Instruments.
+ *
+ * Authors:
+ *      Govindraj R     <govindraj.raja@ti.com>
+ *      Thara Gopinath  <thara@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __OMAP_SERIAL_H__
+#define __OMAP_SERIAL_H__
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <plat/mux.h>
+#define DRIVER_NAME     "omap_uart"
+/*
+ * Use tty device name as ttyO, [O -> OMAP]
+ * in bootargs we specify as console=ttyO0 if uart1
+ * is used as console uart.
+ */
+#define OMAP_SERIAL_NAME        "ttyO"
+#define OMAP_MODE13X_SPEED      230400
+/* WER = 0x7F
+ * Enable module level wakeup in WER reg
+ */
+#define OMAP_UART_WER_MOD_WKUP  0X7F
+/* Enable XON/XOFF flow control on output */
+#define OMAP_UART_SW_TX         0x04
+/* Enable XON/XOFF flow control on input */
+#define OMAP_UART_SW_RX         0x04
+#define OMAP_UART_SYSC_RESET    0X07
+#define OMAP_UART_TCR_TRIG      0X0F
+#define OMAP_UART_SW_CLR        0XF0
+#define OMAP_UART_FIFO_CLR      0X06
+#define OMAP_UART_DMA_CH_FREE   -1
+#define RX_TIMEOUT              (3 * HZ)
+#define OMAP_MAX_HSUART_PORTS   4
+#define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
+struct omap_uart_port_info {
+        bool                    dma_enabled;    /* To specify DMA Mode */
+        unsigned int            uartclk;        /* UART clock rate */
+        void __iomem            *membase;       /* ioremap cookie or NULL */
+        resource_size_t         mapbase;        /* resource base */
+        unsigned long           irqflags;       /* request_irq flags */
+        upf_t                   flags;          /* UPF_* flags */
+};
+struct uart_omap_dma {
+        u8                      uart_dma_tx;
+        u8                      uart_dma_rx;
+        int                     rx_dma_channel;
+        int                     tx_dma_channel;
+        dma_addr_t              rx_buf_dma_phys;
+        dma_addr_t              tx_buf_dma_phys;
+        unsigned int            uart_base;
+        /*
+         * Buffer for rx dma.It is not required for tx because the buffer
+         * comes from port structure.
+         */
+        unsigned char           *rx_buf;
+        unsigned int            prev_rx_dma_pos;
+        int                     tx_buf_size;
+        int                     tx_dma_used;
+        int                     rx_dma_used;
+        spinlock_t              tx_lock;
+        spinlock_t              rx_lock;
+        /* timer to poll activity on rx dma */
+        struct timer_list       rx_timer;
+        int                     rx_buf_size;
+        int                     rx_timeout;
+};
+struct uart_omap_port {
+        struct uart_port        port;
+        struct uart_omap_dma    uart_dma;
+        struct platform_device  *pdev;
+        unsigned char           ier;
+        unsigned char           lcr;
+        unsigned char           mcr;
+        unsigned char           fcr;
+        unsigned char           efr;
+        int                     use_dma;
+        /*
+         * Some bits in registers are cleared on a read, so they must
+         * be saved whenever the register is read but the bits will not
+         * be immediately processed.
+         */
+        unsigned int            lsr_break_flag;
+        unsigned char           msr_saved_flags;
+        char                    name[20];
+        unsigned long           port_activity;
+};
+#endif /* __OMAP_SERIAL_H__ */
diff --git a/arch/arm/plat-omap/include/plat/omap24xx.h b/arch/arm/plat-omap/include/plat/omap24xx.h
index 7055672a8c68..92df9e27cc5c 100644
--- a/arch/arm/plat-omap/include/plat/omap24xx.h
+++ b/arch/arm/plat-omap/include/plat/omap24xx.h
@@ -40,7 +40,7 @@
 #define OMAP24XX_IC_BASE        (L4_24XX_BASE + 0xfe000)
 #define OMAP24XX_IVA_INTC_BASE  0x40000000
-#define OMAP2420_CTRL_BASE      L4_24XX_BASE
+#define OMAP242X_CTRL_BASE      L4_24XX_BASE
 #define OMAP2420_32KSYNCT_BASE  (L4_24XX_BASE + 0x4000)
 #define OMAP2420_PRCM_BASE      (L4_24XX_BASE + 0x8000)
 #define OMAP2420_CM_BASE        (L4_24XX_BASE + 0x8000)
diff --git a/arch/arm/plat-omap/include/plat/omap34xx.h b/arch/arm/plat-omap/include/plat/omap34xx.h
index 98fc8b4a4cc4..b9e85886b9d6 100644
--- a/arch/arm/plat-omap/include/plat/omap34xx.h
+++ b/arch/arm/plat-omap/include/plat/omap34xx.h
@@ -56,8 +56,12 @@
 #define OMAP3430_ISP_RESZ_BASE          (OMAP3430_ISP_BASE + 0x1000)
 #define OMAP3430_ISP_SBL_BASE           (OMAP3430_ISP_BASE + 0x1200)
 #define OMAP3430_ISP_MMU_BASE           (OMAP3430_ISP_BASE + 0x1400)
-#define OMAP3430_ISP_CSI2A_BASE         (OMAP3430_ISP_BASE + 0x1800)
+#define OMAP3430_ISP_CSI2A_REGS1_BASE   (OMAP3430_ISP_BASE + 0x1800)
-#define OMAP3430_ISP_CSI2PHY_BASE       (OMAP3430_ISP_BASE + 0x1970)
+#define OMAP3430_ISP_CSIPHY2_BASE       (OMAP3430_ISP_BASE + 0x1970)
+#define OMAP3630_ISP_CSI2A_REGS2_BASE   (OMAP3430_ISP_BASE + 0x19C0)
+#define OMAP3630_ISP_CSI2C_REGS1_BASE   (OMAP3430_ISP_BASE + 0x1C00)
+#define OMAP3630_ISP_CSIPHY1_BASE       (OMAP3430_ISP_BASE + 0x1D70)
+#define OMAP3630_ISP_CSI2C_REGS2_BASE   (OMAP3430_ISP_BASE + 0x1DC0)
 #define OMAP3430_ISP_END                (OMAP3430_ISP_BASE         + 0x06F)
 #define OMAP3430_ISP_CBUFF_END          (OMAP3430_ISP_CBUFF_BASE   + 0x077)
@@ -69,8 +73,12 @@
 #define OMAP3430_ISP_RESZ_END           (OMAP3430_ISP_RESZ_BASE    + 0x0AB)
 #define OMAP3430_ISP_SBL_END            (OMAP3430_ISP_SBL_BASE     + 0x0FB)
 #define OMAP3430_ISP_MMU_END            (OMAP3430_ISP_MMU_BASE     + 0x06F)
-#define OMAP3430_ISP_CSI2A_END          (OMAP3430_ISP_CSI2A_BASE   + 0x16F)
+#define OMAP3430_ISP_CSI2A_REGS1_END    (OMAP3430_ISP_CSI2A_REGS1_BASE + 0x16F)
-#define OMAP3430_ISP_CSI2PHY_END        (OMAP3430_ISP_CSI2PHY_BASE + 0x007)
+#define OMAP3430_ISP_CSIPHY2_END        (OMAP3430_ISP_CSIPHY2_BASE + 0x00B)
+#define OMAP3630_ISP_CSI2A_REGS2_END    (OMAP3630_ISP_CSI2A_REGS2_BASE + 0x3F)
+#define OMAP3630_ISP_CSI2C_REGS1_END    (OMAP3630_ISP_CSI2C_REGS1_BASE + 0x16F)
+#define OMAP3630_ISP_CSIPHY1_END        (OMAP3630_ISP_CSIPHY1_BASE + 0x00B)
+#define OMAP3630_ISP_CSI2C_REGS2_END    (OMAP3630_ISP_CSI2C_REGS2_BASE + 0x3F)
 #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
 #define OMAP34XX_USBTLL_BASE    (L4_34XX_BASE + 0x62000)
diff --git a/arch/arm/plat-omap/include/plat/omap4-keypad.h b/arch/arm/plat-omap/include/plat/omap4-keypad.h
new file mode 100644
index 000000000000..2b1d9bc1eebb
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap4-keypad.h
@@ -0,0 +1,14 @@
+#ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H
+#define ARCH_ARM_PLAT_OMAP4_KEYPAD_H
+#include <linux/input/matrix_keypad.h>
+struct omap4_keypad_platform_data {
+        const struct matrix_keymap_data *keymap_data;
+        u8 rows;
+        u8 cols;
+};
+extern int omap4_keyboard_init(struct omap4_keypad_platform_data *);
+#endif
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index 8b3f12ff5cbc..ea2b8a6306e7 100644
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -52,5 +52,10 @@
 #define OMAP4_MMU1_BASE                 0x55082000
 #define OMAP4_MMU2_BASE                 0x4A066000
+#define OMAP44XX_USBTLL_BASE            (L4_44XX_BASE + 0x62000)
+#define OMAP44XX_UHH_CONFIG_BASE        (L4_44XX_BASE + 0x64000)
+#define OMAP44XX_HSUSB_OHCI_BASE        (L4_44XX_BASE + 0x64800)
+#define OMAP44XX_HSUSB_EHCI_BASE        (L4_44XX_BASE + 0x64C00)
 #endif /* __ASM_ARCH_OMAP44XX_H */
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 25cd9ac3b095..e4c349ff9fd8 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -36,6 +36,8 @@
 #include <plat/omap_hwmod.h>
+extern struct device omap_device_parent;
 /* omap_device._state values */
 #define OMAP_DEVICE_STATE_UNKNOWN       0
 #define OMAP_DEVICE_STATE_ENABLED       1
@@ -62,7 +64,6 @@
 *
 */
 struct omap_device {
-        u32                             magic;
        struct platform_device          pdev;
        struct omap_hwmod               **hwmods;
        struct omap_device_pm_latency   *pm_lats;
@@ -82,7 +83,6 @@ int omap_device_shutdown(struct platform_device *pdev);
 /* Core code interface */
-bool omap_device_is_valid(struct omap_device *od);
 int omap_device_count_resources(struct omap_device *od);
 int omap_device_fill_resources(struct omap_device *od, struct resource *res);
@@ -107,6 +107,7 @@ void __iomem *omap_device_get_rt_va(struct omap_device *od);
 int omap_device_align_pm_lat(struct platform_device *pdev,
                             u32 new_wakeup_lat_limit);
 struct powerdomain *omap_device_get_pwrdm(struct omap_device *od);
+u32 omap_device_get_context_loss_count(struct platform_device *pdev);
 /* Other */
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index a4e508dfaba2..1adea9c62984 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -1,7 +1,7 @@
 /*
 * omap_hwmod macros, structures
 *
- * Copyright (C) 2009-2010 Nokia Corporation
+ * Copyright (C) 2009-2011 Nokia Corporation
 * Paul Walmsley
 *
 * Created in collaboration with (alphabetical order): Benoît Cousson,
@@ -14,27 +14,26 @@
 *
 * These headers and macros are used to define OMAP on-chip module
 * data and their integration with other OMAP modules and Linux.
- *
+ * Copious documentation and references can also be found in the
- * References:
+ * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this
- * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
+ * writing).
- * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
- * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
- * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
- * - Open Core Protocol Specification 2.2
 *
 * To do:
 * - add interconnect error log structures
 * - add pinmuxing
 * - init_conn_id_bit (CONNID_BIT_VECTOR)
 * - implement default hwmod SMS/SDRC flags?
+ * - move Linux-specific data ("non-ROM data") out
 *
 */
 #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
 #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
 #include <linux/kernel.h>
+#include <linux/init.h>
 #include <linux/list.h>
 #include <linux/ioport.h>
+#include <linux/spinlock.h>
 #include <plat/cpu.h>
 struct omap_device;
@@ -78,6 +77,23 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
 #define HWMOD_IDLEMODE_FORCE            (1 << 0)
 #define HWMOD_IDLEMODE_NO               (1 << 1)
 #define HWMOD_IDLEMODE_SMART            (1 << 2)
+/* Slave idle mode flag only */
+#define HWMOD_IDLEMODE_SMART_WKUP       (1 << 3)
+/**
+ * struct omap_hwmod_mux_info - hwmod specific mux configuration
+ * @pads:              array of omap_device_pad entries
+ * @nr_pads:           number of omap_device_pad entries
+ *
+ * Note that this is currently built during init as needed.
+ */
+struct omap_hwmod_mux_info {
+        int                             nr_pads;
+        struct omap_device_pad          *pads;
+        int                             nr_pads_dynamic;
+        struct omap_device_pad          **pads_dynamic;
+        bool                            enabled;
+};
 /**
 * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
@@ -96,7 +112,7 @@ struct omap_hwmod_irq_info {
 /**
 * struct omap_hwmod_dma_info - DMA channels used by the hwmod
 * @name: name of the DMA channel (module local name)
- * @dma_ch: DMA channel ID
+ * @dma_req: DMA request ID
 *
 * @name should be something short, e.g., "tx" or "rx".  It is for use
 * by platform_get_resource_byname().  It is defined locally to the
@@ -104,7 +120,22 @@ struct omap_hwmod_irq_info {
 */
 struct omap_hwmod_dma_info {
        const char      *name;
-        u16             dma_ch;
+        u16             dma_req;
+};
+/**
+ * struct omap_hwmod_rst_info - IPs reset lines use by hwmod
+ * @name: name of the reset line (module local name)
+ * @rst_shift: Offset of the reset bit
+ * @st_shift: Offset of the reset status bit (OMAP2/3 only)
+ *
+ * @name should be something short, e.g., "cpu0" or "rst". It is defined
+ * locally to the hwmod.
+ */
+struct omap_hwmod_rst_info {
+        const char      *name;
+        u8              rst_shift;
+        u8              st_shift;
 };
 /**
@@ -148,11 +179,12 @@ struct omap_hwmod_omap2_firewall {
 * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init.
 * ADDR_TYPE_RT: Address space contains module register target data.
 */
-#define ADDR_MAP_ON_INIT        (1 << 0)
+#define ADDR_MAP_ON_INIT        (1 << 0)        /* XXX does not belong */
 #define ADDR_TYPE_RT            (1 << 1)
 /**
- * struct omap_hwmod_addr_space - MPU address space handled by the hwmod
+ * struct omap_hwmod_addr_space - address space handled by the hwmod
+ * @name: name of the address space
 * @pa_start: starting physical address
 * @pa_end: ending physical address
 * @flags: (see omap_hwmod_addr_space.flags macros above)
@@ -161,6 +193,7 @@ struct omap_hwmod_omap2_firewall {
 * structure.  GPMC is one example.
 */
 struct omap_hwmod_addr_space {
+        const char *name;
        u32 pa_start;
        u32 pa_end;
        u8 flags;
@@ -189,8 +222,6 @@ struct omap_hwmod_addr_space {
 * @fw: interface firewall data
 * @addr_cnt: ARRAY_SIZE(@addr)
 * @width: OCP data width
- * @thread_cnt: number of threads
- * @max_burst_len: maximum burst length in @width sized words (0 if unlimited)
 * @user: initiators using this interface (see OCP_USER_* macros above)
 * @flags: OCP interface flags (see OCPIF_* macros above)
 *
@@ -210,8 +241,6 @@ struct omap_hwmod_ocp_if {
        }                               fw;
        u8                              addr_cnt;
        u8                              width;
-        u8                              thread_cnt;
-        u8                              max_burst_len;
        u8                              user;
        u8                              flags;
 };
@@ -220,11 +249,12 @@ struct omap_hwmod_ocp_if {
 /* Macros for use in struct omap_hwmod_sysconfig */
 /* Flags for use in omap_hwmod_sysconfig.idlemodes */
-#define MASTER_STANDBY_SHIFT    2
+#define MASTER_STANDBY_SHIFT    4
 #define SLAVE_IDLE_SHIFT        0
 #define SIDLE_FORCE             (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT)
 #define SIDLE_NO                (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT)
 #define SIDLE_SMART             (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT)
+#define SIDLE_SMART_WKUP        (HWMOD_IDLEMODE_SMART_WKUP << SLAVE_IDLE_SHIFT)
 #define MSTANDBY_FORCE          (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
 #define MSTANDBY_NO             (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
 #define MSTANDBY_SMART          (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
@@ -237,8 +267,9 @@ struct omap_hwmod_ocp_if {
 #define SYSC_HAS_CLOCKACTIVITY  (1 << 4)
 #define SYSC_HAS_SIDLEMODE      (1 << 5)
 #define SYSC_HAS_MIDLEMODE      (1 << 6)
-#define SYSS_MISSING            (1 << 7)
+#define SYSS_HAS_RESET_STATUS   (1 << 7)
 #define SYSC_NO_CACHE           (1 << 8)  /* XXX SW flag, belongs elsewhere */
+#define SYSC_HAS_RESET_STATUS   (1 << 9)
 /* omap_hwmod_sysconfig.clockact flags */
 #define CLOCKACT_TEST_BOTH      0x0
@@ -327,10 +358,12 @@ struct omap_hwmod_omap2_prcm {
 /**
 * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
 * @clkctrl_reg: PRCM address of the clock control register
+ * @rstctrl_reg: address of the XXX_RSTCTRL register located in the PRM
 * @submodule_wkdep_bit: bit shift of the WKDEP range
 */
 struct omap_hwmod_omap4_prcm {
        void __iomem    *clkctrl_reg;
+        void __iomem    *rstctrl_reg;
        u8              submodule_wkdep_bit;
 };
@@ -343,15 +376,22 @@ struct omap_hwmod_omap4_prcm {
 * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
 *     of standby, rather than relying on module smart-standby
 * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
- *     SDRAM controller, etc.
+ *     SDRAM controller, etc. XXX probably belongs outside the main hwmod file
+ *     XXX Should be HWMOD_SETUP_NO_RESET
 * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
- *     controller, etc.
+ *     controller, etc. XXX probably belongs outside the main hwmod file
- * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
+ *     XXX Should be HWMOD_SETUP_NO_IDLE
+ * HWMOD_NO_OCP_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
 *     when module is enabled, rather than the default, which is to
 *     enable autoidle
 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
- * HWMOD_NO_IDLEST : this module does not have idle status - this is the case
+ * HWMOD_NO_IDLEST: this module does not have idle status - this is the case
 *     only for few initiator modules on OMAP2 & 3.
+ * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset.
+ *     This is needed for devices like DSS that require optional clocks enabled
+ *     in order to complete the reset. Optional clocks will be disabled
+ *     again after the reset.
+ * HWMOD_16BIT_REG: Module has 16bit registers
 */
 #define HWMOD_SWSUP_SIDLE                       (1 << 0)
 #define HWMOD_SWSUP_MSTANDBY                    (1 << 1)
@@ -360,6 +400,8 @@ struct omap_hwmod_omap4_prcm {
 #define HWMOD_NO_OCP_AUTOIDLE                   (1 << 4)
 #define HWMOD_SET_DEFAULT_CLOCKACT              (1 << 5)
 #define HWMOD_NO_IDLEST                         (1 << 6)
+#define HWMOD_CONTROL_OPT_CLKS_IN_RESET         (1 << 7)
+#define HWMOD_16BIT_REG                         (1 << 8)
 /*
 * omap_hwmod._int_flags definitions
@@ -394,14 +436,31 @@ struct omap_hwmod_omap4_prcm {
 * @name: name of the hwmod_class
 * @sysc: device SYSCONFIG/SYSSTATUS register data
 * @rev: revision of the IP class
+ * @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown
+ * @reset: ptr to fn to be executed in place of the standard hwmod reset fn
 *
 * Represent the class of a OMAP hardware "modules" (e.g. timer,
 * smartreflex, gpio, uart...)
+ *
+ * @pre_shutdown is a function that will be run immediately before
+ * hwmod clocks are disabled, etc.  It is intended for use for hwmods
+ * like the MPU watchdog, which cannot be disabled with the standard
+ * omap_hwmod_shutdown().  The function should return 0 upon success,
+ * or some negative error upon failure.  Returning an error will cause
+ * omap_hwmod_shutdown() to abort the device shutdown and return an
+ * error.
+ *
+ * If @reset is defined, then the function it points to will be
+ * executed in place of the standard hwmod _reset() code in
+ * mach-omap2/omap_hwmod.c.  This is needed for IP blocks which have
+ * unusual reset sequences - usually processor IP blocks like the IVA.
 */
 struct omap_hwmod_class {
        const char                              *name;
        struct omap_hwmod_class_sysconfig       *sysc;
        u32                                     rev;
+        int                                     (*pre_shutdown)(struct omap_hwmod *oh);
+        int                                     (*reset)(struct omap_hwmod *oh);
 };
 /**
@@ -410,29 +469,31 @@ struct omap_hwmod_class {
 * @class: struct omap_hwmod_class * to the class of this hwmod
 * @od: struct omap_device currently associated with this hwmod (internal use)
 * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
- * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt)
+ * @sdma_reqs: ptr to an array of System DMA request IDs (see sdma_reqs_cnt)
 * @prcm: PRCM data pertaining to this hwmod
 * @main_clk: main clock: OMAP clock name
 * @_clk: pointer to the main struct clk (filled in at runtime)
 * @opt_clks: other device clocks that drivers can request (0..*)
+ * @vdd_name: voltage domain name
+ * @voltdm: pointer to voltage domain (filled in at runtime)
 * @masters: ptr to array of OCP ifs that this hwmod can initiate on
 * @slaves: ptr to array of OCP ifs that this hwmod can respond on
 * @dev_attr: arbitrary device attributes that can be passed to the driver
 * @_sysc_cache: internal-use hwmod flags
 * @_mpu_rt_va: cached register target start address (internal use)
 * @_mpu_port_index: cached MPU register target slave ID (internal use)
- * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6)
- * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift
 * @mpu_irqs_cnt: number of @mpu_irqs
- * @sdma_chs_cnt: number of @sdma_chs
+ * @sdma_reqs_cnt: number of @sdma_reqs
 * @opt_clks_cnt: number of @opt_clks
 * @master_cnt: number of @master entries
 * @slaves_cnt: number of @slave entries
 * @response_lat: device OCP response latency (in interface clock cycles)
 * @_int_flags: internal-use hwmod flags
 * @_state: internal-use hwmod state
+ * @_postsetup_state: internal-use state to leave the hwmod in after _setup()
 * @flags: hwmod flags (documented below)
 * @omap_chip: OMAP chips this hwmod is present on
+ * @_lock: spinlock serializing operations on this hwmod
 * @node: list node for hwmod list (internal use)
 *
 * @main_clk refers to this module's "main clock," which for our
@@ -447,8 +508,10 @@ struct omap_hwmod {
        const char                      *name;
        struct omap_hwmod_class         *class;
        struct omap_device              *od;
+        struct omap_hwmod_mux_info      *mux;
        struct omap_hwmod_irq_info      *mpu_irqs;
-        struct omap_hwmod_dma_info      *sdma_chs;
+        struct omap_hwmod_dma_info      *sdma_reqs;
+        struct omap_hwmod_rst_info      *rst_lines;
        union {
                struct omap_hwmod_omap2_prcm omap2;
                struct omap_hwmod_omap4_prcm omap4;
@@ -456,35 +519,37 @@ struct omap_hwmod {
        const char                      *main_clk;
        struct clk                      *_clk;
        struct omap_hwmod_opt_clk       *opt_clks;
+        char                            *vdd_name;
+        struct voltagedomain            *voltdm;
        struct omap_hwmod_ocp_if        **masters; /* connect to *_IA */
        struct omap_hwmod_ocp_if        **slaves;  /* connect to *_TA */
        void                            *dev_attr;
        u32                             _sysc_cache;
        void __iomem                    *_mpu_rt_va;
+        spinlock_t                      _lock;
        struct list_head                node;
        u16                             flags;
        u8                              _mpu_port_index;
-        u8                              msuspendmux_reg_id;
-        u8                              msuspendmux_shift;
        u8                              response_lat;
        u8                              mpu_irqs_cnt;
-        u8                              sdma_chs_cnt;
+        u8                              sdma_reqs_cnt;
+        u8                              rst_lines_cnt;
        u8                              opt_clks_cnt;
        u8                              masters_cnt;
        u8                              slaves_cnt;
        u8                              hwmods_cnt;
        u8                              _int_flags;
        u8                              _state;
+        u8                              _postsetup_state;
        const struct omap_chip_id       omap_chip;
 };
-int omap_hwmod_init(struct omap_hwmod **ohs);
+int omap_hwmod_register(struct omap_hwmod **ohs);
-int omap_hwmod_register(struct omap_hwmod *oh);
-int omap_hwmod_unregister(struct omap_hwmod *oh);
 struct omap_hwmod *omap_hwmod_lookup(const char *name);
 int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
                        void *data);
-int omap_hwmod_late_init(u8 skip_setup_idle);
+int __init omap_hwmod_setup_one(const char *name);
 int omap_hwmod_enable(struct omap_hwmod *oh);
 int _omap_hwmod_enable(struct omap_hwmod *oh);
@@ -492,16 +557,21 @@ int omap_hwmod_idle(struct omap_hwmod *oh);
 int _omap_hwmod_idle(struct omap_hwmod *oh);
 int omap_hwmod_shutdown(struct omap_hwmod *oh);
+int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name);
+int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name);
+int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name);
 int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
 int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
 int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode);
+int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle);
 int omap_hwmod_reset(struct omap_hwmod *oh);
 void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
-void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs);
+void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
-u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs);
+u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
 int omap_hwmod_count_resources(struct omap_hwmod *oh);
 int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
@@ -527,6 +597,11 @@ int omap_hwmod_for_each_by_class(const char *classname,
                                           void *user),
                                 void *user);
+int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state);
+u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
+int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);
 /*
 * Chip variant-specific hwmod init routines - XXX should be converted
 * to use initcalls once the initial boot ordering is straightened out
@@ -534,5 +609,6 @@ int omap_hwmod_for_each_by_class(const char *classname,
 extern int omap2420_hwmod_init(void);
 extern int omap2430_hwmod_init(void);
 extern int omap3xxx_hwmod_init(void);
+extern int omap44xx_hwmod_init(void);
 #endif
diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h
index 72f433d7d827..2858667d2e4f 100644
--- a/arch/arm/plat-omap/include/plat/onenand.h
+++ b/arch/arm/plat-omap/include/plat/onenand.h
@@ -15,14 +15,24 @@
 #define ONENAND_SYNC_READ       (1 << 0)
 #define ONENAND_SYNC_READWRITE  (1 << 1)
+struct onenand_freq_info {
+        u16                     maf_id;
+        u16                     dev_id;
+        u16                     ver_id;
+};
 struct omap_onenand_platform_data {
        int                     cs;
        int                     gpio_irq;
        struct mtd_partition    *parts;
        int                     nr_parts;
-        int                     (*onenand_setup)(void __iomem *, int freq);
+        int                     (*onenand_setup)(void __iomem *, int *freq_ptr);
+        int             (*get_freq)(const struct onenand_freq_info *freq_info,
+                                    bool *clk_dep);
        int                     dma_channel;
        u8                      flags;
+        u8                      regulator_can_sleep;
+        u8                      skip_initial_unlocking;
 };
 #define ONENAND_MAX_PARTITIONS 8
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
deleted file mode 100644
index fb6ec74fe39e..000000000000
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * OMAP2/3 powerdomain control
- *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2009 Nokia Corporation
- *
- * Written by Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN
-#define ASM_ARM_ARCH_OMAP_POWERDOMAIN
-#include <linux/types.h>
-#include <linux/list.h>
-#include <asm/atomic.h>
-#include <plat/cpu.h>
-/* Powerdomain basic power states */
-#define PWRDM_POWER_OFF         0x0
-#define PWRDM_POWER_RET         0x1
-#define PWRDM_POWER_INACTIVE    0x2
-#define PWRDM_POWER_ON          0x3
-#define PWRDM_MAX_PWRSTS        4
-/* Powerdomain allowable state bitfields */
-#define PWRSTS_ON               (1 << PWRDM_POWER_ON)
-#define PWRSTS_OFF_ON           ((1 << PWRDM_POWER_OFF) | \
-                                 (1 << PWRDM_POWER_ON))
-#define PWRSTS_OFF_RET          ((1 << PWRDM_POWER_OFF) | \
-                                 (1 << PWRDM_POWER_RET))
-#define PWRSTS_RET_ON           ((1 << PWRDM_POWER_RET) | \
-                                 (1 << PWRDM_POWER_ON))
-#define PWRSTS_OFF_RET_ON       (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
-/* Powerdomain flags */
-#define PWRDM_HAS_HDWR_SAR      (1 << 0) /* hardware save-and-restore support */
-#define PWRDM_HAS_MPU_QUIRK     (1 << 1) /* MPU pwr domain has MEM bank 0 bits
-                                          * in MEM bank 1 position. This is
-                                          * true for OMAP3430
-                                          */
-#define PWRDM_HAS_LOWPOWERSTATECHANGE   (1 << 2) /*
-                                                  * support to transition from a
-                                                  * sleep state to a lower sleep
-                                                  * state without waking up the
-                                                  * powerdomain
-                                                  */
-/*
- * Number of memory banks that are power-controllable.  On OMAP4430, the
- * maximum is 5.
- */
-#define PWRDM_MAX_MEM_BANKS     5
-/*
- * Maximum number of clockdomains that can be associated with a powerdomain.
- * CORE powerdomain on OMAP4 is the worst case
- */
-#define PWRDM_MAX_CLKDMS        9
-/* XXX A completely arbitrary number. What is reasonable here? */
-#define PWRDM_TRANSITION_BAILOUT 100000
-struct clockdomain;
-struct powerdomain;
-/**
- * struct powerdomain - OMAP powerdomain
- * @name: Powerdomain name
- * @omap_chip: represents the OMAP chip types containing this pwrdm
- * @prcm_offs: the address offset from CM_BASE/PRM_BASE
- * @pwrsts: Possible powerdomain power states
- * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
- * @flags: Powerdomain flags
- * @banks: Number of software-controllable memory banks in this powerdomain
- * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
- * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
- * @pwrdm_clkdms: Clockdomains in this powerdomain
- * @node: list_head linking all powerdomains
- * @state:
- * @state_counter:
- * @timer:
- * @state_timer:
- */
-struct powerdomain {
-        const char *name;
-        const struct omap_chip_id omap_chip;
-        const s16 prcm_offs;
-        const u8 pwrsts;
-        const u8 pwrsts_logic_ret;
-        const u8 flags;
-        const u8 banks;
-        const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
-        const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
-        struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
-        struct list_head node;
-        int state;
-        unsigned state_counter[PWRDM_MAX_PWRSTS];
-        unsigned ret_logic_off_counter;
-        unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
-#ifdef CONFIG_PM_DEBUG
-        s64 timer;
-        s64 state_timer[PWRDM_MAX_PWRSTS];
-#endif
-};
-void pwrdm_init(struct powerdomain **pwrdm_list);
-struct powerdomain *pwrdm_lookup(const char *name);
-int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
-                        void *user);
-int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
-                        void *user);
-int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
-int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
-int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
-                         int (*fn)(struct powerdomain *pwrdm,
-                                   struct clockdomain *clkdm));
-int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
-int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
-int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
-int pwrdm_read_pwrst(struct powerdomain *pwrdm);
-int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
-int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
-int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
-int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
-int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
-int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
-int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
-int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
-int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
-int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
-int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
-int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
-int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
-bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
-int pwrdm_wait_transition(struct powerdomain *pwrdm);
-int pwrdm_state_switch(struct powerdomain *pwrdm);
-int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
-int pwrdm_pre_transition(void);
-int pwrdm_post_transition(void);
-#endif
diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h
index 9fbd91419cd1..267f43bb2a4e 100644
--- a/arch/arm/plat-omap/include/plat/prcm.h
+++ b/arch/arm/plat-omap/include/plat/prcm.h
@@ -18,30 +18,19 @@
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * XXX This file is deprecated.  The PRCM is an OMAP2+-only subsystem,
+ * so this file doesn't belong in plat-omap/include/plat.  Please
+ * do not add anything new to this file.
 */
 #ifndef __ASM_ARM_ARCH_OMAP_PRCM_H
 #define __ASM_ARM_ARCH_OMAP_PRCM_H
 u32 omap_prcm_get_reset_sources(void);
-void omap_prcm_arch_reset(char mode, const char *cmd);
 int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
                         const char *name);
-#define START_PADCONF_SAVE 0x2
-#define PADCONF_SAVE_DONE  0x1
-void omap3_prcm_save_context(void);
-void omap3_prcm_restore_context(void);
-u32 prm_read_mod_reg(s16 module, u16 idx);
-void prm_write_mod_reg(u32 val, s16 module, u16 idx);
-u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
-u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
-u32 cm_read_mod_reg(s16 module, u16 idx);
-void cm_write_mod_reg(u32 val, s16 module, u16 idx);
-u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
 #endif
diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
index 7b76f50564ba..925b12b500dc 100644
--- a/arch/arm/plat-omap/include/plat/sdrc.h
+++ b/arch/arm/plat-omap/include/plat/sdrc.h
@@ -124,8 +124,14 @@ struct omap_sdrc_params {
        u32 mr;
 };
-void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                            struct omap_sdrc_params *sdrc_cs1);
+#else
+static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+                                          struct omap_sdrc_params *sdrc_cs1) {};
+#endif
 int omap2_sdrc_get_params(unsigned long r,
                          struct omap_sdrc_params **sdrc_cs0,
                          struct omap_sdrc_params **sdrc_cs1);
@@ -147,6 +153,7 @@ struct memory_timings {
 };
 extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
+struct omap_sdrc_params *rx51_get_sdram_timings(void);
 u32 omap2xxx_sdrc_dll_is_unlocked(void);
 u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index 19145f5c32ba..2723f9166ea2 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -27,7 +27,7 @@
 * 2. We assume printascii is called at least once before paging_init,
 *    and addruart has a chance to read OMAP_UART_INFO
 */
-#define OMAP_UART_INFO          (PHYS_OFFSET + 0x3ffc)
+#define OMAP_UART_INFO          (PLAT_PHYS_OFFSET + 0x3ffc)
 /* OMAP1 serial ports */
 #define OMAP1_UART1_BASE        0xfffb0000
@@ -51,6 +51,11 @@
 #define OMAP4_UART3_BASE        0x48020000
 #define OMAP4_UART4_BASE        0x4806e000
+/* TI816X serial ports */
+#define TI816X_UART1_BASE       0x48020000
+#define TI816X_UART2_BASE       0x48022000
+#define TI816X_UART3_BASE       0x48024000
 /* External port on Zoom2/3 */
 #define ZOOM_UART_BASE          0x10000000
 #define ZOOM_UART_VIRT          0xfa400000
@@ -81,6 +86,9 @@
 #define OMAP4UART2              OMAP2UART2
 #define OMAP4UART3              43
 #define OMAP4UART4              44
+#define TI816XUART1             81
+#define TI816XUART2             82
+#define TI816XUART3             83
 #define ZOOM_UART               95              /* Only on zoom2/3 */
 /* This is only used by 8250.c for omap1510 */
@@ -93,9 +101,11 @@
                        })
 #ifndef __ASSEMBLER__
-extern void __init omap_serial_early_init(void);
+struct omap_board_data;
 extern void omap_serial_init(void);
-extern void omap_serial_init_port(int port);
+extern void omap_serial_init_port(struct omap_board_data *bdata);
 extern int omap_uart_can_sleep(void);
 extern void omap_uart_check_wakeup(void);
 extern void omap_uart_prepare_suspend(void);
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
deleted file mode 100644
index 5177a9c5a25a..000000000000
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * OMAP4 machine specific smp.h
- *
- * Copyright (C) 2009 Texas Instruments, Inc.
- *
- * Author:
- *      Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * Interface functions needed for the SMP. This file is based on arm
- * realview smp platform.
- * Copyright (c) 2003 ARM Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef OMAP_ARCH_SMP_H
-#define OMAP_ARCH_SMP_H
-#include <asm/hardware/gic.h>
-/* Needed for secondary core boot */
-extern void omap_secondary_startup(void);
-extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
-extern void omap_auxcoreboot_addr(u32 cpu_addr);
-extern u32 omap_read_auxcoreboot0(void);
-/*
- * We use Soft IRQ1 as the IPI
- */
-static inline void smp_cross_call(const struct cpumask *mask)
-{
-        gic_raise_softirq(mask, 1);
-}
-/*
- * Read MPIDR: Multiprocessor affinity register
- */
-#define hard_smp_processor_id()                 \
-        ({                                              \
-                unsigned int cpunum;                    \
-                __asm__("mrc p15, 0, %0, c0, c0, 5"     \
-                        : "=r" (cpunum));               \
-                cpunum &= 0x0F;                         \
-        })
-#endif
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 16a1b458d53c..f500fc34d065 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -11,8 +11,20 @@
 #ifndef __ARCH_ARM_OMAP_SRAM_H
 #define __ARCH_ARM_OMAP_SRAM_H
-extern int __init omap_sram_init(void);
+#ifndef __ASSEMBLY__
-extern void * omap_sram_push(void * start, unsigned long size);
+#include <asm/fncpy.h>
+extern void *omap_sram_push_address(unsigned long size);
+/* Macro to push a function to the internal SRAM, using the fncpy API */
+#define omap_sram_push(funcp, size) ({                          \
+        typeof(&(funcp)) _res = NULL;                           \
+        void *_sram_address = omap_sram_push_address(size);     \
+        if (_sram_address)                                      \
+                _res = fncpy(_sram_address, &(funcp), size);    \
+        _res;                                                   \
+})
 extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
 extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
@@ -75,4 +87,14 @@ extern void omap_push_sram_idle(void);
 static inline void omap_push_sram_idle(void) {}
 #endif /* CONFIG_PM */
+#endif /* __ASSEMBLY__ */
+/*
+ * OMAP2+: define the SRAM PA addresses.
+ * Used by the SRAM management code and the idle sleep code.
+ */
+#define OMAP2_SRAM_PA           0x40200000
+#define OMAP3_SRAM_PA           0x40200000
+#define OMAP4_SRAM_PA           0x40300000
 #endif
diff --git a/arch/arm/plat-omap/include/plat/system.h b/arch/arm/plat-omap/include/plat/system.h
index d0a119f735b4..c5fa9e929009 100644
--- a/arch/arm/plat-omap/include/plat/system.h
+++ b/arch/arm/plat-omap/include/plat/system.h
@@ -4,48 +4,14 @@
 */
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
-#include <linux/clk.h>
-#include <asm/mach-types.h>
+#include <asm/proc-fns.h>
-#include <mach/hardware.h>
-#include <plat/prcm.h>
-#ifndef CONFIG_MACH_VOICEBLUE
-#define voiceblue_reset()               do {} while (0)
-#else
-extern void voiceblue_reset(void);
-#endif
 static inline void arch_idle(void)
 {
        cpu_do_idle();
 }
-static inline void omap1_arch_reset(char mode, const char *cmd)
+extern void (*arch_reset)(char, const char *);
-{
-        /*
-         * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
-         * "Global Software Reset Affects Traffic Controller Frequency".
-         */
-        if (cpu_is_omap5912()) {
-                omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
-                                 DPLL_CTL);
-                omap_writew(0x8, ARM_RSTCT1);
-        }
-        if (machine_is_voiceblue())
-                voiceblue_reset();
-        else
-                omap_writew(1, ARM_RSTCT1);
-}
-static inline void arch_reset(char mode, const char *cmd)
-{
-        if (!cpu_class_is_omap2())
-                omap1_arch_reset(mode, cmd);
-        else
-                omap_prcm_arch_reset(mode, cmd);
-}
 #endif
diff --git a/arch/arm/plat-omap/include/plat/ti816x.h b/arch/arm/plat-omap/include/plat/ti816x.h
new file mode 100644
index 000000000000..50510f5dda1e
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/ti816x.h
@@ -0,0 +1,27 @@
+/*
+ * This file contains the address data for various TI816X modules.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARCH_TI816X_H
+#define __ASM_ARCH_TI816X_H
+#define L4_SLOW_TI816X_BASE     0x48000000
+#define TI816X_SCM_BASE         0x48140000
+#define TI816X_CTRL_BASE        TI816X_SCM_BASE
+#define TI816X_PRCM_BASE        0x48180000
+#define TI816X_ARM_INTC_BASE    0x48200000
+#endif /* __ASM_ARCH_TI816X_H */
diff --git a/arch/arm/plat-omap/include/plat/timer-gp.h b/arch/arm/plat-omap/include/plat/timer-gp.h
deleted file mode 100644
index c88d346b59d9..000000000000
--- a/arch/arm/plat-omap/include/plat/timer-gp.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * OMAP2/3 GPTIMER support.headers
- *
- * Copyright (C) 2009 Nokia Corporation
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
-#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
-int __init omap2_gp_clockevent_set_gptimer(u8 id);
-#endif
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index ddf723be48dc..ac4b60d9aa29 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -27,8 +27,8 @@
 #define MDR1_MODE_MASK                  0x07
-static volatile u8 *uart_base;
+volatile u8 *uart_base;
-static int uart_shift;
+int uart_shift;
 /*
 * Store the DEBUG_LL uart number into memory.
@@ -93,6 +93,10 @@ static inline void flush(void)
 #define DEBUG_LL_ZOOM(mach)                                             \
        _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
+#define DEBUG_LL_TI816X(p, mach)                                        \
+        _DEBUG_LL_ENTRY(mach, TI816X_UART##p##_BASE, OMAP_PORT_SHIFT,   \
+                TI816XUART##p)
 static inline void __arch_decomp_setup(unsigned long arch_id)
 {
        int port = 0;
@@ -125,7 +129,6 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                DEBUG_LL_OMAP1(3, sx1);
                /* omap2 based boards using UART1 */
-                DEBUG_LL_OMAP2(1, omap2evm);
                DEBUG_LL_OMAP2(1, omap_2430sdp);
                DEBUG_LL_OMAP2(1, omap_apollon);
                DEBUG_LL_OMAP2(1, omap_h4);
@@ -139,10 +142,17 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                DEBUG_LL_OMAP2(1, omap3evm);
                DEBUG_LL_OMAP3(1, omap_3430sdp);
                DEBUG_LL_OMAP3(1, omap_3630sdp);
+                DEBUG_LL_OMAP3(1, omap3530_lv_som);
+                DEBUG_LL_OMAP3(1, omap3_torpedo);
                /* omap3 based boards using UART3 */
                DEBUG_LL_OMAP3(3, cm_t35);
+                DEBUG_LL_OMAP3(3, cm_t3517);
+                DEBUG_LL_OMAP3(3, craneboard);
+                DEBUG_LL_OMAP3(3, devkit8000);
                DEBUG_LL_OMAP3(3, igep0020);
+                DEBUG_LL_OMAP3(3, igep0030);
+                DEBUG_LL_OMAP3(3, nokia_rm680);
                DEBUG_LL_OMAP3(3, nokia_rx51);
                DEBUG_LL_OMAP3(3, omap3517evm);
                DEBUG_LL_OMAP3(3, omap3_beagle);
@@ -153,11 +163,15 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                /* omap4 based boards using UART3 */
                DEBUG_LL_OMAP4(3, omap_4430sdp);
+                DEBUG_LL_OMAP4(3, omap4_panda);
                /* zoom2/3 external uart */
                DEBUG_LL_ZOOM(omap_zoom2);
                DEBUG_LL_ZOOM(omap_zoom3);
+                /* TI8168 base boards using UART3 */
+                DEBUG_LL_TI816X(3, ti8168evm);
        } while (0);
 }
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 2a9427c8cc48..17d3c939775c 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -7,14 +7,12 @@
 #include <plat/board.h>
 #define OMAP3_HS_USB_PORTS      3
-enum ehci_hcd_omap_mode {
-        EHCI_HCD_OMAP_MODE_UNKNOWN,
-        EHCI_HCD_OMAP_MODE_PHY,
-        EHCI_HCD_OMAP_MODE_TLL,
-};
-enum ohci_omap3_port_mode {
+enum usbhs_omap_port_mode {
-        OMAP_OHCI_PORT_MODE_UNUSED,
+        OMAP_USBHS_PORT_MODE_UNUSED,
+        OMAP_EHCI_PORT_MODE_PHY,
+        OMAP_EHCI_PORT_MODE_TLL,
+        OMAP_EHCI_PORT_MODE_HSIC,
        OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
        OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
        OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
@@ -24,24 +22,45 @@ enum ohci_omap3_port_mode {
        OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
        OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
        OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
-        OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM,
+        OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
 };
-struct ehci_hcd_omap_platform_data {
+struct usbhs_omap_board_data {
-        enum ehci_hcd_omap_mode         port_mode[OMAP3_HS_USB_PORTS];
+        enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
-        unsigned                        phy_reset:1;
        /* have to be valid if phy_reset is true and portx is in phy mode */
        int     reset_gpio_port[OMAP3_HS_USB_PORTS];
+        /* Set this to true for ES2.x silicon */
+        unsigned                        es2_compatibility:1;
+        unsigned                        phy_reset:1;
+        /*
+         * Regulators for USB PHYs.
+         * Each PHY can have a separate regulator.
+         */
+        struct regulator                *regulator[OMAP3_HS_USB_PORTS];
 };
-struct ohci_hcd_omap_platform_data {
+struct ehci_hcd_omap_platform_data {
-        enum ohci_omap3_port_mode       port_mode[OMAP3_HS_USB_PORTS];
+        enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
+        int                             reset_gpio_port[OMAP3_HS_USB_PORTS];
+        struct regulator                *regulator[OMAP3_HS_USB_PORTS];
+        unsigned                        phy_reset:1;
+};
-        /* Set this to true for ES2.x silicon */
+struct ohci_hcd_omap_platform_data {
+        enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
        unsigned                        es2_compatibility:1;
 };
+struct usbhs_omap_platform_data {
+        enum usbhs_omap_port_mode               port_mode[OMAP3_HS_USB_PORTS];
+        struct ehci_hcd_omap_platform_data      *ehci_data;
+        struct ohci_hcd_omap_platform_data      *ohci_data;
+};
 /*-------------------------------------------------------------------------*/
 #define OMAP1_OTG_BASE                  0xfffb0400
@@ -69,18 +88,32 @@ struct omap_musb_board_data {
        u8      mode;
        u16     power;
        unsigned extvbus:1;
+        void    (*set_phy_power)(u8 on);
+        void    (*clear_irq)(void);
+        void    (*set_mode)(u8 mode);
+        void    (*reset)(void);
 };
 enum musb_interface    {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
 extern void usb_musb_init(struct omap_musb_board_data *board_data);
-extern void usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata);
+extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
-extern void usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata);
+extern int omap_usbhs_enable(struct device *dev);
+extern void omap_usbhs_disable(struct device *dev);
+extern int omap4430_phy_power(struct device *dev, int ID, int on);
+extern int omap4430_phy_set_clk(struct device *dev, int on);
+extern int omap4430_phy_init(struct device *dev);
+extern int omap4430_phy_exit(struct device *dev);
+extern int omap4430_phy_suspend(struct device *dev, int suspend);
 #endif
+extern void am35x_musb_reset(void);
+extern void am35x_musb_phy_power(u8 on);
+extern void am35x_musb_clear_irq(void);
+extern void am35x_set_mode(u8 musb_mode);
 /*
 * FIXME correct answer depends on hmc_mode,
@@ -105,7 +138,7 @@ static inline void omap1_usb_init(struct omap_usb_config *pdata)
 #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
 void omap2_usbfs_init(struct omap_usb_config *pdata);
 #else
-static inline omap2_usbfs_init(struct omap_usb_config *pdata)
+static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
 {
 }
 #endif
@@ -218,6 +251,27 @@ static inline omap2_usbfs_init(struct omap_usb_config *pdata)
 #       define  USBT2TLL5PI             (1 << 17)
 #       define  USB0PUENACTLOI          (1 << 16)
 #       define  USBSTANDBYCTRL          (1 << 15)
+/* AM35x */
+/* USB 2.0 PHY Control */
+#define CONF2_PHY_GPIOMODE      (1 << 23)
+#define CONF2_OTGMODE           (3 << 14)
+#define CONF2_NO_OVERRIDE       (0 << 14)
+#define CONF2_FORCE_HOST        (1 << 14)
+#define CONF2_FORCE_DEVICE      (2 << 14)
+#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
+#define CONF2_SESENDEN          (1 << 13)
+#define CONF2_VBDTCTEN          (1 << 12)
+#define CONF2_REFFREQ_24MHZ     (2 << 8)
+#define CONF2_REFFREQ_26MHZ     (7 << 8)
+#define CONF2_REFFREQ_13MHZ     (6 << 8)
+#define CONF2_REFFREQ           (0xf << 8)
+#define CONF2_PHYCLKGD          (1 << 7)
+#define CONF2_VBUSSENSE         (1 << 6)
+#define CONF2_PHY_PLLON         (1 << 5)
+#define CONF2_RESET             (1 << 4)
+#define CONF2_PHYPWRDN          (1 << 3)
+#define CONF2_OTGPWRDN          (1 << 2)
+#define CONF2_DATPOL            (1 << 1)
 #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
 u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
diff --git a/arch/arm/plat-omap/include/plat/vrfb.h b/arch/arm/plat-omap/include/plat/vrfb.h
index d8a03ced3b10..3792bdea2f6d 100644
--- a/arch/arm/plat-omap/include/plat/vrfb.h
+++ b/arch/arm/plat-omap/include/plat/vrfb.h
@@ -35,6 +35,7 @@ struct vrfb {
        bool yuv_mode;
 };
+#ifdef CONFIG_OMAP2_VRFB
 extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
 extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
 extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
@@ -47,4 +48,19 @@ extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
 extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot);
 extern void omap_vrfb_restore_context(void);
+#else
+static inline int omap_vrfb_request_ctx(struct vrfb *vrfb) { return 0; }
+static inline void omap_vrfb_release_ctx(struct vrfb *vrfb) {}
+static inline void omap_vrfb_adjust_size(u16 *width, u16 *height,
+                u8 bytespp) {}
+static inline u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp)
+                { return 0; }
+static inline u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp)
+                { return 0; }
+static inline void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
+                u16 width, u16 height, unsigned bytespp, bool yuv_mode) {}
+static inline int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot)
+                { return 0; }
+static inline void omap_vrfb_restore_context(void) {}
+#endif
 #endif /* __VRFB_H */
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index b0078cf96281..f1ecfa9fc61d 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -85,7 +85,10 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
        }
 #endif
 #ifdef CONFIG_ARCH_OMAP3
-        if (cpu_is_omap34xx()) {
+        if (cpu_is_ti816x()) {
+                if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
+                        return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
+        } else if (cpu_is_omap34xx()) {
                if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE))
                        return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);
                if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
@@ -136,61 +139,3 @@ void omap_iounmap(volatile void __iomem *addr)
                __iounmap(addr);
 }
 EXPORT_SYMBOL(omap_iounmap);
-/*
- * NOTE: Please use ioremap + __raw_read/write where possible instead of these
- */
-u8 omap_readb(u32 pa)
-{
-        if (cpu_class_is_omap1())
-                return __raw_readb(OMAP1_IO_ADDRESS(pa));
-        else
-                return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_readb);
-u16 omap_readw(u32 pa)
-{
-        if (cpu_class_is_omap1())
-                return __raw_readw(OMAP1_IO_ADDRESS(pa));
-        else
-                return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_readw);
-u32 omap_readl(u32 pa)
-{
-        if (cpu_class_is_omap1())
-                return __raw_readl(OMAP1_IO_ADDRESS(pa));
-        else
-                return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_readl);
-void omap_writeb(u8 v, u32 pa)
-{
-        if (cpu_class_is_omap1())
-                __raw_writeb(v, OMAP1_IO_ADDRESS(pa));
-        else
-                __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_writeb);
-void omap_writew(u16 v, u32 pa)
-{
-        if (cpu_class_is_omap1())
-                __raw_writew(v, OMAP1_IO_ADDRESS(pa));
-        else
-                __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_writew);
-void omap_writel(u32 v, u32 pa)
-{
-        if (cpu_class_is_omap1())
-                __raw_writel(v, OMAP1_IO_ADDRESS(pa));
-        else
-                __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_writel);
diff --git a/arch/arm/plat-omap/iommu-debug.c b/arch/arm/plat-omap/iommu-debug.c
index e6c0d536899c..f07cf2f08e09 100644
--- a/arch/arm/plat-omap/iommu-debug.c
+++ b/arch/arm/plat-omap/iommu-debug.c
@@ -328,12 +328,14 @@ static int debug_open_generic(struct inode *inode, struct file *file)
                .open = debug_open_generic,                             \
                .read = debug_read_##name,                              \
                .write = debug_write_##name,                            \
+                .llseek = generic_file_llseek,                          \
        };
 #define DEBUG_FOPS_RO(name)                                             \
        static const struct file_operations debug_##name##_fops = {     \
                .open = debug_open_generic,                             \
                .read = debug_read_##name,                              \
+                .llseek = generic_file_llseek,                          \
        };
 DEBUG_FOPS_RO(ver);
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index 6cd151b31bc5..34fc31ee9081 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -104,6 +104,9 @@ static int iommu_enable(struct iommu *obj)
        if (!obj)
                return -EINVAL;
+        if (!arch_iommu)
+                return -ENODEV;
        clk_enable(obj->clk);
        err = arch_iommu->enable(obj);
@@ -780,25 +783,21 @@ static void iopgtable_clear_entry_all(struct iommu *obj)
 */
 static irqreturn_t iommu_fault_handler(int irq, void *data)
 {
-        u32 stat, da;
+        u32 da, errs;
        u32 *iopgd, *iopte;
-        int err = -EIO;
        struct iommu *obj = data;
        if (!obj->refcount)
                return IRQ_NONE;
-        /* Dynamic loading TLB or PTE */
-        if (obj->isr)
-                err = obj->isr(obj);
-        if (!err)
-                return IRQ_HANDLED;
        clk_enable(obj->clk);
-        stat = iommu_report_fault(obj, &da);
+        errs = iommu_report_fault(obj, &da);
        clk_disable(obj->clk);
-        if (!stat)
+        if (errs == 0)
+                return IRQ_HANDLED;
+        /* Fault callback or TLB/PTE Dynamic loading */
+        if (obj->isr && !obj->isr(obj, da, errs, obj->isr_priv))
                return IRQ_HANDLED;
        iommu_disable(obj);
@@ -806,15 +805,16 @@ static irqreturn_t iommu_fault_handler(int irq, void *data)
        iopgd = iopgd_offset(obj, da);
        if (!iopgd_is_table(*iopgd)) {
-                dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__,
+                dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p "
-                        da, iopgd, *iopgd);
+                        "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd);
                return IRQ_NONE;
        }
        iopte = iopte_offset(iopgd, da);
-        dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
+        dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x "
-                __func__, da, iopgd, *iopgd, iopte, *iopte);
+                "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd,
+                iopte, *iopte);
        return IRQ_NONE;
 }
@@ -830,6 +830,28 @@ static int device_match_by_alias(struct device *dev, void *data)
 }
 /**
+ * iommu_set_da_range - Set a valid device address range
+ * @obj:                target iommu
+ * @start               Start of valid range
+ * @end                 End of valid range
+ **/
+int iommu_set_da_range(struct iommu *obj, u32 start, u32 end)
+{
+        if (!obj)
+                return -EFAULT;
+        if (end < start || !PAGE_ALIGN(start | end))
+                return -EINVAL;
+        obj->da_start = start;
+        obj->da_end = end;
+        return 0;
+}
+EXPORT_SYMBOL_GPL(iommu_set_da_range);
+/**
 * iommu_get - Get iommu handler
 * @name:       target iommu name
 **/
@@ -895,6 +917,33 @@ void iommu_put(struct iommu *obj)
 }
 EXPORT_SYMBOL_GPL(iommu_put);
+int iommu_set_isr(const char *name,
+                  int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs,
+                             void *priv),
+                  void *isr_priv)
+{
+        struct device *dev;
+        struct iommu *obj;
+        dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name,
+                                 device_match_by_alias);
+        if (!dev)
+                return -ENODEV;
+        obj = to_iommu(dev);
+        mutex_lock(&obj->iommu_lock);
+        if (obj->refcount != 0) {
+                mutex_unlock(&obj->iommu_lock);
+                return -EBUSY;
+        }
+        obj->isr = isr;
+        obj->isr_priv = isr_priv;
+        mutex_unlock(&obj->iommu_lock);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(iommu_set_isr);
 /*
 *      OMAP Device MMU(IOMMU) detection
 */
@@ -922,6 +971,8 @@ static int __devinit omap_iommu_probe(struct platform_device *pdev)
        obj->name = pdata->name;
        obj->dev = &pdev->dev;
        obj->ctx = (void *)obj + sizeof(*obj);
+        obj->da_start = pdata->da_start;
+        obj->da_end = pdata->da_end;
        mutex_init(&obj->iommu_lock);
        mutex_init(&obj->mmap_lock);
@@ -933,11 +984,6 @@ static int __devinit omap_iommu_probe(struct platform_device *pdev)
                err = -ENODEV;
                goto err_mem;
        }
-        obj->regbase = ioremap(res->start, resource_size(res));
-        if (!obj->regbase) {
-                err = -ENOMEM;
-                goto err_mem;
-        }
        res = request_mem_region(res->start, resource_size(res),
                                 dev_name(&pdev->dev));
@@ -946,6 +992,12 @@ static int __devinit omap_iommu_probe(struct platform_device *pdev)
                goto err_mem;
        }
+        obj->regbase = ioremap(res->start, resource_size(res));
+        if (!obj->regbase) {
+                err = -ENOMEM;
+                goto err_ioremap;
+        }
        irq = platform_get_irq(pdev, 0);
        if (irq < 0) {
                err = -ENODEV;
@@ -974,8 +1026,9 @@ static int __devinit omap_iommu_probe(struct platform_device *pdev)
 err_pgd:
        free_irq(irq, obj);
 err_irq:
-        release_mem_region(res->start, resource_size(res));
        iounmap(obj->regbase);
+err_ioremap:
+        release_mem_region(res->start, resource_size(res));
 err_mem:
        clk_put(obj->clk);
 err_clk:
diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c
index 8ce0de247c71..83a37c54342f 100644
--- a/arch/arm/plat-omap/iovmm.c
+++ b/arch/arm/plat-omap/iovmm.c
@@ -87,35 +87,43 @@ static size_t sgtable_len(const struct sg_table *sgt)
 }
 #define sgtable_ok(x)   (!!sgtable_len(x))
+static unsigned max_alignment(u32 addr)
+{
+        int i;
+        unsigned pagesize[] = { SZ_16M, SZ_1M, SZ_64K, SZ_4K, };
+        for (i = 0; i < ARRAY_SIZE(pagesize) && addr & (pagesize[i] - 1); i++)
+                ;
+        return (i < ARRAY_SIZE(pagesize)) ? pagesize[i] : 0;
+}
 /*
 * calculate the optimal number sg elements from total bytes based on
 * iommu superpages
 */
-static unsigned int sgtable_nents(size_t bytes)
+static unsigned sgtable_nents(size_t bytes, u32 da, u32 pa)
 {
-        int i;
+        unsigned nr_entries = 0, ent_sz;
-        unsigned int nr_entries;
-        const unsigned long pagesize[] = { SZ_16M, SZ_1M, SZ_64K, SZ_4K, };
        if (!IS_ALIGNED(bytes, PAGE_SIZE)) {
                pr_err("%s: wrong size %08x\n", __func__, bytes);
                return 0;
        }
-        nr_entries = 0;
+        while (bytes) {
-        for (i = 0; i < ARRAY_SIZE(pagesize); i++) {
+                ent_sz = max_alignment(da | pa);
-                if (bytes >= pagesize[i]) {
+                ent_sz = min_t(unsigned, ent_sz, iopgsz_max(bytes));
-                        nr_entries += (bytes / pagesize[i]);
+                nr_entries++;
-                        bytes %= pagesize[i];
+                da += ent_sz;
-                }
+                pa += ent_sz;
+                bytes -= ent_sz;
        }
-        BUG_ON(bytes);
        return nr_entries;
 }
 /* allocate and initialize sg_table header(a kind of 'superblock') */
-static struct sg_table *sgtable_alloc(const size_t bytes, u32 flags)
+static struct sg_table *sgtable_alloc(const size_t bytes, u32 flags,
+                                                        u32 da, u32 pa)
 {
        unsigned int nr_entries;
        int err;
@@ -127,9 +135,8 @@ static struct sg_table *sgtable_alloc(const size_t bytes, u32 flags)
        if (!IS_ALIGNED(bytes, PAGE_SIZE))
                return ERR_PTR(-EINVAL);
-        /* FIXME: IOVMF_DA_FIXED should support 'superpages' */
+        if (flags & IOVMF_LINEAR) {
-        if ((flags & IOVMF_LINEAR) && (flags & IOVMF_DA_ANON)) {
+                nr_entries = sgtable_nents(bytes, da, pa);
-                nr_entries = sgtable_nents(bytes);
                if (!nr_entries)
                        return ERR_PTR(-EINVAL);
        } else
@@ -264,22 +271,24 @@ static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da,
                                           size_t bytes, u32 flags)
 {
        struct iovm_struct *new, *tmp;
-        u32 start, prev_end, alignement;
+        u32 start, prev_end, alignment;
        if (!obj || !bytes)
                return ERR_PTR(-EINVAL);
        start = da;
-        alignement = PAGE_SIZE;
+        alignment = PAGE_SIZE;
+        if (~flags & IOVMF_DA_FIXED) {
+                /* Don't map address 0 */
+                start = obj->da_start ? obj->da_start : alignment;
-        if (flags & IOVMF_DA_ANON) {
-                /*
-                 * Reserve the first page for NULL
-                 */
-                start = PAGE_SIZE;
                if (flags & IOVMF_LINEAR)
-                        alignement = iopgsz_max(bytes);
+                        alignment = iopgsz_max(bytes);
-                start = roundup(start, alignement);
+                start = roundup(start, alignment);
+        } else if (start < obj->da_start || start > obj->da_end ||
+                                        obj->da_end - start < bytes) {
+                return ERR_PTR(-EINVAL);
        }
        tmp = NULL;
@@ -289,19 +298,19 @@ static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da,
        prev_end = 0;
        list_for_each_entry(tmp, &obj->mmap, list) {
-                if (prev_end >= start)
+                if (prev_end > start)
                        break;
-                if (start + bytes < tmp->da_start)
+                if (tmp->da_start > start && (tmp->da_start - start) >= bytes)
                        goto found;
-                if (flags & IOVMF_DA_ANON)
+                if (tmp->da_end >= start && ~flags & IOVMF_DA_FIXED)
-                        start = roundup(tmp->da_end + 1, alignement);
+                        start = roundup(tmp->da_end + 1, alignment);
                prev_end = tmp->da_end;
        }
-        if ((start > prev_end) && (ULONG_MAX - start >= bytes))
+        if ((start >= prev_end) && (obj->da_end - start >= bytes))
                goto found;
        dev_dbg(obj->dev, "%s: no space to fit %08x(%x) flags: %08x\n",
@@ -409,7 +418,8 @@ static inline void sgtable_drain_vmalloc(struct sg_table *sgt)
        BUG_ON(!sgt);
 }
-static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, size_t len)
+static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, u32 da,
+                                                                size_t len)
 {
        unsigned int i;
        struct scatterlist *sg;
@@ -418,9 +428,10 @@ static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, size_t len)
        va = phys_to_virt(pa);
        for_each_sg(sgt->sgl, sg, sgt->nents, i) {
-                size_t bytes;
+                unsigned bytes;
-                bytes = iopgsz_max(len);
+                bytes = max_alignment(da | pa);
+                bytes = min_t(unsigned, bytes, iopgsz_max(len));
                BUG_ON(!iopgsz_ok(bytes));
@@ -429,6 +440,7 @@ static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, size_t len)
                 * 'pa' is cotinuous(linear).
                 */
                pa += bytes;
+                da += bytes;
                len -= bytes;
        }
        BUG_ON(len);
@@ -636,10 +648,8 @@ u32 iommu_vmap(struct iommu *obj, u32 da, const struct sg_table *sgt,
                        return PTR_ERR(va);
        }
-        flags &= IOVMF_HW_MASK;
        flags |= IOVMF_DISCONT;
        flags |= IOVMF_MMIO;
-        flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
        da = __iommu_vmap(obj, da, sgt, va, bytes, flags);
        if (IS_ERR_VALUE(da))
@@ -679,7 +689,7 @@ EXPORT_SYMBOL_GPL(iommu_vunmap);
 * @flags:      iovma and page property
 *
 * Allocate @bytes linearly and creates 1-n-1 mapping and returns
- * @da again, which might be adjusted if 'IOVMF_DA_ANON' is set.
+ * @da again, which might be adjusted if 'IOVMF_DA_FIXED' is not set.
 */
 u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags)
 {
@@ -695,18 +705,16 @@ u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags)
        if (!va)
                return -ENOMEM;
-        sgt = sgtable_alloc(bytes, flags);
+        flags |= IOVMF_DISCONT;
+        flags |= IOVMF_ALLOC;
+        sgt = sgtable_alloc(bytes, flags, da, 0);
        if (IS_ERR(sgt)) {
                da = PTR_ERR(sgt);
                goto err_sgt_alloc;
        }
        sgtable_fill_vmalloc(sgt, va);
-        flags &= IOVMF_HW_MASK;
-        flags |= IOVMF_DISCONT;
-        flags |= IOVMF_ALLOC;
-        flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
        da = __iommu_vmap(obj, da, sgt, va, bytes, flags);
        if (IS_ERR_VALUE(da))
                goto err_iommu_vmap;
@@ -746,11 +754,11 @@ static u32 __iommu_kmap(struct iommu *obj, u32 da, u32 pa, void *va,
 {
        struct sg_table *sgt;
-        sgt = sgtable_alloc(bytes, flags);
+        sgt = sgtable_alloc(bytes, flags, da, pa);
        if (IS_ERR(sgt))
                return PTR_ERR(sgt);
-        sgtable_fill_kmalloc(sgt, pa, bytes);
+        sgtable_fill_kmalloc(sgt, pa, da, bytes);
        da = map_iommu_region(obj, da, sgt, va, bytes, flags);
        if (IS_ERR_VALUE(da)) {
@@ -769,7 +777,7 @@ static u32 __iommu_kmap(struct iommu *obj, u32 da, u32 pa, void *va,
 * @flags:      iovma and page property
 *
 * Creates 1-1-1 mapping and returns @da again, which can be
- * adjusted if 'IOVMF_DA_ANON' is set.
+ * adjusted if 'IOVMF_DA_FIXED' is not set.
 */
 u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes,
                 u32 flags)
@@ -785,10 +793,8 @@ u32 iommu_kmap(struct iommu *obj, u32 da, u32 pa, size_t bytes,
        if (!va)
                return -ENOMEM;
-        flags &= IOVMF_HW_MASK;
        flags |= IOVMF_LINEAR;
        flags |= IOVMF_MMIO;
-        flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
        da = __iommu_kmap(obj, da, pa, va, bytes, flags);
        if (IS_ERR_VALUE(da))
@@ -811,7 +817,7 @@ void iommu_kunmap(struct iommu *obj, u32 da)
        struct sg_table *sgt;
        typedef void (*func_t)(const void *);
-        sgt = unmap_vm_area(obj, da, (func_t)__iounmap,
+        sgt = unmap_vm_area(obj, da, (func_t)iounmap,
                            IOVMF_LINEAR | IOVMF_MMIO);
        if (!sgt)
                dev_dbg(obj->dev, "%s: No sgt\n", __func__);
@@ -827,7 +833,7 @@ EXPORT_SYMBOL_GPL(iommu_kunmap);
 * @flags:      iovma and page property
 *
 * Allocate @bytes linearly and creates 1-1-1 mapping and returns
- * @da again, which might be adjusted if 'IOVMF_DA_ANON' is set.
+ * @da again, which might be adjusted if 'IOVMF_DA_FIXED' is not set.
 */
 u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags)
 {
@@ -844,10 +850,8 @@ u32 iommu_kmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags)
                return -ENOMEM;
        pa = virt_to_phys(va);
-        flags &= IOVMF_HW_MASK;
        flags |= IOVMF_LINEAR;
        flags |= IOVMF_ALLOC;
-        flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
        da = __iommu_kmap(obj, da, pa, va, bytes, flags);
        if (IS_ERR_VALUE(da))
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index d2fafb892f7f..69ddc9f76c13 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -28,12 +28,11 @@
 #include <linux/slab.h>
 #include <linux/kfifo.h>
 #include <linux/err.h>
+#include <linux/notifier.h>
 #include <plat/mailbox.h>
-static struct workqueue_struct *mboxd;
 static struct omap_mbox **mboxes;
-static bool rq_full;
 static int mbox_configured;
 static DEFINE_MUTEX(mbox_configured_lock);
@@ -93,20 +92,25 @@ int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
        struct omap_mbox_queue *mq = mbox->txq;
        int ret = 0, len;
-        spin_lock(&mq->lock);
+        spin_lock_bh(&mq->lock);
        if (kfifo_avail(&mq->fifo) < sizeof(msg)) {
                ret = -ENOMEM;
                goto out;
        }
+        if (kfifo_is_empty(&mq->fifo) && !__mbox_poll_for_space(mbox)) {
+                mbox_fifo_write(mbox, msg);
+                goto out;
+        }
        len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
        WARN_ON(len != sizeof(msg));
        tasklet_schedule(&mbox->txq->tasklet);
 out:
-        spin_unlock(&mq->lock);
+        spin_unlock_bh(&mq->lock);
        return ret;
 }
 EXPORT_SYMBOL(omap_mbox_msg_send);
@@ -146,8 +150,14 @@ static void mbox_rx_work(struct work_struct *work)
                len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
                WARN_ON(len != sizeof(msg));
-                if (mq->callback)
+                blocking_notifier_call_chain(&mq->mbox->notifier, len,
-                        mq->callback((void *)msg);
+                                                                (void *)msg);
+                spin_lock_irq(&mq->lock);
+                if (mq->full) {
+                        mq->full = false;
+                        omap_mbox_enable_irq(mq->mbox, IRQ_RX);
+                }
+                spin_unlock_irq(&mq->lock);
        }
 }
@@ -170,7 +180,7 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox)
        while (!mbox_fifo_empty(mbox)) {
                if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
                        omap_mbox_disable_irq(mbox, IRQ_RX);
-                        rq_full = true;
+                        mq->full = true;
                        goto nomem;
                }
@@ -186,7 +196,7 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox)
        /* no more messages in the fifo. clear IRQ source. */
        ack_mbox_irq(mbox, IRQ_RX);
 nomem:
-        queue_work(mboxd, &mbox->rxq->work);
+        schedule_work(&mbox->rxq->work);
 }
 static irqreturn_t mbox_interrupt(int irq, void *p)
@@ -239,83 +249,90 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
        int ret = 0;
        struct omap_mbox_queue *mq;
-        if (mbox->ops->startup) {
+        mutex_lock(&mbox_configured_lock);
-                mutex_lock(&mbox_configured_lock);
+        if (!mbox_configured++) {
-                if (!mbox_configured)
+                if (likely(mbox->ops->startup)) {
                        ret = mbox->ops->startup(mbox);
+                        if (unlikely(ret))
-                if (ret) {
+                                goto fail_startup;
-                        mutex_unlock(&mbox_configured_lock);
+                } else
-                        return ret;
+                        goto fail_startup;
-                }
-                mbox_configured++;
-                mutex_unlock(&mbox_configured_lock);
        }
-        ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
+        if (!mbox->use_count++) {
-                                mbox->name, mbox);
+                ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
-        if (ret) {
+                                                        mbox->name, mbox);
-                printk(KERN_ERR
+                if (unlikely(ret)) {
-                        "failed to register mailbox interrupt:%d\n", ret);
+                        pr_err("failed to register mailbox interrupt:%d\n",
-                goto fail_request_irq;
+                                                                        ret);
-        }
+                        goto fail_request_irq;
+                }
-        mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet);
+                mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet);
-        if (!mq) {
+                if (!mq) {
-                ret = -ENOMEM;
+                        ret = -ENOMEM;
-                goto fail_alloc_txq;
+                        goto fail_alloc_txq;
-        }
+                }
-        mbox->txq = mq;
+                mbox->txq = mq;
-        mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL);
+                mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL);
-        if (!mq) {
+                if (!mq) {
-                ret = -ENOMEM;
+                        ret = -ENOMEM;
-                goto fail_alloc_rxq;
+                        goto fail_alloc_rxq;
+                }
+                mbox->rxq = mq;
+                mq->mbox = mbox;
        }
-        mbox->rxq = mq;
+        mutex_unlock(&mbox_configured_lock);
        return 0;
- fail_alloc_rxq:
+fail_alloc_rxq:
        mbox_queue_free(mbox->txq);
- fail_alloc_txq:
+fail_alloc_txq:
        free_irq(mbox->irq, mbox);
- fail_request_irq:
+fail_request_irq:
        if (mbox->ops->shutdown)
                mbox->ops->shutdown(mbox);
+        mbox->use_count--;
+fail_startup:
+        mbox_configured--;
+        mutex_unlock(&mbox_configured_lock);
        return ret;
 }
 static void omap_mbox_fini(struct omap_mbox *mbox)
 {
-        free_irq(mbox->irq, mbox);
+        mutex_lock(&mbox_configured_lock);
-        tasklet_kill(&mbox->txq->tasklet);
-        flush_work(&mbox->rxq->work);
+        if (!--mbox->use_count) {
-        mbox_queue_free(mbox->txq);
+                free_irq(mbox->irq, mbox);
-        mbox_queue_free(mbox->rxq);
+                tasklet_kill(&mbox->txq->tasklet);
+        flush_work_sync(&mbox->rxq->work);
+                mbox_queue_free(mbox->txq);
+                mbox_queue_free(mbox->rxq);
+        }
-        if (mbox->ops->shutdown) {
+        if (likely(mbox->ops->shutdown)) {
-                mutex_lock(&mbox_configured_lock);
+                if (!--mbox_configured)
-                if (mbox_configured > 0)
-                        mbox_configured--;
-                if (!mbox_configured)
                        mbox->ops->shutdown(mbox);
-                mutex_unlock(&mbox_configured_lock);
        }
+        mutex_unlock(&mbox_configured_lock);
 }
-struct omap_mbox *omap_mbox_get(const char *name)
+struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb)
 {
-        struct omap_mbox *mbox;
+        struct omap_mbox *_mbox, *mbox = NULL;
-        int ret;
+        int i, ret;
        if (!mboxes)
                return ERR_PTR(-EINVAL);
-        for (mbox = *mboxes; mbox; mbox++)
+        for (i = 0; (_mbox = mboxes[i]); i++) {
-                if (!strcmp(mbox->name, name))
+                if (!strcmp(_mbox->name, name)) {
+                        mbox = _mbox;
                        break;
+                }
+        }
        if (!mbox)
                return ERR_PTR(-ENOENT);
@@ -324,12 +341,16 @@ struct omap_mbox *omap_mbox_get(const char *name)
        if (ret)
                return ERR_PTR(-ENODEV);
+        if (nb)
+                blocking_notifier_chain_register(&mbox->notifier, nb);
        return mbox;
 }
 EXPORT_SYMBOL(omap_mbox_get);
-void omap_mbox_put(struct omap_mbox *mbox)
+void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb)
 {
+        blocking_notifier_chain_unregister(&mbox->notifier, nb);
        omap_mbox_fini(mbox);
 }
 EXPORT_SYMBOL(omap_mbox_put);
@@ -353,6 +374,8 @@ int omap_mbox_register(struct device *parent, struct omap_mbox **list)
                        ret = PTR_ERR(mbox->dev);
                        goto err_out;
                }
+                BLOCKING_INIT_NOTIFIER_HEAD(&mbox->notifier);
        }
        return 0;
@@ -385,13 +408,10 @@ static int __init omap_mbox_init(void)
        if (err)
                return err;
-        mboxd = create_workqueue("mboxd");
-        if (!mboxd)
-                return -ENOMEM;
        /* kfifo size sanity check: alignment and minimal size */
        mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t));
-        mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, sizeof(mbox_msg_t));
+        mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size,
+                                                        sizeof(mbox_msg_t));
        return 0;
 }
@@ -399,7 +419,6 @@ subsys_initcall(omap_mbox_init);
 static void __exit omap_mbox_exit(void)
 {
-        destroy_workqueue(mboxd);
        class_unregister(&omap_mbox_class);
 }
 module_exit(omap_mbox_exit);
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 0c8612fd8312..5587acf0eb2c 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -27,13 +27,17 @@
 #include <plat/dma.h>
 #include <plat/mcbsp.h>
+#include <plat/omap_device.h>
+#include <linux/pm_runtime.h>
+/* XXX These "sideways" includes are a sign that something is wrong */
+#include "../mach-omap2/cm2xxx_3xxx.h"
 #include "../mach-omap2/cm-regbits-34xx.h"
 struct omap_mcbsp **mcbsp_ptr;
 int omap_mcbsp_count, omap_mcbsp_cache_size;
-void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
+static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
 {
        if (cpu_class_is_omap1()) {
                ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
@@ -47,7 +51,7 @@ void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
        }
 }
-int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
+static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
 {
        if (cpu_class_is_omap1()) {
                return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
@@ -62,12 +66,12 @@ int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
 }
 #ifdef CONFIG_ARCH_OMAP3
-void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
+static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
 {
        __raw_writel(val, mcbsp->st_data->io_base_st + reg);
 }
-int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
+static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
 {
        return __raw_readl(mcbsp->st_data->io_base_st + reg);
 }
@@ -80,9 +84,6 @@ int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
 #define MCBSP_READ_CACHE(mcbsp, reg) \
                omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
-#define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
-#define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
 #define MCBSP_ST_READ(mcbsp, reg) \
                        omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
@@ -228,26 +229,96 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 }
 EXPORT_SYMBOL(omap_mcbsp_config);
+/**
+ * omap_mcbsp_dma_params - returns the dma channel number
+ * @id - mcbsp id
+ * @stream - indicates the direction of data flow (rx or tx)
+ *
+ * Returns the dma channel number for the rx channel or tx channel
+ * based on the value of @stream for the requested mcbsp given by @id
+ */
+int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream)
+{
+        struct omap_mcbsp *mcbsp;
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+        if (stream)
+                return mcbsp->dma_rx_sync;
+        else
+                return mcbsp->dma_tx_sync;
+}
+EXPORT_SYMBOL(omap_mcbsp_dma_ch_params);
+/**
+ * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
+ * @id - mcbsp id
+ * @stream - indicates the direction of data flow (rx or tx)
+ *
+ * Returns the address of mcbsp data transmit register or data receive register
+ * to be used by DMA for transferring/receiving data based on the value of
+ * @stream for the requested mcbsp given by @id
+ */
+int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
+{
+        struct omap_mcbsp *mcbsp;
+        int data_reg;
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+        data_reg = mcbsp->phys_dma_base;
+        if (mcbsp->mcbsp_config_type < MCBSP_CONFIG_TYPE2) {
+                if (stream)
+                        data_reg += OMAP_MCBSP_REG_DRR1;
+                else
+                        data_reg += OMAP_MCBSP_REG_DXR1;
+        } else {
+                if (stream)
+                        data_reg += OMAP_MCBSP_REG_DRR;
+                else
+                        data_reg += OMAP_MCBSP_REG_DXR;
+        }
+        return data_reg;
+}
+EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
 #ifdef CONFIG_ARCH_OMAP3
+static struct omap_device *find_omap_device_by_dev(struct device *dev)
+{
+        struct platform_device *pdev = container_of(dev,
+                                        struct platform_device, dev);
+        return container_of(pdev, struct omap_device, pdev);
+}
 static void omap_st_on(struct omap_mcbsp *mcbsp)
 {
        unsigned int w;
+        struct omap_device *od;
+        od = find_omap_device_by_dev(mcbsp->dev);
        /*
         * Sidetone uses McBSP ICLK - which must not idle when sidetones
         * are enabled or sidetones start sounding ugly.
         */
-        w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
+        w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
        w &= ~(1 << (mcbsp->id - 2));
-        cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
        /* Enable McBSP Sidetone */
        w = MCBSP_READ(mcbsp, SSELCR);
        MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
-        w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
-        MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
        /* Enable Sidetone from Sidetone Core */
        w = MCBSP_ST_READ(mcbsp, SSELCR);
        MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
@@ -256,27 +327,27 @@ static void omap_st_on(struct omap_mcbsp *mcbsp)
 static void omap_st_off(struct omap_mcbsp *mcbsp)
 {
        unsigned int w;
+        struct omap_device *od;
+        od = find_omap_device_by_dev(mcbsp->dev);
        w = MCBSP_ST_READ(mcbsp, SSELCR);
        MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
-        w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
-        MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
        w = MCBSP_READ(mcbsp, SSELCR);
        MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
-        w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
+        w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
        w |= 1 << (mcbsp->id - 2);
-        cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
 }
 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
 {
        u16 val, i;
+        struct omap_device *od;
-        val = MCBSP_ST_READ(mcbsp, SYSCONFIG);
+        od = find_omap_device_by_dev(mcbsp->dev);
-        MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE));
        val = MCBSP_ST_READ(mcbsp, SSELCR);
@@ -304,9 +375,9 @@ static void omap_st_chgain(struct omap_mcbsp *mcbsp)
 {
        u16 w;
        struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
+        struct omap_device *od;
-        w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
+        od = find_omap_device_by_dev(mcbsp->dev);
-        MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
        w = MCBSP_ST_READ(mcbsp, SSELCR);
@@ -649,48 +720,33 @@ EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
 {
+        struct omap_device *od;
+        od = find_omap_device_by_dev(mcbsp->dev);
        /*
         * Enable wakup behavior, smart idle and all wakeups
         * REVISIT: some wakeups may be unnecessary
         */
        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                u16 syscon;
+                MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
-                syscon = MCBSP_READ(mcbsp, SYSCON);
-                syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
-                if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
-                        syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
-                                        CLOCKACTIVITY(0x02));
-                        MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
-                } else {
-                        syscon |= SIDLEMODE(0x01);
-                }
-                MCBSP_WRITE(mcbsp, SYSCON, syscon);
        }
 }
 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
 {
+        struct omap_device *od;
+        od = find_omap_device_by_dev(mcbsp->dev);
        /*
         * Disable wakup behavior, smart idle and all wakeups
         */
        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                u16 syscon;
-                syscon = MCBSP_READ(mcbsp, SYSCON);
-                syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
                /*
                 * HW bug workaround - If no_idle mode is taken, we need to
                 * go to smart_idle before going to always_idle, or the
                 * device will not hit retention anymore.
                 */
-                syscon |= SIDLEMODE(0x02);
-                MCBSP_WRITE(mcbsp, SYSCON, syscon);
-                syscon &= ~(SIDLEMODE(0x03));
-                MCBSP_WRITE(mcbsp, SYSCON, syscon);
                MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
        }
@@ -758,15 +814,14 @@ int omap_mcbsp_request(unsigned int id)
                goto err_kfree;
        }
-        mcbsp->free = 0;
+        mcbsp->free = false;
        mcbsp->reg_cache = reg_cache;
        spin_unlock(&mcbsp->lock);
        if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
                mcbsp->pdata->ops->request(id);
-        clk_enable(mcbsp->iclk);
+        pm_runtime_get_sync(mcbsp->dev);
-        clk_enable(mcbsp->fclk);
        /* Do procedure specific to omap34xx arch, if applicable */
        omap34xx_mcbsp_request(mcbsp);
@@ -814,11 +869,10 @@ err_clk_disable:
        /* Do procedure specific to omap34xx arch, if applicable */
        omap34xx_mcbsp_free(mcbsp);
-        clk_disable(mcbsp->fclk);
+        pm_runtime_put_sync(mcbsp->dev);
-        clk_disable(mcbsp->iclk);
        spin_lock(&mcbsp->lock);
-        mcbsp->free = 1;
+        mcbsp->free = true;
        mcbsp->reg_cache = NULL;
 err_kfree:
        spin_unlock(&mcbsp->lock);
@@ -845,8 +899,7 @@ void omap_mcbsp_free(unsigned int id)
        /* Do procedure specific to omap34xx arch, if applicable */
        omap34xx_mcbsp_free(mcbsp);
-        clk_disable(mcbsp->fclk);
+        pm_runtime_put_sync(mcbsp->dev);
-        clk_disable(mcbsp->iclk);
        if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
                /* Free IRQs */
@@ -861,7 +914,7 @@ void omap_mcbsp_free(unsigned int id)
        if (mcbsp->free)
                dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
        else
-                mcbsp->free = 1;
+                mcbsp->free = true;
        mcbsp->reg_cache = NULL;
        spin_unlock(&mcbsp->lock);
@@ -878,7 +931,7 @@ EXPORT_SYMBOL(omap_mcbsp_free);
 void omap_mcbsp_start(unsigned int id, int tx, int rx)
 {
        struct omap_mcbsp *mcbsp;
-        int idle;
+        int enable_srg = 0;
        u16 w;
        if (!omap_mcbsp_check_valid_id(id)) {
@@ -893,10 +946,13 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
        mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
        mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
-        idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
+        /* Only enable SRG, if McBSP is master */
-                        MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
+        w = MCBSP_READ_CACHE(mcbsp, PCR0);
+        if (w & (FSXM | FSRM | CLKXM | CLKRM))
+                enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
+                                MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
-        if (idle) {
+        if (enable_srg) {
                /* Start the sample generator */
                w = MCBSP_READ_CACHE(mcbsp, SPCR2);
                MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
@@ -919,7 +975,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
         */
        udelay(500);
-        if (idle) {
+        if (enable_srg) {
                /* Start frame sync */
                w = MCBSP_READ_CACHE(mcbsp, SPCR2);
                MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
@@ -1047,7 +1103,7 @@ int omap_mcbsp_pollread(unsigned int id, u16 *buf)
                /* resend */
                return -1;
        } else {
-                /* wait for recieve confirmation */
+                /* wait for receive confirmation */
                int attemps = 0;
                while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
                        if (attemps++ > 1000) {
@@ -1645,9 +1701,10 @@ static const struct attribute_group sidetone_attr_group = {
        .attrs = (struct attribute **)sidetone_attrs,
 };
-int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
+static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
 {
-        struct omap_mcbsp_platform_data *pdata = mcbsp->pdata;
+        struct platform_device *pdev;
+        struct resource *res;
        struct omap_mcbsp_st_data *st_data;
        int err;
@@ -1657,7 +1714,10 @@ int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
                goto err1;
        }
-        st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K);
+        pdev = container_of(mcbsp->dev, struct platform_device, dev);
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
+        st_data->io_base_st = ioremap(res->start, resource_size(res));
        if (!st_data->io_base_st) {
                err = -ENOMEM;
                goto err2;
@@ -1746,6 +1806,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
        struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
        struct omap_mcbsp *mcbsp;
        int id = pdev->id - 1;
+        struct resource *res;
        int ret = 0;
        if (!pdata) {
@@ -1771,51 +1832,82 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
        spin_lock_init(&mcbsp->lock);
        mcbsp->id = id + 1;
-        mcbsp->free = 1;
+        mcbsp->free = true;
        mcbsp->dma_tx_lch = -1;
        mcbsp->dma_rx_lch = -1;
-        mcbsp->phys_base = pdata->phys_base;
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
-        mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
+        if (!res) {
+                res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+                if (!res) {
+                        dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
+                                        "resource\n", __func__, pdev->id);
+                        ret = -ENOMEM;
+                        goto exit;
+                }
+        }
+        mcbsp->phys_base = res->start;
+        omap_mcbsp_cache_size = resource_size(res);
+        mcbsp->io_base = ioremap(res->start, resource_size(res));
        if (!mcbsp->io_base) {
                ret = -ENOMEM;
                goto err_ioremap;
        }
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
+        if (!res)
+                mcbsp->phys_dma_base = mcbsp->phys_base;
+        else
+                mcbsp->phys_dma_base = res->start;
        /* Default I/O is IRQ based */
        mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
-        mcbsp->tx_irq = pdata->tx_irq;
-        mcbsp->rx_irq = pdata->rx_irq;
-        mcbsp->dma_rx_sync = pdata->dma_rx_sync;
-        mcbsp->dma_tx_sync = pdata->dma_tx_sync;
-        mcbsp->iclk = clk_get(&pdev->dev, "ick");
+        mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
-        if (IS_ERR(mcbsp->iclk)) {
+        mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
-                ret = PTR_ERR(mcbsp->iclk);
-                dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
+        /* From OMAP4 there will be a single irq line */
-                goto err_iclk;
+        if (mcbsp->tx_irq == -ENXIO)
+                mcbsp->tx_irq = platform_get_irq(pdev, 0);
+        res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
+        if (!res) {
+                dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
+                                        __func__, pdev->id);
+                ret = -ENODEV;
+                goto err_res;
+        }
+        mcbsp->dma_rx_sync = res->start;
+        res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
+        if (!res) {
+                dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
+                                        __func__, pdev->id);
+                ret = -ENODEV;
+                goto err_res;
        }
+        mcbsp->dma_tx_sync = res->start;
        mcbsp->fclk = clk_get(&pdev->dev, "fck");
        if (IS_ERR(mcbsp->fclk)) {
                ret = PTR_ERR(mcbsp->fclk);
                dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
-                goto err_fclk;
+                goto err_res;
        }
        mcbsp->pdata = pdata;
        mcbsp->dev = &pdev->dev;
        mcbsp_ptr[id] = mcbsp;
+        mcbsp->mcbsp_config_type = pdata->mcbsp_config_type;
        platform_set_drvdata(pdev, mcbsp);
+        pm_runtime_enable(mcbsp->dev);
        /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
        omap34xx_device_init(mcbsp);
        return 0;
-err_fclk:
+err_res:
-        clk_put(mcbsp->iclk);
-err_iclk:
        iounmap(mcbsp->io_base);
 err_ioremap:
        kfree(mcbsp);
@@ -1836,17 +1928,10 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
                omap34xx_device_exit(mcbsp);
-                clk_disable(mcbsp->fclk);
-                clk_disable(mcbsp->iclk);
                clk_put(mcbsp->fclk);
-                clk_put(mcbsp->iclk);
                iounmap(mcbsp->io_base);
+                kfree(mcbsp);
-                mcbsp->fclk = NULL;
-                mcbsp->iclk = NULL;
-                mcbsp->free = 0;
-                mcbsp->dev = NULL;
        }
        return 0;
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c
index e129ce80c53b..b0471bb2d47d 100644
--- a/arch/arm/plat-omap/omap-pm-noop.c
+++ b/arch/arm/plat-omap/omap-pm-noop.c
@@ -20,15 +20,14 @@
 #include <linux/init.h>
 #include <linux/cpufreq.h>
 #include <linux/device.h>
+#include <linux/platform_device.h>
 /* Interface documentation is in mach/omap-pm.h */
 #include <plat/omap-pm.h>
+#include <plat/omap_device.h>
-#include <plat/powerdomain.h>
+static bool off_mode_enabled;
+static u32 dummy_context_loss_counter;
-struct omap_opp *dsp_opps;
-struct omap_opp *mpu_opps;
-struct omap_opp *l3_opps;
 /*
 * Device-driver-originated constraints (via board-*.c files)
@@ -284,37 +283,70 @@ unsigned long omap_pm_cpu_get_freq(void)
        return 0;
 }
+/**
+ * omap_pm_enable_off_mode - notify OMAP PM that off-mode is enabled
+ *
+ * Intended for use only by OMAP PM core code to notify this layer
+ * that off mode has been enabled.
+ */
+void omap_pm_enable_off_mode(void)
+{
+        off_mode_enabled = true;
+}
+/**
+ * omap_pm_disable_off_mode - notify OMAP PM that off-mode is disabled
+ *
+ * Intended for use only by OMAP PM core code to notify this layer
+ * that off mode has been disabled.
+ */
+void omap_pm_disable_off_mode(void)
+{
+        off_mode_enabled = false;
+}
 /*
 * Device context loss tracking
 */
-int omap_pm_get_dev_context_loss_count(struct device *dev)
+#ifdef CONFIG_ARCH_OMAP2PLUS
+u32 omap_pm_get_dev_context_loss_count(struct device *dev)
 {
-        if (!dev) {
+        struct platform_device *pdev = to_platform_device(dev);
-                WARN_ON(1);
+        u32 count;
-                return -EINVAL;
-        };
+        if (WARN_ON(!dev))
+                return 0;
+        if (dev->parent == &omap_device_parent) {
+                count = omap_device_get_context_loss_count(pdev);
+        } else {
+                WARN_ONCE(off_mode_enabled, "omap_pm: using dummy context loss counter; device %s should be converted to omap_device",
+                          dev_name(dev));
+                if (off_mode_enabled)
+                        dummy_context_loss_counter++;
+                count = dummy_context_loss_counter;
+        }
-        pr_debug("OMAP PM: returning context loss count for dev %s\n",
+        pr_debug("OMAP PM: context loss count for dev %s = %d\n",
-                 dev_name(dev));
+                 dev_name(dev), count);
-        /*
+        return count;
-         * Map the device to the powerdomain.  Return the powerdomain
+}
-         * off counter.
-         */
-        return 0;
+#else
+u32 omap_pm_get_dev_context_loss_count(struct device *dev)
+{
+        return dummy_context_loss_counter;
 }
+#endif
 /* Should be called before clk framework init */
-int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
+int __init omap_pm_if_early_init(void)
-                                 struct omap_opp *dsp_opp_table,
-                                 struct omap_opp *l3_opp_table)
 {
-        mpu_opps = mpu_opp_table;
-        dsp_opps = dsp_opp_table;
-        l3_opps = l3_opp_table;
        return 0;
 }
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index d2b160942ccc..49fc0df0c21f 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -82,20 +82,18 @@
 #include <linux/slab.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/pm_runtime.h>
 #include <plat/omap_device.h>
 #include <plat/omap_hwmod.h>
+#include <plat/clock.h>
 /* These parameters are passed to _omap_device_{de,}activate() */
 #define USE_WAKEUP_LAT                  0
 #define IGNORE_WAKEUP_LAT               1
-/*
- * OMAP_DEVICE_MAGIC: used to determine whether a struct omap_device
- * obtained via container_of() is in fact a struct omap_device
- */
-#define OMAP_DEVICE_MAGIC                0xf00dcafe
 /* Private functions */
 /**
@@ -243,10 +241,90 @@ static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
        return container_of(pdev, struct omap_device, pdev);
 }
+/**
+ * _add_optional_clock_clkdev - Add clkdev entry for hwmod optional clocks
+ * @od: struct omap_device *od
+ *
+ * For every optional clock present per hwmod per omap_device, this function
+ * adds an entry in the clkdev table of the form <dev-id=dev_name, con-id=role>
+ * if it does not exist already.
+ *
+ * The function is called from inside omap_device_build_ss(), after
+ * omap_device_register.
+ *
+ * This allows drivers to get a pointer to its optional clocks based on its role
+ * by calling clk_get(<dev*>, <role>).
+ *
+ * No return value.
+ */
+static void _add_optional_clock_clkdev(struct omap_device *od,
+                                      struct omap_hwmod *oh)
+{
+        int i;
+        for (i = 0; i < oh->opt_clks_cnt; i++) {
+                struct omap_hwmod_opt_clk *oc;
+                struct clk *r;
+                struct clk_lookup *l;
+                oc = &oh->opt_clks[i];
+                if (!oc->_clk)
+                        continue;
+                r = clk_get_sys(dev_name(&od->pdev.dev), oc->role);
+                if (!IS_ERR(r))
+                        continue; /* clkdev entry exists */
+                r = omap_clk_get_by_name((char *)oc->clk);
+                if (IS_ERR(r)) {
+                        pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n",
+                               dev_name(&od->pdev.dev), oc->clk);
+                        continue;
+                }
+                l = clkdev_alloc(r, oc->role, dev_name(&od->pdev.dev));
+                if (!l) {
+                        pr_err("omap_device: %s: clkdev_alloc for %s failed\n",
+                               dev_name(&od->pdev.dev), oc->role);
+                        return;
+                }
+                clkdev_add(l);
+        }
+}
 /* Public functions for use by core code */
 /**
+ * omap_device_get_context_loss_count - get lost context count
+ * @od: struct omap_device *
+ *
+ * Using the primary hwmod, query the context loss count for this
+ * device.
+ *
+ * Callers should consider context for this device lost any time this
+ * function returns a value different than the value the caller got
+ * the last time it called this function.
+ *
+ * If any hwmods exist for the omap_device assoiated with @pdev,
+ * return the context loss counter for that hwmod, otherwise return
+ * zero.
+ */
+u32 omap_device_get_context_loss_count(struct platform_device *pdev)
+{
+        struct omap_device *od;
+        u32 ret = 0;
+        od = _find_by_pdev(pdev);
+        if (od->hwmods_cnt)
+                ret = omap_hwmod_get_context_loss_count(od->hwmods[0]);
+        return ret;
+}
+/**
 * omap_device_count_resources - count number of struct resource entries needed
 * @od: struct omap_device *
 *
@@ -257,12 +335,11 @@ static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
 */
 int omap_device_count_resources(struct omap_device *od)
 {
-        struct omap_hwmod *oh;
        int c = 0;
        int i;
-        for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
+        for (i = 0; i < od->hwmods_cnt; i++)
-                c += omap_hwmod_count_resources(oh);
+                c += omap_hwmod_count_resources(od->hwmods[i]);
        pr_debug("omap_device: %s: counted %d total resources across %d "
                 "hwmods\n", od->pdev.name, c, od->hwmods_cnt);
@@ -289,12 +366,11 @@ int omap_device_count_resources(struct omap_device *od)
 */
 int omap_device_fill_resources(struct omap_device *od, struct resource *res)
 {
-        struct omap_hwmod *oh;
        int c = 0;
        int i, r;
-        for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) {
+        for (i = 0; i < od->hwmods_cnt; i++) {
-                r = omap_hwmod_fill_resources(oh, res);
+                r = omap_hwmod_fill_resources(od->hwmods[i], res);
                res += r;
                c += r;
        }
@@ -414,15 +490,15 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
        od->pm_lats = pm_lats;
        od->pm_lats_cnt = pm_lats_cnt;
-        od->magic = OMAP_DEVICE_MAGIC;
        if (is_early_device)
                ret = omap_early_device_register(od);
        else
                ret = omap_device_register(od);
-        for (i = 0; i < oh_cnt; i++)
+        for (i = 0; i < oh_cnt; i++) {
                hwmods[i]->od = od;
+                _add_optional_clock_clkdev(od, hwmods[i]);
+        }
        if (ret)
                goto odbs_exit4;
@@ -461,6 +537,42 @@ int omap_early_device_register(struct omap_device *od)
        return 0;
 }
+static int _od_runtime_suspend(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        int ret;
+        ret = pm_generic_runtime_suspend(dev);
+        if (!ret)
+                omap_device_idle(pdev);
+        return ret;
+}
+static int _od_runtime_idle(struct device *dev)
+{
+        return pm_generic_runtime_idle(dev);
+}
+static int _od_runtime_resume(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        omap_device_enable(pdev);
+        return pm_generic_runtime_resume(dev);
+}
+static struct dev_power_domain omap_device_power_domain = {
+        .ops = {
+                .runtime_suspend = _od_runtime_suspend,
+                .runtime_idle = _od_runtime_idle,
+                .runtime_resume = _od_runtime_resume,
+                USE_PLATFORM_PM_SLEEP_OPS
+        }
+};
 /**
 * omap_device_register - register an omap_device with one omap_hwmod
 * @od: struct omap_device * to register
@@ -473,6 +585,8 @@ int omap_device_register(struct omap_device *od)
 {
        pr_debug("omap_device: %s: registering\n", od->pdev.name);
+        od->pdev.dev.parent = &omap_device_parent;
+        od->pdev.dev.pwr_domain = &omap_device_power_domain;
        return platform_device_register(&od->pdev);
 }
@@ -566,7 +680,6 @@ int omap_device_shutdown(struct platform_device *pdev)
 {
        int ret, i;
        struct omap_device *od;
-        struct omap_hwmod *oh;
        od = _find_by_pdev(pdev);
@@ -579,8 +692,8 @@ int omap_device_shutdown(struct platform_device *pdev)
        ret = _omap_device_deactivate(od, IGNORE_WAKEUP_LAT);
-        for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
+        for (i = 0; i < od->hwmods_cnt; i++)
-                omap_hwmod_shutdown(oh);
+                omap_hwmod_shutdown(od->hwmods[i]);
        od->_state = OMAP_DEVICE_STATE_SHUTDOWN;
@@ -627,18 +740,6 @@ int omap_device_align_pm_lat(struct platform_device *pdev,
 }
 /**
- * omap_device_is_valid - Check if pointer is a valid omap_device
- * @od: struct omap_device *
- *
- * Return whether struct omap_device pointer @od points to a valid
- * omap_device.
- */
-bool omap_device_is_valid(struct omap_device *od)
-{
-        return (od && od->magic == OMAP_DEVICE_MAGIC);
-}
-/**
 * omap_device_get_pwrdm - return the powerdomain * associated with @od
 * @od: struct omap_device *
 *
@@ -692,11 +793,10 @@ void __iomem *omap_device_get_rt_va(struct omap_device *od)
 */
 int omap_device_enable_hwmods(struct omap_device *od)
 {
-        struct omap_hwmod *oh;
        int i;
-        for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
+        for (i = 0; i < od->hwmods_cnt; i++)
-                omap_hwmod_enable(oh);
+                omap_hwmod_enable(od->hwmods[i]);
        /* XXX pass along return value here? */
        return 0;
@@ -710,11 +810,10 @@ int omap_device_enable_hwmods(struct omap_device *od)
 */
 int omap_device_idle_hwmods(struct omap_device *od)
 {
-        struct omap_hwmod *oh;
        int i;
-        for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
+        for (i = 0; i < od->hwmods_cnt; i++)
-                omap_hwmod_idle(oh);
+                omap_hwmod_idle(od->hwmods[i]);
        /* XXX pass along return value here? */
        return 0;
@@ -729,11 +828,10 @@ int omap_device_idle_hwmods(struct omap_device *od)
 */
 int omap_device_disable_clocks(struct omap_device *od)
 {
-        struct omap_hwmod *oh;
        int i;
-        for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
+        for (i = 0; i < od->hwmods_cnt; i++)
-                omap_hwmod_disable_clocks(oh);
+                omap_hwmod_disable_clocks(od->hwmods[i]);
        /* XXX pass along return value here? */
        return 0;
@@ -748,12 +846,22 @@ int omap_device_disable_clocks(struct omap_device *od)
 */
 int omap_device_enable_clocks(struct omap_device *od)
 {
-        struct omap_hwmod *oh;
        int i;
-        for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++)
+        for (i = 0; i < od->hwmods_cnt; i++)
-                omap_hwmod_enable_clocks(oh);
+                omap_hwmod_enable_clocks(od->hwmods[i]);
        /* XXX pass along return value here? */
        return 0;
 }
+struct device omap_device_parent = {
+        .init_name      = "omap",
+        .parent         = &platform_bus,
+};
+static int __init omap_device_init(void)
+{
+        return device_register(&omap_device_parent);
+}
+core_initcall(omap_device_init);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 10b3b4c63372..6af3d0b1f8d0 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -19,6 +19,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/omapfb.h>
 #include <asm/tlb.h>
 #include <asm/cacheflush.h>
@@ -30,30 +31,28 @@
 #include <plat/cpu.h>
 #include <plat/vram.h>
-#include <plat/control.h>
+#include "sram.h"
+#include "fb.h"
+/* XXX These "sideways" includes are a sign that something is wrong */
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-# include "../mach-omap2/prm.h"
+# include "../mach-omap2/prm2xxx_3xxx.h"
-# include "../mach-omap2/cm.h"
 # include "../mach-omap2/sdrc.h"
 #endif
 #define OMAP1_SRAM_PA           0x20000000
 #define OMAP1_SRAM_VA           VMALLOC_END
-#define OMAP2_SRAM_PA           0x40200000
+#define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
-#define OMAP2_SRAM_PUB_PA       0x4020f800
 #define OMAP2_SRAM_VA           0xfe400000
 #define OMAP2_SRAM_PUB_VA       (OMAP2_SRAM_VA + 0x800)
-#define OMAP3_SRAM_PA           0x40200000
 #define OMAP3_SRAM_VA           0xfe400000
-#define OMAP3_SRAM_PUB_PA       0x40208000
+#define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
 #define OMAP3_SRAM_PUB_VA       (OMAP3_SRAM_VA + 0x8000)
-#define OMAP4_SRAM_PA           0x40300000
 #define OMAP4_SRAM_VA           0xfe400000
 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
 #define OMAP4_SRAM_PUB_VA       (OMAP4_SRAM_VA + 0x4000)
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_ARCH_OMAP2PLUS)
 #define SRAM_BOOTLOADER_SZ      0x00
 #else
 #define SRAM_BOOTLOADER_SZ      0x80
@@ -68,7 +67,6 @@
 #define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
 #define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
 #define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
-#define OMAP34XX_VA_CONTROL_STAT        OMAP2_L4_IO_ADDRESS(0x480022F0)
 #define GP_DEVICE               0x300
@@ -79,12 +77,6 @@ static unsigned long omap_sram_base;
 static unsigned long omap_sram_size;
 static unsigned long omap_sram_ceil;
-extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
-                                         unsigned long sram_vstart,
-                                         unsigned long sram_size,
-                                         unsigned long pstart_avail,
-                                         unsigned long size_avail);
 /*
 * Depending on the target RAMFS firewall setup, the public usable amount of
 * SRAM varies.  The default accessible size for all device types is 2k. A GP
@@ -93,16 +85,7 @@ extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
 */
 static int is_sram_locked(void)
 {
-        int type = 0;
+        if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
-        if (cpu_is_omap44xx())
-                /* Not yet supported */
-                return 0;
-        if (cpu_is_omap242x())
-                type = omap_rev() & OMAP2_DEVICETYPE_MASK;
-        if (type == GP_DEVICE) {
                /* RAMFW: R/W access to all initiators for all qualifier sets */
                if (cpu_is_omap242x()) {
                        __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
@@ -127,7 +110,7 @@ static int is_sram_locked(void)
 * to secure SRAM will hang the system. Also the SRAM is not
 * yet mapped at this point.
 */
-void __init omap_detect_sram(void)
+static void __init omap_detect_sram(void)
 {
        unsigned long reserved;
@@ -181,9 +164,9 @@ void __init omap_detect_sram(void)
                     cpu_is_omap1710())
                        omap_sram_size = 0x4000;        /* 16K */
                else if (cpu_is_omap1611())
-                        omap_sram_size = 0x3e800;       /* 250K */
+                        omap_sram_size = SZ_256K;
                else {
-                        printk(KERN_ERR "Could not detect SRAM size\n");
+                        pr_err("Could not detect SRAM size\n");
                        omap_sram_size = 0x4000;
                }
        }
@@ -213,7 +196,7 @@ static struct map_desc omap_sram_io_desc[] __initdata = {
 /*
 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
 */
-void __init omap_map_sram(void)
+static void __init omap_map_sram(void)
 {
        unsigned long base;
@@ -238,10 +221,10 @@ void __init omap_map_sram(void)
        omap_sram_io_desc[0].length = ROUND_DOWN(omap_sram_size, PAGE_SIZE);
        iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
-        printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
+        pr_info("SRAM: Mapped pa 0x%08llx to va 0x%08lx size: 0x%lx\n",
-        __pfn_to_phys(omap_sram_io_desc[0].pfn),
+                (long long) __pfn_to_phys(omap_sram_io_desc[0].pfn),
-        omap_sram_io_desc[0].virtual,
+                omap_sram_io_desc[0].virtual,
-               omap_sram_io_desc[0].length);
+                omap_sram_io_desc[0].length);
        /*
         * Normally devicemaps_init() would flush caches and tlb after
@@ -259,18 +242,22 @@ void __init omap_map_sram(void)
               omap_sram_size - SRAM_BOOTLOADER_SZ);
 }
-void * omap_sram_push(void * start, unsigned long size)
+/*
+ * Memory allocator for SRAM: calculates the new ceiling address
+ * for pushing a function using the fncpy API.
+ *
+ * Note that fncpy requires the returned address to be aligned
+ * to an 8-byte boundary.
+ */
+void *omap_sram_push_address(unsigned long size)
 {
        if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) {
-                printk(KERN_ERR "Not enough space in SRAM\n");
+                pr_err("Not enough space in SRAM\n");
                return NULL;
        }
        omap_sram_ceil -= size;
-        omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
+        omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, FNCPY_ALIGN);
-        memcpy((void *)omap_sram_ceil, start, size);
-        flush_icache_range((unsigned long)omap_sram_ceil,
-                (unsigned long)(omap_sram_ceil + size));
        return (void *)omap_sram_ceil;
 }
@@ -285,7 +272,7 @@ void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
        _omap_sram_reprogram_clock(dpllctl, ckctl);
 }
-int __init omap1_sram_init(void)
+static int __init omap1_sram_init(void)
 {
        _omap_sram_reprogram_clock =
                        omap_sram_push(omap1_sram_reprogram_clock,
@@ -329,8 +316,8 @@ u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 }
 #endif
-#ifdef CONFIG_ARCH_OMAP2420
+#ifdef CONFIG_SOC_OMAP2420
-int __init omap242x_sram_init(void)
+static int __init omap242x_sram_init(void)
 {
        _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
                                        omap242x_sram_ddr_init_sz);
@@ -350,8 +337,8 @@ static inline int omap242x_sram_init(void)
 }
 #endif
-#ifdef CONFIG_ARCH_OMAP2430
+#ifdef CONFIG_SOC_OMAP2430
-int __init omap243x_sram_init(void)
+static int __init omap243x_sram_init(void)
 {
        _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
                                        omap243x_sram_ddr_init_sz);
@@ -407,7 +394,7 @@ void omap3_sram_restore_context(void)
 }
 #endif /* CONFIG_PM */
-int __init omap34xx_sram_init(void)
+static int __init omap34xx_sram_init(void)
 {
        _omap3_sram_configure_core_dpll =
                omap_sram_push(omap3_sram_configure_core_dpll,
@@ -422,20 +409,6 @@ static inline int omap34xx_sram_init(void)
 }
 #endif
-#ifdef CONFIG_ARCH_OMAP4
-int __init omap44xx_sram_init(void)
-{
-        printk(KERN_ERR "FIXME: %s not implemented\n", __func__);
-        return -ENODEV;
-}
-#else
-static inline int omap44xx_sram_init(void)
-{
-        return 0;
-}
-#endif
 int __init omap_sram_init(void)
 {
        omap_detect_sram();
@@ -449,8 +422,6 @@ int __init omap_sram_init(void)
                omap243x_sram_init();
        else if (cpu_is_omap34xx())
                omap34xx_sram_init();
-        else if (cpu_is_omap44xx())
-                omap44xx_sram_init();
        return 0;
 }
diff --git a/arch/arm/plat-omap/sram.h b/arch/arm/plat-omap/sram.h
new file mode 100644
index 000000000000..29b43ef97f20
--- /dev/null
+++ b/arch/arm/plat-omap/sram.h
@@ -0,0 +1,6 @@
+#ifndef __PLAT_OMAP_SRAM_H__
+#define __PLAT_OMAP_SRAM_H__
+extern int __init omap_sram_init(void);
+#endif /* __PLAT_OMAP_SRAM_H__ */
author	Glenn Elliott <gelliott@cs.unc.edu>	2012-03-04 19:47:13 -0500
committer	Glenn Elliott <gelliott@cs.unc.edu>	2012-03-04 19:47:13 -0500
commit	c71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
tree	ecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /arch/arm/plat-omap
parent	ea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent	6a00f206debf8a5c8899055726ad127dbeeed098 (diff)