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authorTony Lindgren <tony@atomide.com>2008-07-03 05:24:38 -0400
committerTony Lindgren <tony@atomide.com>2008-07-03 05:24:38 -0400
commitc2d43e39c7c303db53facd0bea44b66f263e3f35 (patch)
tree10b0b5a5dde1176f925b5aedcda32963f7c80029 /arch/arm/plat-omap/sram.c
parent373a67021d00a8b8c86bfa19f8914377de05b4bd (diff)
ARM: OMAP: SRAM: Split sram24xx.S into sram242x.S and sram243x.S
Split sram24xx.S into sram242x.S and sram243x.S Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap/sram.c')
-rw-r--r--arch/arm/plat-omap/sram.c211
1 files changed, 176 insertions, 35 deletions
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 1f23f0459e5f..554ee58e1294 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -10,6 +10,7 @@
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13#undef DEBUG
13 14
14#include <linux/module.h> 15#include <linux/module.h>
15#include <linux/kernel.h> 16#include <linux/kernel.h>
@@ -24,25 +25,43 @@
24#include <asm/arch/sram.h> 25#include <asm/arch/sram.h>
25#include <asm/arch/board.h> 26#include <asm/arch/board.h>
26 27
28#include <asm/arch/control.h>
29
30#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
31# include "../mach-omap2/prm.h"
32# include "../mach-omap2/cm.h"
33# include "../mach-omap2/sdrc.h"
34#endif
35
27#define OMAP1_SRAM_PA 0x20000000 36#define OMAP1_SRAM_PA 0x20000000
28#define OMAP1_SRAM_VA 0xd0000000 37#define OMAP1_SRAM_VA VMALLOC_END
29#define OMAP2_SRAM_PA 0x40200000 38#define OMAP2_SRAM_PA 0x40200000
30#define OMAP2_SRAM_PUB_PA 0x4020f800 39#define OMAP2_SRAM_PUB_PA 0x4020f800
31#define OMAP2_SRAM_VA 0xd0000000 40#define OMAP2_SRAM_VA VMALLOC_END
32#define OMAP2_SRAM_PUB_VA 0xd0000800 41#define OMAP2_SRAM_PUB_VA (VMALLOC_END + 0x800)
33 42#define OMAP3_SRAM_PA 0x40200000
34#if defined(CONFIG_ARCH_OMAP24XX) 43#define OMAP3_SRAM_VA 0xd7000000
44#define OMAP3_SRAM_PUB_PA 0x40208000
45#define OMAP3_SRAM_PUB_VA 0xd7008000
46
47#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
35#define SRAM_BOOTLOADER_SZ 0x00 48#define SRAM_BOOTLOADER_SZ 0x00
36#else 49#else
37#define SRAM_BOOTLOADER_SZ 0x80 50#define SRAM_BOOTLOADER_SZ 0x80
38#endif 51#endif
39 52
40#define VA_REQINFOPERM0 IO_ADDRESS(0x68005048) 53#define OMAP24XX_VA_REQINFOPERM0 IO_ADDRESS(0x68005048)
41#define VA_READPERM0 IO_ADDRESS(0x68005050) 54#define OMAP24XX_VA_READPERM0 IO_ADDRESS(0x68005050)
42#define VA_WRITEPERM0 IO_ADDRESS(0x68005058) 55#define OMAP24XX_VA_WRITEPERM0 IO_ADDRESS(0x68005058)
43#define VA_CONTROL_STAT IO_ADDRESS(0x480002F8) 56
57#define OMAP34XX_VA_REQINFOPERM0 IO_ADDRESS(0x68012848)
58#define OMAP34XX_VA_READPERM0 IO_ADDRESS(0x68012850)
59#define OMAP34XX_VA_WRITEPERM0 IO_ADDRESS(0x68012858)
60#define OMAP34XX_VA_ADDR_MATCH2 IO_ADDRESS(0x68012880)
61#define OMAP34XX_VA_SMS_RG_ATT0 IO_ADDRESS(0x6C000048)
62#define OMAP34XX_VA_CONTROL_STAT IO_ADDRESS(0x480022F0)
63
44#define GP_DEVICE 0x300 64#define GP_DEVICE 0x300
45#define TYPE_MASK 0x700
46 65
47#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) 66#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
48 67
@@ -68,14 +87,21 @@ static int is_sram_locked(void)
68 int type = 0; 87 int type = 0;
69 88
70 if (cpu_is_omap242x()) 89 if (cpu_is_omap242x())
71 type = __raw_readl(VA_CONTROL_STAT) & TYPE_MASK; 90 type = system_rev & OMAP2_DEVICETYPE_MASK;
72 91
73 if (type == GP_DEVICE) { 92 if (type == GP_DEVICE) {
74 /* RAMFW: R/W access to all initiators for all qualifier sets */ 93 /* RAMFW: R/W access to all initiators for all qualifier sets */
75 if (cpu_is_omap242x()) { 94 if (cpu_is_omap242x()) {
76 __raw_writel(0xFF, VA_REQINFOPERM0); /* all q-vects */ 95 __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
77 __raw_writel(0xCFDE, VA_READPERM0); /* all i-read */ 96 __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
78 __raw_writel(0xCFDE, VA_WRITEPERM0); /* all i-write */ 97 __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
98 }
99 if (cpu_is_omap34xx()) {
100 __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
101 __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
102 __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
103 __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
104 __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
79 } 105 }
80 return 0; 106 return 0;
81 } else 107 } else
@@ -92,18 +118,30 @@ void __init omap_detect_sram(void)
92{ 118{
93 unsigned long reserved; 119 unsigned long reserved;
94 120
95 if (cpu_is_omap24xx()) { 121 if (cpu_class_is_omap2()) {
96 if (is_sram_locked()) { 122 if (is_sram_locked()) {
97 omap_sram_base = OMAP2_SRAM_PUB_VA; 123 if (cpu_is_omap34xx()) {
98 omap_sram_start = OMAP2_SRAM_PUB_PA; 124 omap_sram_base = OMAP3_SRAM_PUB_VA;
99 omap_sram_size = 0x800; /* 2K */ 125 omap_sram_start = OMAP3_SRAM_PUB_PA;
126 omap_sram_size = 0x8000; /* 32K */
127 } else {
128 omap_sram_base = OMAP2_SRAM_PUB_VA;
129 omap_sram_start = OMAP2_SRAM_PUB_PA;
130 omap_sram_size = 0x800; /* 2K */
131 }
100 } else { 132 } else {
101 omap_sram_base = OMAP2_SRAM_VA; 133 if (cpu_is_omap34xx()) {
102 omap_sram_start = OMAP2_SRAM_PA; 134 omap_sram_base = OMAP3_SRAM_VA;
103 if (cpu_is_omap242x()) 135 omap_sram_start = OMAP3_SRAM_PA;
104 omap_sram_size = 0xa0000; /* 640K */
105 else if (cpu_is_omap243x())
106 omap_sram_size = 0x10000; /* 64K */ 136 omap_sram_size = 0x10000; /* 64K */
137 } else {
138 omap_sram_base = OMAP2_SRAM_VA;
139 omap_sram_start = OMAP2_SRAM_PA;
140 if (cpu_is_omap242x())
141 omap_sram_size = 0xa0000; /* 640K */
142 else if (cpu_is_omap243x())
143 omap_sram_size = 0x10000; /* 64K */
144 }
107 } 145 }
108 } else { 146 } else {
109 omap_sram_base = OMAP1_SRAM_VA; 147 omap_sram_base = OMAP1_SRAM_VA;
@@ -157,6 +195,13 @@ void __init omap_map_sram(void)
157 omap_sram_io_desc[0].pfn = __phys_to_pfn(base); 195 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
158 } 196 }
159 197
198 if (cpu_is_omap34xx()) {
199 omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
200 base = OMAP3_SRAM_PA;
201 base = ROUND_DOWN(base, PAGE_SIZE);
202 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
203 }
204
160 omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */ 205 omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */
161 iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc)); 206 iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
162 207
@@ -191,6 +236,7 @@ void * omap_sram_push(void * start, unsigned long size)
191 omap_sram_ceil -= size; 236 omap_sram_ceil -= size;
192 omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *)); 237 omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
193 memcpy((void *)omap_sram_ceil, start, size); 238 memcpy((void *)omap_sram_ceil, start, size);
239 flush_icache_range((unsigned long)start, (unsigned long)(start + size));
194 240
195 return (void *)omap_sram_ceil; 241 return (void *)omap_sram_ceil;
196} 242}
@@ -214,8 +260,9 @@ void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
214 260
215int __init omap1_sram_init(void) 261int __init omap1_sram_init(void)
216{ 262{
217 _omap_sram_reprogram_clock = omap_sram_push(sram_reprogram_clock, 263 _omap_sram_reprogram_clock =
218 sram_reprogram_clock_sz); 264 omap_sram_push(omap1_sram_reprogram_clock,
265 omap1_sram_reprogram_clock_sz);
219 266
220 return 0; 267 return 0;
221} 268}
@@ -224,7 +271,7 @@ int __init omap1_sram_init(void)
224#define omap1_sram_init() do {} while (0) 271#define omap1_sram_init() do {} while (0)
225#endif 272#endif
226 273
227#ifdef CONFIG_ARCH_OMAP2 274#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
228 275
229static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 276static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
230 u32 base_cs, u32 force_unlock); 277 u32 base_cs, u32 force_unlock);
@@ -259,19 +306,109 @@ u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
259 306
260 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass); 307 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
261} 308}
309#endif
310
311#ifdef CONFIG_ARCH_OMAP2420
312int __init omap242x_sram_init(void)
313{
314 _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
315 omap242x_sram_ddr_init_sz);
316
317 _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
318 omap242x_sram_reprogram_sdrc_sz);
319
320 _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
321 omap242x_sram_set_prcm_sz);
322
323 return 0;
324}
325#else
326static inline int omap242x_sram_init(void)
327{
328 return 0;
329}
330#endif
331
332#ifdef CONFIG_ARCH_OMAP2430
333int __init omap243x_sram_init(void)
334{
335 _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
336 omap243x_sram_ddr_init_sz);
337
338 _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
339 omap243x_sram_reprogram_sdrc_sz);
340
341 _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
342 omap243x_sram_set_prcm_sz);
343
344 return 0;
345}
346#else
347static inline int omap243x_sram_init(void)
348{
349 return 0;
350}
351#endif
352
353#ifdef CONFIG_ARCH_OMAP3
354
355static u32 (*_omap2_sram_reprogram_gpmc)(u32 perf_level);
356u32 omap2_sram_reprogram_gpmc(u32 perf_level)
357{
358 if (!_omap2_sram_reprogram_gpmc)
359 omap_sram_error();
360
361 return _omap2_sram_reprogram_gpmc(perf_level);
362}
363
364static u32 (*_omap2_sram_configure_core_dpll)(u32 m, u32 n,
365 u32 freqsel, u32 m2);
366u32 omap2_sram_configure_core_dpll(u32 m, u32 n, u32 freqsel, u32 m2)
367{
368 if (!_omap2_sram_configure_core_dpll)
369 omap_sram_error();
370
371 return _omap2_sram_configure_core_dpll(m, n, freqsel, m2);
372}
262 373
263int __init omap2_sram_init(void) 374/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
375void restore_sram_functions(void)
264{ 376{
265 _omap2_sram_ddr_init = omap_sram_push(sram_ddr_init, sram_ddr_init_sz); 377 omap_sram_ceil = omap_sram_base + omap_sram_size;
266 378
267 _omap2_sram_reprogram_sdrc = omap_sram_push(sram_reprogram_sdrc, 379 _omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
268 sram_reprogram_sdrc_sz); 380 omap34xx_sram_reprogram_gpmc_sz);
269 _omap2_set_prcm = omap_sram_push(sram_set_prcm, sram_set_prcm_sz); 381
382 _omap2_sram_configure_core_dpll =
383 omap_sram_push(omap34xx_sram_configure_core_dpll,
384 omap34xx_sram_configure_core_dpll_sz);
385}
386
387int __init omap34xx_sram_init(void)
388{
389 _omap2_sram_ddr_init = omap_sram_push(omap34xx_sram_ddr_init,
390 omap34xx_sram_ddr_init_sz);
391
392 _omap2_sram_reprogram_sdrc = omap_sram_push(omap34xx_sram_reprogram_sdrc,
393 omap34xx_sram_reprogram_sdrc_sz);
394
395 _omap2_set_prcm = omap_sram_push(omap34xx_sram_set_prcm,
396 omap34xx_sram_set_prcm_sz);
397
398 _omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
399 omap34xx_sram_reprogram_gpmc_sz);
400
401 _omap2_sram_configure_core_dpll =
402 omap_sram_push(omap34xx_sram_configure_core_dpll,
403 omap34xx_sram_configure_core_dpll_sz);
270 404
271 return 0; 405 return 0;
272} 406}
273#else 407#else
274#define omap2_sram_init() do {} while (0) 408static inline int omap34xx_sram_init(void)
409{
410 return 0;
411}
275#endif 412#endif
276 413
277int __init omap_sram_init(void) 414int __init omap_sram_init(void)
@@ -279,10 +416,14 @@ int __init omap_sram_init(void)
279 omap_detect_sram(); 416 omap_detect_sram();
280 omap_map_sram(); 417 omap_map_sram();
281 418
282 if (!cpu_is_omap24xx()) 419 if (!(cpu_class_is_omap2()))
283 omap1_sram_init(); 420 omap1_sram_init();
284 else 421 else if (cpu_is_omap242x())
285 omap2_sram_init(); 422 omap242x_sram_init();
423 else if (cpu_is_omap2430())
424 omap243x_sram_init();
425 else if (cpu_is_omap34xx())
426 omap34xx_sram_init();
286 427
287 return 0; 428 return 0;
288} 429}