ARM: OMAP4: Add minimal support for omap4

This patch adds the support for OMAP4. The platform and machine specific
headers and sources updated for OMAP4430 SDP platform.

OMAP4430 is Texas Instrument's SOC based on ARM Cortex-A9 SMP architecture.
It's a dual core SOC with GIC used for interrupt handling and SCU for cache
coherency.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

13 files changed, 264 insertions, 14 deletions

diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index 073a2c5569f0..c20e02ec3034 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -22,7 +22,8 @@ struct clkops {
         void                    (*disable)(struct clk *);
 };
 
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
+                defined(CONFIG_ARCH_OMAP4)
 
 struct clksel_rate {
         u32                     val;
@@ -51,7 +52,7 @@ struct dpll_data {
         u8                      max_divider;
         u32                     max_tolerance;
         u16                     max_multiplier;
-#  if defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
         u8                      modes;
         void __iomem            *autoidle_reg;
         void __iomem            *idlest_reg;
@@ -83,7 +84,8 @@ struct clk {
         void                    (*init)(struct clk *);
         __u8                    enable_bit;
         __s8                    usecount;
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
+                defined(CONFIG_ARCH_OMAP4)
         u8                      fixed_div;
         void __iomem            *clksel_reg;
         u32                     clksel_mask;
diff --git a/arch/arm/plat-omap/include/mach/common.h b/arch/arm/plat-omap/include/mach/common.h
index 0ecf36deb17b..4b188334c666 100644
--- a/arch/arm/plat-omap/include/mach/common.h
+++ b/arch/arm/plat-omap/include/mach/common.h
@@ -62,6 +62,7 @@ struct omap_globals {
 void omap2_set_globals_242x(void);
 void omap2_set_globals_243x(void);
 void omap2_set_globals_343x(void);
+void omap2_set_globals_443x(void);
 
 /* These get called from omap2_set_globals_xxxx(), do not call these */
 void omap2_set_globals_tap(struct omap_globals *);
diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h
index 269147f3836f..f45ec621da96 100644
--- a/arch/arm/plat-omap/include/mach/control.h
+++ b/arch/arm/plat-omap/include/mach/control.h
@@ -1,9 +1,9 @@
 /*
  * arch/arm/plat-omap/include/mach/control.h
  *
- * OMAP2/3 System Control Module definitions
+ * OMAP2/3/4 System Control Module definitions
  *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
  * Copyright (C) 2007-2008 Nokia Corporation
  *
  * Written by Paul Walmsley
@@ -190,7 +190,8 @@
 #define OMAP2_PBIASLITEVMODE0           (1 << 0)
 
 #ifndef __ASSEMBLY__
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
+                defined(CONFIG_ARCH_OMAP4)
 extern void __iomem *omap_ctrl_base_get(void);
 extern u8 omap_ctrl_readb(u16 offset);
 extern u16 omap_ctrl_readw(u16 offset);
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h
index 98b144252364..fc60c4ebcc28 100644
--- a/arch/arm/plat-omap/include/mach/cpu.h
+++ b/arch/arm/plat-omap/include/mach/cpu.h
@@ -5,8 +5,12 @@
  *
  * Copyright (C) 2004, 2008 Nokia Corporation
  *
+ * Copyright (C) 2009 Texas Instruments.
+ *
  * Written by Tony Lindgren <tony.lindgren@nokia.com>
  *
+ * Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -155,6 +159,8 @@ IS_OMAP_SUBCLASS(343x, 0x343)
 #define cpu_is_omap243x()               0
 #define cpu_is_omap34xx()               0
 #define cpu_is_omap343x()               0
+#define cpu_is_omap44xx()               0
+#define cpu_is_omap443x()               0
 
 #if defined(MULTI_OMAP1)
 # if defined(CONFIG_ARCH_OMAP730)
@@ -348,12 +354,21 @@ IS_OMAP_TYPE(3430, 0x3430)
 # define cpu_is_omap3430()              is_omap3430()
 #endif
 
+# if defined(CONFIG_ARCH_OMAP4)
+# undef cpu_is_omap44xx
+# undef cpu_is_omap443x
+# define cpu_is_omap44xx()              1
+# define cpu_is_omap443x()              1
+# endif
+
 /* Macros to detect if we have OMAP1 or OMAP2 */
 #define cpu_class_is_omap1()    (cpu_is_omap7xx() || cpu_is_omap15xx() || \
                                 cpu_is_omap16xx())
-#define cpu_class_is_omap2()    (cpu_is_omap24xx() || cpu_is_omap34xx())
+#define cpu_class_is_omap2()    (cpu_is_omap24xx() || cpu_is_omap34xx() || \
+                                cpu_is_omap44xx())
 
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
+                        defined(CONFIG_ARCH_OMAP4)
 
 /* Various silicon revisions for omap2 */
 #define OMAP242X_CLASS          0x24200024
@@ -370,6 +385,8 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define OMAP3430_REV_ES3_0      0x34303034
 #define OMAP3430_REV_ES3_1      0x34304034
 
+#define OMAP443X_CLASS          0x44300034
+
 /*
  * omap_chip bits
  *
diff --git a/arch/arm/plat-omap/include/mach/debug-macro.S b/arch/arm/plat-omap/include/mach/debug-macro.S
index 1b11f5c6a2d9..ac24050e3416 100644
--- a/arch/arm/plat-omap/include/mach/debug-macro.S
+++ b/arch/arm/plat-omap/include/mach/debug-macro.S
@@ -36,7 +36,7 @@
                 add     \rx, \rx, #0x00004000   @ UART 3
 #endif
 
-#elif   CONFIG_ARCH_OMAP3
+#elif defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
                 moveq   \rx, #0x48000000        @ physical base address
                 movne   \rx, #0xd8000000        @ virtual base
                 orr     \rx, \rx, #0x0006a000
diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/mach/dma.h
index 19df76f97ab3..8c1eae88737e 100644
--- a/arch/arm/plat-omap/include/mach/dma.h
+++ b/arch/arm/plat-omap/include/mach/dma.h
@@ -48,6 +48,7 @@
 /* Hardware registers for omap2 and omap3 */
 #define OMAP24XX_DMA4_BASE              (L4_24XX_BASE + 0x56000)
 #define OMAP34XX_DMA4_BASE              (L4_34XX_BASE + 0x56000)
+#define OMAP44XX_DMA4_BASE              (L4_44XX_BASE + 0x56000)
 
 #define OMAP_DMA4_REVISION              0x00
 #define OMAP_DMA4_GCR                   0x78
diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S
index 33256a0e9a28..00f45c01390d 100644
--- a/arch/arm/plat-omap/include/mach/entry-macro.S
+++ b/arch/arm/plat-omap/include/mach/entry-macro.S
@@ -3,6 +3,9 @@
  *
  * Low-level IRQ helper macros for OMAP-based platforms
  *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
  * This file is licensed under  the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
@@ -10,6 +13,7 @@
 #include <mach/hardware.h>
 #include <mach/io.h>
 #include <mach/irqs.h>
+#include <asm/hardware/gic.h>
 
 #if defined(CONFIG_ARCH_OMAP1)
 
@@ -56,7 +60,8 @@
                 .endm
 
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                        defined(CONFIG_ARCH_OMAP4)
 
 #include <mach/omap24xx.h>
 #include <mach/omap34xx.h>
@@ -67,7 +72,9 @@
 #elif defined(CONFIG_ARCH_OMAP34XX)
 #define OMAP2_VA_IC_BASE                IO_ADDRESS(OMAP34XX_IC_BASE)
 #endif
-
+#if defined(CONFIG_ARCH_OMAP4)
+#include <mach/omap44xx.h>
+#endif
 #define INTCPS_SIR_IRQ_OFFSET   0x0040          /* Active interrupt offset */
 #define ACTIVEIRQ_MASK          0x7f            /* Active interrupt bits */
 
@@ -80,6 +87,7 @@
                 .macro  arch_ret_to_user, tmp1, tmp2
                 .endm
 
+#ifndef CONFIG_ARCH_OMAP4
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
                 ldr     \base, =OMAP2_VA_IC_BASE
                 ldr     \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
@@ -95,6 +103,40 @@
                 and     \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
 
                 .endm
+#else
+                /*
+                 * The interrupt numbering scheme is defined in the
+                 * interrupt controller spec.  To wit:
+                 *
+                 * Interrupts 0-15 are IPI
+                 * 16-28 are reserved
+                 * 29-31 are local.  We allow 30 to be used for the watchdog.
+                 * 32-1020 are global
+                 * 1021-1022 are reserved
+                 * 1023 is "spurious" (no interrupt)
+                 *
+                 * For now, we ignore all local interrupts so only return an
+                 * interrupt if it's between 30 and 1020.  The test_for_ipi
+                 * routine below will pick up on IPIs.
+                 * A simple read from the controller will tell us the number
+                 * of the highest priority enabled interrupt.
+                 * We then just need to check whether it is in the
+                 * valid range for an IRQ (30-1020 inclusive).
+                 */
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \base, =OMAP44XX_VA_GIC_CPU_BASE
+                ldr     \irqstat, [\base, #GIC_CPU_INTACK]
+
+                ldr     \tmp, =1021
+
+                bic     \irqnr, \irqstat, #0x1c00
+
+                cmp     \irqnr, #29
+                cmpcc   \irqnr, \irqnr
+                cmpne   \irqnr, \tmp
+                cmpcs   \irqnr, \irqnr
+                .endm
+#endif
 
                 .macro  irq_prio_table
                 .endm
diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/mach/hardware.h
index 3dc423ed3e80..26c1fbff08aa 100644
--- a/arch/arm/plat-omap/include/mach/hardware.h
+++ b/arch/arm/plat-omap/include/mach/hardware.h
@@ -285,5 +285,6 @@
 #include "omap16xx.h"
 #include "omap24xx.h"
 #include "omap34xx.h"
+#include "omap44xx.h"
 
 #endif  /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h
index 0610d7e2b3d7..3b2814720569 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/mach/io.h
@@ -6,6 +6,9 @@
  * Copied from arch/arm/mach-sa1100/include/mach/io.h
  * Copyright (C) 1997-1999 Russell King
  *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
  * Free Software Foundation; either version 2 of the License, or (at your
@@ -157,6 +160,40 @@
 #define DSP_MMU_34XX_VIRT       0xe2000000
 #define DSP_MMU_34XX_SIZE       SZ_4K
 
+
+#elif defined(CONFIG_ARCH_OMAP4)
+/* We map both L3 and L4 on OMAP4 */
+#define L3_44XX_PHYS            L3_44XX_BASE
+#define L3_44XX_VIRT            0xd4000000
+#define L3_44XX_SIZE            SZ_1M
+
+#define L4_44XX_PHYS            L4_44XX_BASE
+#define L4_44XX_VIRT            0xda000000
+#define L4_44XX_SIZE            SZ_4M
+
+
+#define L4_WK_44XX_PHYS         L4_WK_44XX_BASE
+#define L4_WK_44XX_VIRT         0xda300000
+#define L4_WK_44XX_SIZE         SZ_1M
+
+#define L4_PER_44XX_PHYS        L4_PER_44XX_BASE
+#define L4_PER_44XX_VIRT        0xd8000000
+#define L4_PER_44XX_SIZE        SZ_4M
+
+#define L4_EMU_44XX_PHYS        L4_EMU_44XX_BASE
+#define L4_EMU_44XX_VIRT        0xe4000000
+#define L4_EMU_44XX_SIZE        SZ_64M
+
+#define OMAP44XX_GPMC_PHYS      OMAP44XX_GPMC_BASE
+#define OMAP44XX_GPMC_VIRT      0xe0000000
+#define OMAP44XX_GPMC_SIZE      SZ_1M
+
+
+#define IO_OFFSET               0x90000000
+#define __IO_ADDRESS(pa)        ((pa) + IO_OFFSET)/* Works for L3 and L4 */
+#define __OMAP2_IO_ADDRESS(pa)  ((pa) + IO_OFFSET)/* Works for L3 and L4 */
+#define io_v2p(va)              ((va) - IO_OFFSET)/* Works for L3 and L4 */
+
 #endif
 
 #define IO_ADDRESS(pa)          IOMEM(__IO_ADDRESS(pa))
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
index 7f57ee66f364..5bc331e93cf2 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -4,6 +4,9 @@
  *  Copyright (C) Greg Lonnon 2001
  *  Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
  *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -422,6 +425,92 @@
 
 #define INT_34XX_BENCH_MPU_EMUL 3
 
+
+#define IRQ_GIC_START           32
+
+#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START)
+#define INT_44XX_SSM_ABORT_IRQ  (6 + IRQ_GIC_START)
+#define INT_44XX_SYS_NIRQ       (7 + IRQ_GIC_START)
+#define INT_44XX_D2D_FW_IRQ     (8 + IRQ_GIC_START)
+#define INT_44XX_PRCM_MPU_IRQ   (11 + IRQ_GIC_START)
+#define INT_44XX_SDMA_IRQ0      (12 + IRQ_GIC_START)
+#define INT_44XX_SDMA_IRQ1      (13 + IRQ_GIC_START)
+#define INT_44XX_SDMA_IRQ2      (14 + IRQ_GIC_START)
+#define INT_44XX_SDMA_IRQ3      (15 + IRQ_GIC_START)
+#define INT_44XX_ISS_IRQ        (24 + IRQ_GIC_START)
+#define INT_44XX_DSS_IRQ        (25 + IRQ_GIC_START)
+#define INT_44XX_MAIL_U0_MPU    (26 + IRQ_GIC_START)
+#define INT_44XX_DSP_MMU        (28 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER1       (37 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER2       (38 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER3       (39 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER4       (40 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER5       (41 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER6       (42 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER7       (43 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER8       (44 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER9       (45 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER10      (46 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER11      (47 + IRQ_GIC_START)
+#define INT_44XX_GPTIMER12      (95 + IRQ_GIC_START)
+#define INT_44XX_SHA1MD5        (51 + IRQ_GIC_START)
+#define INT_44XX_I2C1_IRQ       (56 + IRQ_GIC_START)
+#define INT_44XX_I2C2_IRQ       (57 + IRQ_GIC_START)
+#define INT_44XX_HDQ_IRQ        (58 + IRQ_GIC_START)
+#define INT_44XX_SPI1_IRQ       (65 + IRQ_GIC_START)
+#define INT_44XX_SPI2_IRQ       (66 + IRQ_GIC_START)
+#define INT_44XX_HSI_1_IRQ0     (67 + IRQ_GIC_START)
+#define INT_44XX_HSI_2_IRQ1     (68 + IRQ_GIC_START)
+#define INT_44XX_HSI_1_DMAIRQ   (71 + IRQ_GIC_START)
+#define INT_44XX_UART1_IRQ      (72 + IRQ_GIC_START)
+#define INT_44XX_UART2_IRQ      (73 + IRQ_GIC_START)
+#define INT_44XX_UART3_IRQ      (74 + IRQ_GIC_START)
+#define INT_44XX_UART4_IRQ      (70 + IRQ_GIC_START)
+#define INT_44XX_USB_IRQ_NISO   (76 + IRQ_GIC_START)
+#define INT_44XX_USB_IRQ_ISO    (77 + IRQ_GIC_START)
+#define INT_44XX_USB_IRQ_HGEN   (78 + IRQ_GIC_START)
+#define INT_44XX_USB_IRQ_HSOF   (79 + IRQ_GIC_START)
+#define INT_44XX_USB_IRQ_OTG    (80 + IRQ_GIC_START)
+#define INT_44XX_MCBSP4_IRQ_TX  (81 + IRQ_GIC_START)
+#define INT_44XX_MCBSP4_IRQ_RX  (82 + IRQ_GIC_START)
+#define INT_44XX_MMC_IRQ        (83 + IRQ_GIC_START)
+#define INT_44XX_MMC2_IRQ       (86 + IRQ_GIC_START)
+#define INT_44XX_MCBSP2_IRQ_TX  (89 + IRQ_GIC_START)
+#define INT_44XX_MCBSP2_IRQ_RX  (90 + IRQ_GIC_START)
+#define INT_44XX_SPI3_IRQ       (91 + IRQ_GIC_START)
+#define INT_44XX_SPI5_IRQ       (69 + IRQ_GIC_START)
+
+#define INT_44XX_MCBSP5_IRQ     (16 + IRQ_GIC_START)
+#define INT_44xX_MCBSP1_IRQ     (17 + IRQ_GIC_START)
+#define INT_44XX_MCBSP2_IRQ     (22 + IRQ_GIC_START)
+#define INT_44XX_MCBSP3_IRQ     (23 + IRQ_GIC_START)
+#define INT_44XX_MCBSP4_IRQ     (27 + IRQ_GIC_START)
+#define INT_44XX_HS_USB_MC      (92 + IRQ_GIC_START)
+#define INT_44XX_HS_USB_DMA     (93 + IRQ_GIC_START)
+
+#define INT_44XX_GPIO_BANK1     (29 + IRQ_GIC_START)
+#define INT_44XX_GPIO_BANK2     (30 + IRQ_GIC_START)
+#define INT_44XX_GPIO_BANK3     (31 + IRQ_GIC_START)
+#define INT_44XX_GPIO_BANK4     (32 + IRQ_GIC_START)
+#define INT_44XX_GPIO_BANK5     (33 + IRQ_GIC_START)
+#define INT_44XX_GPIO_BANK6     (34 + IRQ_GIC_START)
+#define INT_44XX_USIM_IRQ       (35 + IRQ_GIC_START)
+#define INT_44XX_WDT3_IRQ       (36 + IRQ_GIC_START)
+#define INT_44XX_SPI4_IRQ       (48 + IRQ_GIC_START)
+#define INT_44XX_SHA1MD52_IRQ   (49 + IRQ_GIC_START)
+#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START)
+#define INT_44XX_SHA1MD51_IRQ   (51 + IRQ_GIC_START)
+#define INT_44XX_RNG_IRQ        (52 + IRQ_GIC_START)
+#define INT_44XX_I2C3_IRQ       (61 + IRQ_GIC_START)
+#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START)
+#define INT_44XX_PBIAS_IRQ      (75 + IRQ_GIC_START)
+#define INT_44XX_OHCI_IRQ       (76 + IRQ_GIC_START)
+#define INT_44XX_EHCI_IRQ       (77 + IRQ_GIC_START)
+#define INT_44XX_TLL_IRQ        (78 + IRQ_GIC_START)
+#define INT_44XX_PARTHASH_IRQ   (79 + IRQ_GIC_START)
+#define INT_44XX_MMC3_IRQ       (94 + IRQ_GIC_START)
+
+
 /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
  * 16 MPUIO lines */
 #define OMAP_MAX_GPIO_LINES     192
diff --git a/arch/arm/plat-omap/include/mach/memory.h b/arch/arm/plat-omap/include/mach/memory.h
index 99ed564d9277..9ad41dc484c1 100644
--- a/arch/arm/plat-omap/include/mach/memory.h
+++ b/arch/arm/plat-omap/include/mach/memory.h
@@ -38,7 +38,8 @@
  */
 #if defined(CONFIG_ARCH_OMAP1)
 #define PHYS_OFFSET             UL(0x10000000)
-#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
+                        defined(CONFIG_ARCH_OMAP4)
 #define PHYS_OFFSET             UL(0x80000000)
 #endif
 
diff --git a/arch/arm/plat-omap/include/mach/omap44xx.h b/arch/arm/plat-omap/include/mach/omap44xx.h
new file mode 100644
index 000000000000..15dec7f1c7c0
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/omap44xx.h
@@ -0,0 +1,46 @@
+/*:
+ * Address mappings and base address for OMAP4 interconnects
+ * and peripherals.
+ *
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_OMAP44XX_H
+#define __ASM_ARCH_OMAP44XX_H
+
+/*
+ * Please place only base defines here and put the rest in device
+ * specific headers.
+ */
+#define L4_44XX_BASE                    0x4a000000
+#define L4_WK_44XX_BASE                 0x4a300000
+#define L4_PER_44XX_BASE                0x48000000
+#define L4_EMU_44XX_BASE                0x54000000
+#define L3_44XX_BASE                    0x44000000
+#define OMAP4430_32KSYNCT_BASE          0x4a304000
+#define OMAP4430_CM_BASE                0x4a004000
+#define OMAP4430_PRM_BASE               0x48306000
+#define OMAP44XX_GPMC_BASE              0x50000000
+#define OMAP443X_SCM_BASE               0x4a002000
+#define OMAP443X_CTRL_BASE              OMAP443X_SCM_BASE
+#define OMAP44XX_IC_BASE                0x48200000
+#define OMAP44XX_IVA_INTC_BASE          0x40000000
+#define IRQ_SIR_IRQ                     0x0040
+#define OMAP44XX_GIC_DIST_BASE          0x48241000
+#define OMAP44XX_GIC_CPU_BASE           0x48240100
+#define OMAP44XX_VA_GIC_CPU_BASE        IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
+#define OMAP44XX_SCU_BASE               0x48240000
+#define OMAP44XX_VA_SCU_BASE            IO_ADDRESS(OMAP44XX_SCU_BASE)
+#define OMAP44XX_LOCAL_TWD_BASE         0x48240600
+#define OMAP44XX_VA_LOCAL_TWD_BASE      IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE)
+#define OMAP44XX_LOCAL_TWD_SIZE         0x00000100
+#define OMAP44XX_WKUPGEN_BASE           0x48281000
+#define OMAP44XX_VA_WKUPGEN_BASE        IO_ADDRESS(OMAP44XX_WKUPGEN_BASE)
+
+#endif /* __ASM_ARCH_OMAP44XX_H */
+
diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/mach/serial.h
index 8a676a04be48..e37894e423bd 100644
--- a/arch/arm/plat-omap/include/mach/serial.h
+++ b/arch/arm/plat-omap/include/mach/serial.h
@@ -1,5 +1,8 @@
 /*
- *  arch/arm/plat-omap/include/mach/serial.h
+ * arch/arm/plat-omap/include/mach/serial.h
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Addded OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -15,19 +18,28 @@
 #define OMAP_UART1_BASE         0xfffb0000
 #define OMAP_UART2_BASE         0xfffb0800
 #define OMAP_UART3_BASE         0xfffb9800
+#define OMAP_MAX_NR_PORTS       3
 #elif defined(CONFIG_ARCH_OMAP2)
 /* OMAP2 serial ports */
 #define OMAP_UART1_BASE         0x4806a000
 #define OMAP_UART2_BASE         0x4806c000
 #define OMAP_UART3_BASE         0x4806e000
+#define OMAP_MAX_NR_PORTS       3
 #elif defined(CONFIG_ARCH_OMAP3)
 /* OMAP3 serial ports */
 #define OMAP_UART1_BASE         0x4806a000
 #define OMAP_UART2_BASE         0x4806c000
 #define OMAP_UART3_BASE         0x49020000
+#define OMAP_MAX_NR_PORTS       3
+#elif defined(CONFIG_ARCH_OMAP4)
+/* OMAP4 serial ports */
+#define OMAP_UART1_BASE         0x4806a000
+#define OMAP_UART2_BASE         0x4806c000
+#define OMAP_UART3_BASE         0x48020000
+#define OMAP_UART4_BASE         0x4806e000
+#define OMAP_MAX_NR_PORTS       4
 #endif
 
-#define OMAP_MAX_NR_PORTS       3
 #define OMAP1510_BASE_BAUD      (12000000/16)
 #define OMAP16XX_BASE_BAUD      (48000000/16)
 #define OMAP24XX_BASE_BAUD      (48000000/16)