diff options
| author | Alistair Buxton <a.j.buxton@gmail.com> | 2009-09-17 23:09:39 -0400 |
|---|---|---|
| committer | Alistair Buxton <a.j.buxton@gmail.com> | 2009-10-07 18:14:06 -0400 |
| commit | 372b1c32e7e7d7aa5f44e0eaed4ad8ae21e4e9da (patch) | |
| tree | 32491b47873015ae75cf2e8bc675cb20e00ab259 /arch/arm/plat-omap/include | |
| parent | b51988db94faec47d6e7c69c8e691cfc194f66db (diff) | |
OMAP7XX: Replace omap730 references in irqs.h and all users
This patch is part of a series which removes references to omap730 in code
which is shared with omap850, replacing them with references to omap7xx.
Turns INT_730_* to INT_7XX_* for definitions in irqs.h and all users.
Signed-off-by: Alistair Buxton <a.j.buxton@gmail.com>
Reviewed-by: Zebediah C. McClure <zmc@lurian.net>
Diffstat (limited to 'arch/arm/plat-omap/include')
| -rw-r--r-- | arch/arm/plat-omap/include/mach/entry-macro.S | 2 | ||||
| -rw-r--r-- | arch/arm/plat-omap/include/mach/irqs.h | 148 |
2 files changed, 75 insertions, 75 deletions
diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S index bcf715856658..abe086416e19 100644 --- a/arch/arm/plat-omap/include/mach/entry-macro.S +++ b/arch/arm/plat-omap/include/mach/entry-macro.S | |||
| @@ -21,7 +21,7 @@ | |||
| 21 | (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)) | 21 | (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)) |
| 22 | #error "FIXME: OMAP7XX doesn't support multiple-OMAP" | 22 | #error "FIXME: OMAP7XX doesn't support multiple-OMAP" |
| 23 | #elif defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | 23 | #elif defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
| 24 | #define INT_IH2_IRQ INT_730_IH2_IRQ | 24 | #define INT_IH2_IRQ INT_7XX_IH2_IRQ |
| 25 | #elif defined(CONFIG_ARCH_OMAP15XX) | 25 | #elif defined(CONFIG_ARCH_OMAP15XX) |
| 26 | #define INT_IH2_IRQ INT_1510_IH2_IRQ | 26 | #define INT_IH2_IRQ INT_1510_IH2_IRQ |
| 27 | #elif defined(CONFIG_ARCH_OMAP16XX) | 27 | #elif defined(CONFIG_ARCH_OMAP16XX) |
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h index 7f338f0c7450..6a6d0281e1d5 100644 --- a/arch/arm/plat-omap/include/mach/irqs.h +++ b/arch/arm/plat-omap/include/mach/irqs.h | |||
| @@ -86,26 +86,26 @@ | |||
| 86 | #define INT_1610_SSR_FIFO_0 29 | 86 | #define INT_1610_SSR_FIFO_0 29 |
| 87 | 87 | ||
| 88 | /* | 88 | /* |
| 89 | * OMAP-730 specific IRQ numbers for interrupt handler 1 | 89 | * OMAP-7xx specific IRQ numbers for interrupt handler 1 |
| 90 | */ | 90 | */ |
| 91 | #define INT_730_IH2_FIQ 0 | 91 | #define INT_7XX_IH2_FIQ 0 |
| 92 | #define INT_730_IH2_IRQ 1 | 92 | #define INT_7XX_IH2_IRQ 1 |
| 93 | #define INT_730_USB_NON_ISO 2 | 93 | #define INT_7XX_USB_NON_ISO 2 |
| 94 | #define INT_730_USB_ISO 3 | 94 | #define INT_7XX_USB_ISO 3 |
| 95 | #define INT_730_ICR 4 | 95 | #define INT_7XX_ICR 4 |
| 96 | #define INT_730_EAC 5 | 96 | #define INT_7XX_EAC 5 |
| 97 | #define INT_730_GPIO_BANK1 6 | 97 | #define INT_7XX_GPIO_BANK1 6 |
| 98 | #define INT_730_GPIO_BANK2 7 | 98 | #define INT_7XX_GPIO_BANK2 7 |
| 99 | #define INT_730_GPIO_BANK3 8 | 99 | #define INT_7XX_GPIO_BANK3 8 |
| 100 | #define INT_730_McBSP2TX 10 | 100 | #define INT_7XX_McBSP2TX 10 |
| 101 | #define INT_730_McBSP2RX 11 | 101 | #define INT_7XX_McBSP2RX 11 |
| 102 | #define INT_730_McBSP2RX_OVF 12 | 102 | #define INT_7XX_McBSP2RX_OVF 12 |
| 103 | #define INT_730_LCD_LINE 14 | 103 | #define INT_7XX_LCD_LINE 14 |
| 104 | #define INT_730_GSM_PROTECT 15 | 104 | #define INT_7XX_GSM_PROTECT 15 |
| 105 | #define INT_730_TIMER3 16 | 105 | #define INT_7XX_TIMER3 16 |
| 106 | #define INT_730_GPIO_BANK5 17 | 106 | #define INT_7XX_GPIO_BANK5 17 |
| 107 | #define INT_730_GPIO_BANK6 18 | 107 | #define INT_7XX_GPIO_BANK6 18 |
| 108 | #define INT_730_SPGIO_WR 29 | 108 | #define INT_7XX_SPGIO_WR 29 |
| 109 | 109 | ||
| 110 | /* | 110 | /* |
| 111 | * IRQ numbers for interrupt handler 2 | 111 | * IRQ numbers for interrupt handler 2 |
| @@ -183,62 +183,62 @@ | |||
| 183 | #define INT_1610_SHA1MD5 (91 + IH2_BASE) | 183 | #define INT_1610_SHA1MD5 (91 + IH2_BASE) |
| 184 | 184 | ||
| 185 | /* | 185 | /* |
| 186 | * OMAP-730 specific IRQ numbers for interrupt handler 2 | 186 | * OMAP-7xx specific IRQ numbers for interrupt handler 2 |
| 187 | */ | 187 | */ |
| 188 | #define INT_730_HW_ERRORS (0 + IH2_BASE) | 188 | #define INT_7XX_HW_ERRORS (0 + IH2_BASE) |
| 189 | #define INT_730_NFIQ_PWR_FAIL (1 + IH2_BASE) | 189 | #define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE) |
| 190 | #define INT_730_CFCD (2 + IH2_BASE) | 190 | #define INT_7XX_CFCD (2 + IH2_BASE) |
| 191 | #define INT_730_CFIREQ (3 + IH2_BASE) | 191 | #define INT_7XX_CFIREQ (3 + IH2_BASE) |
| 192 | #define INT_730_I2C (4 + IH2_BASE) | 192 | #define INT_7XX_I2C (4 + IH2_BASE) |
| 193 | #define INT_730_PCC (5 + IH2_BASE) | 193 | #define INT_7XX_PCC (5 + IH2_BASE) |
| 194 | #define INT_730_MPU_EXT_NIRQ (6 + IH2_BASE) | 194 | #define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE) |
| 195 | #define INT_730_SPI_100K_1 (7 + IH2_BASE) | 195 | #define INT_7XX_SPI_100K_1 (7 + IH2_BASE) |
| 196 | #define INT_730_SYREN_SPI (8 + IH2_BASE) | 196 | #define INT_7XX_SYREN_SPI (8 + IH2_BASE) |
| 197 | #define INT_730_VLYNQ (9 + IH2_BASE) | 197 | #define INT_7XX_VLYNQ (9 + IH2_BASE) |
| 198 | #define INT_730_GPIO_BANK4 (10 + IH2_BASE) | 198 | #define INT_7XX_GPIO_BANK4 (10 + IH2_BASE) |
| 199 | #define INT_730_McBSP1TX (11 + IH2_BASE) | 199 | #define INT_7XX_McBSP1TX (11 + IH2_BASE) |
| 200 | #define INT_730_McBSP1RX (12 + IH2_BASE) | 200 | #define INT_7XX_McBSP1RX (12 + IH2_BASE) |
| 201 | #define INT_730_McBSP1RX_OF (13 + IH2_BASE) | 201 | #define INT_7XX_McBSP1RX_OF (13 + IH2_BASE) |
| 202 | #define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE) | 202 | #define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE) |
| 203 | #define INT_730_UART_MODEM_1 (15 + IH2_BASE) | 203 | #define INT_7XX_UART_MODEM_1 (15 + IH2_BASE) |
| 204 | #define INT_730_MCSI (16 + IH2_BASE) | 204 | #define INT_7XX_MCSI (16 + IH2_BASE) |
| 205 | #define INT_730_uWireTX (17 + IH2_BASE) | 205 | #define INT_7XX_uWireTX (17 + IH2_BASE) |
| 206 | #define INT_730_uWireRX (18 + IH2_BASE) | 206 | #define INT_7XX_uWireRX (18 + IH2_BASE) |
| 207 | #define INT_730_SMC_CD (19 + IH2_BASE) | 207 | #define INT_7XX_SMC_CD (19 + IH2_BASE) |
| 208 | #define INT_730_SMC_IREQ (20 + IH2_BASE) | 208 | #define INT_7XX_SMC_IREQ (20 + IH2_BASE) |
| 209 | #define INT_730_HDQ_1WIRE (21 + IH2_BASE) | 209 | #define INT_7XX_HDQ_1WIRE (21 + IH2_BASE) |
| 210 | #define INT_730_TIMER32K (22 + IH2_BASE) | 210 | #define INT_7XX_TIMER32K (22 + IH2_BASE) |
| 211 | #define INT_730_MMC_SDIO (23 + IH2_BASE) | 211 | #define INT_7XX_MMC_SDIO (23 + IH2_BASE) |
| 212 | #define INT_730_UPLD (24 + IH2_BASE) | 212 | #define INT_7XX_UPLD (24 + IH2_BASE) |
| 213 | #define INT_730_USB_HHC_1 (27 + IH2_BASE) | 213 | #define INT_7XX_USB_HHC_1 (27 + IH2_BASE) |
| 214 | #define INT_730_USB_HHC_2 (28 + IH2_BASE) | 214 | #define INT_7XX_USB_HHC_2 (28 + IH2_BASE) |
| 215 | #define INT_730_USB_GENI (29 + IH2_BASE) | 215 | #define INT_7XX_USB_GENI (29 + IH2_BASE) |
| 216 | #define INT_730_USB_OTG (30 + IH2_BASE) | 216 | #define INT_7XX_USB_OTG (30 + IH2_BASE) |
| 217 | #define INT_730_CAMERA_IF (31 + IH2_BASE) | 217 | #define INT_7XX_CAMERA_IF (31 + IH2_BASE) |
| 218 | #define INT_730_RNG (32 + IH2_BASE) | 218 | #define INT_7XX_RNG (32 + IH2_BASE) |
| 219 | #define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE) | 219 | #define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE) |
| 220 | #define INT_730_DBB_RF_EN (34 + IH2_BASE) | 220 | #define INT_7XX_DBB_RF_EN (34 + IH2_BASE) |
| 221 | #define INT_730_MPUIO_KEYPAD (35 + IH2_BASE) | 221 | #define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE) |
| 222 | #define INT_730_SHA1_MD5 (36 + IH2_BASE) | 222 | #define INT_7XX_SHA1_MD5 (36 + IH2_BASE) |
| 223 | #define INT_730_SPI_100K_2 (37 + IH2_BASE) | 223 | #define INT_7XX_SPI_100K_2 (37 + IH2_BASE) |
| 224 | #define INT_730_RNG_IDLE (38 + IH2_BASE) | 224 | #define INT_7XX_RNG_IDLE (38 + IH2_BASE) |
| 225 | #define INT_730_MPUIO (39 + IH2_BASE) | 225 | #define INT_7XX_MPUIO (39 + IH2_BASE) |
| 226 | #define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) | 226 | #define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) |
| 227 | #define INT_730_LLPC_OE_FALLING (41 + IH2_BASE) | 227 | #define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE) |
| 228 | #define INT_730_LLPC_OE_RISING (42 + IH2_BASE) | 228 | #define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE) |
| 229 | #define INT_730_LLPC_VSYNC (43 + IH2_BASE) | 229 | #define INT_7XX_LLPC_VSYNC (43 + IH2_BASE) |
| 230 | #define INT_730_WAKE_UP_REQ (46 + IH2_BASE) | 230 | #define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE) |
| 231 | #define INT_730_DMA_CH6 (53 + IH2_BASE) | 231 | #define INT_7XX_DMA_CH6 (53 + IH2_BASE) |
| 232 | #define INT_730_DMA_CH7 (54 + IH2_BASE) | 232 | #define INT_7XX_DMA_CH7 (54 + IH2_BASE) |
| 233 | #define INT_730_DMA_CH8 (55 + IH2_BASE) | 233 | #define INT_7XX_DMA_CH8 (55 + IH2_BASE) |
| 234 | #define INT_730_DMA_CH9 (56 + IH2_BASE) | 234 | #define INT_7XX_DMA_CH9 (56 + IH2_BASE) |
| 235 | #define INT_730_DMA_CH10 (57 + IH2_BASE) | 235 | #define INT_7XX_DMA_CH10 (57 + IH2_BASE) |
| 236 | #define INT_730_DMA_CH11 (58 + IH2_BASE) | 236 | #define INT_7XX_DMA_CH11 (58 + IH2_BASE) |
| 237 | #define INT_730_DMA_CH12 (59 + IH2_BASE) | 237 | #define INT_7XX_DMA_CH12 (59 + IH2_BASE) |
| 238 | #define INT_730_DMA_CH13 (60 + IH2_BASE) | 238 | #define INT_7XX_DMA_CH13 (60 + IH2_BASE) |
| 239 | #define INT_730_DMA_CH14 (61 + IH2_BASE) | 239 | #define INT_7XX_DMA_CH14 (61 + IH2_BASE) |
| 240 | #define INT_730_DMA_CH15 (62 + IH2_BASE) | 240 | #define INT_7XX_DMA_CH15 (62 + IH2_BASE) |
| 241 | #define INT_730_NAND (63 + IH2_BASE) | 241 | #define INT_7XX_NAND (63 + IH2_BASE) |
| 242 | 242 | ||
| 243 | #define INT_24XX_SYS_NIRQ 7 | 243 | #define INT_24XX_SYS_NIRQ 7 |
| 244 | #define INT_24XX_SDMA_IRQ0 12 | 244 | #define INT_24XX_SDMA_IRQ0 12 |