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authorTony Lindgren <tony@atomide.com>2009-10-19 20:32:58 -0400
committerTony Lindgren <tony@atomide.com>2009-10-19 20:32:58 -0400
commit3eff851b9dc1e84aa0822772e0be9afb0c973585 (patch)
tree7c9e7b28e65e8c74c2cc6601f0ff4e5f49e6a8c2 /arch/arm/plat-omap/include/plat
parent1e79ab8a45b71d3d08eb6cdac44b66229dcea03e (diff)
omap: headers: Create headers necessary for compile under mach-omap1 and mach-omap2
Create the headers needed for compiling under mach-omap1/include/mach and mach-omap2/include/mach. This was done with the following script: #!/bin/bash mach_files="clkdev.h gpio.h hardware.h io.h irqs.h memory.h \ smp.h system.h timex.h uncompress.h vmalloc.h" omaps="mach-omap1 mach-omap2" mach_dir_old="arch/arm/plat-omap/include/mach" plat_dir_new="arch/arm/plat-omap/include/plat" mkdir -p $plat_dir_new git add $plat_dir_new for dir in $omaps; do mach_dir_new="arch/arm/$dir/include/mach" for header in $mach_files; do file="$mach_dir_new/$header" if [ ! -f $file ]; then echo -ne "/*\n * $file\n */\n\n#include <plat/$header>\n" > $file git add $file if [ ! -f $plat_dir_new/$header ]; then git mv $mach_dir_old/$header $plat_dir_new/$header fi fi done done Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap/include/plat')
-rw-r--r--arch/arm/plat-omap/include/plat/clkdev.h13
-rw-r--r--arch/arm/plat-omap/include/plat/gpio.h128
-rw-r--r--arch/arm/plat-omap/include/plat/hardware.h290
-rw-r--r--arch/arm/plat-omap/include/plat/io.h287
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h487
-rw-r--r--arch/arm/plat-omap/include/plat/memory.h96
-rw-r--r--arch/arm/plat-omap/include/plat/smp.h51
-rw-r--r--arch/arm/plat-omap/include/plat/system.h51
-rw-r--r--arch/arm/plat-omap/include/plat/timex.h41
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h84
10 files changed, 1528 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/plat/clkdev.h b/arch/arm/plat-omap/include/plat/clkdev.h
new file mode 100644
index 000000000000..730c49d1ebd8
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/clkdev.h
@@ -0,0 +1,13 @@
1#ifndef __MACH_CLKDEV_H
2#define __MACH_CLKDEV_H
3
4static inline int __clk_get(struct clk *clk)
5{
6 return 1;
7}
8
9static inline void __clk_put(struct clk *clk)
10{
11}
12
13#endif
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
new file mode 100644
index 000000000000..633ff688b928
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -0,0 +1,128 @@
1/*
2 * arch/arm/plat-omap/include/mach/gpio.h
3 *
4 * OMAP GPIO handling defines and functions
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 *
8 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#ifndef __ASM_ARCH_OMAP_GPIO_H
27#define __ASM_ARCH_OMAP_GPIO_H
28
29#include <linux/io.h>
30#include <mach/irqs.h>
31
32#define OMAP1_MPUIO_BASE 0xfffb5000
33
34#if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850))
35
36#define OMAP_MPUIO_INPUT_LATCH 0x00
37#define OMAP_MPUIO_OUTPUT 0x02
38#define OMAP_MPUIO_IO_CNTL 0x04
39#define OMAP_MPUIO_KBR_LATCH 0x08
40#define OMAP_MPUIO_KBC 0x0a
41#define OMAP_MPUIO_GPIO_EVENT_MODE 0x0c
42#define OMAP_MPUIO_GPIO_INT_EDGE 0x0e
43#define OMAP_MPUIO_KBD_INT 0x10
44#define OMAP_MPUIO_GPIO_INT 0x12
45#define OMAP_MPUIO_KBD_MASKIT 0x14
46#define OMAP_MPUIO_GPIO_MASKIT 0x16
47#define OMAP_MPUIO_GPIO_DEBOUNCING 0x18
48#define OMAP_MPUIO_LATCH 0x1a
49#else
50#define OMAP_MPUIO_INPUT_LATCH 0x00
51#define OMAP_MPUIO_OUTPUT 0x04
52#define OMAP_MPUIO_IO_CNTL 0x08
53#define OMAP_MPUIO_KBR_LATCH 0x10
54#define OMAP_MPUIO_KBC 0x14
55#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
56#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
57#define OMAP_MPUIO_KBD_INT 0x20
58#define OMAP_MPUIO_GPIO_INT 0x24
59#define OMAP_MPUIO_KBD_MASKIT 0x28
60#define OMAP_MPUIO_GPIO_MASKIT 0x2c
61#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
62#define OMAP_MPUIO_LATCH 0x34
63#endif
64
65#define OMAP34XX_NR_GPIOS 6
66
67#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
68#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
69
70#define OMAP_GPIO_IRQ(nr) (OMAP_GPIO_IS_MPUIO(nr) ? \
71 IH_MPUIO_BASE + ((nr) & 0x0f) : \
72 IH_GPIO_BASE + (nr))
73
74extern int omap_gpio_init(void); /* Call from board init only */
75extern void omap2_gpio_prepare_for_retention(void);
76extern void omap2_gpio_resume_after_retention(void);
77extern void omap_set_gpio_debounce(int gpio, int enable);
78extern void omap_set_gpio_debounce_time(int gpio, int enable);
79
80/*-------------------------------------------------------------------------*/
81
82/* Wrappers for "new style" GPIO calls, using the new infrastructure
83 * which lets us plug in FPGA, I2C, and other implementations.
84 * *
85 * The original OMAP-specfic calls should eventually be removed.
86 */
87
88#include <linux/errno.h>
89#include <asm-generic/gpio.h>
90
91static inline int gpio_get_value(unsigned gpio)
92{
93 return __gpio_get_value(gpio);
94}
95
96static inline void gpio_set_value(unsigned gpio, int value)
97{
98 __gpio_set_value(gpio, value);
99}
100
101static inline int gpio_cansleep(unsigned gpio)
102{
103 return __gpio_cansleep(gpio);
104}
105
106static inline int gpio_to_irq(unsigned gpio)
107{
108 return __gpio_to_irq(gpio);
109}
110
111static inline int irq_to_gpio(unsigned irq)
112{
113 int tmp;
114
115 /* omap1 SOC mpuio */
116 if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16)))
117 return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES;
118
119 /* SOC gpio */
120 tmp = irq - IH_GPIO_BASE;
121 if (tmp < OMAP_MAX_GPIO_LINES)
122 return tmp;
123
124 /* we don't supply reverse mappings for non-SOC gpios */
125 return -EIO;
126}
127
128#endif
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
new file mode 100644
index 000000000000..b3b713dc4b59
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -0,0 +1,290 @@
1/*
2 * arch/arm/plat-omap/include/mach/hardware.h
3 *
4 * Hardware definitions for TI OMAP processors and boards
5 *
6 * NOTE: Please put device driver specific defines into a separate header
7 * file for each driver.
8 *
9 * Copyright (C) 2001 RidgeRun, Inc.
10 * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
11 *
12 * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
13 * and Dirk Behme <dirk.behme@de.bosch.com>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 */
35
36#ifndef __ASM_ARCH_OMAP_HARDWARE_H
37#define __ASM_ARCH_OMAP_HARDWARE_H
38
39#include <asm/sizes.h>
40#ifndef __ASSEMBLER__
41#include <asm/types.h>
42#include <mach/cpu.h>
43#endif
44#include <mach/serial.h>
45
46/*
47 * ---------------------------------------------------------------------------
48 * Common definitions for all OMAP processors
49 * NOTE: Put all processor or board specific parts to the special header
50 * files.
51 * ---------------------------------------------------------------------------
52 */
53
54/*
55 * ----------------------------------------------------------------------------
56 * Timers
57 * ----------------------------------------------------------------------------
58 */
59#define OMAP_MPU_TIMER1_BASE (0xfffec500)
60#define OMAP_MPU_TIMER2_BASE (0xfffec600)
61#define OMAP_MPU_TIMER3_BASE (0xfffec700)
62#define MPU_TIMER_FREE (1 << 6)
63#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
64#define MPU_TIMER_AR (1 << 1)
65#define MPU_TIMER_ST (1 << 0)
66
67/*
68 * ----------------------------------------------------------------------------
69 * Clocks
70 * ----------------------------------------------------------------------------
71 */
72#define CLKGEN_REG_BASE (0xfffece00)
73#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
74#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
75#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
76#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
77#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
78#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
79#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
80#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
81
82#define CK_RATEF 1
83#define CK_IDLEF 2
84#define CK_ENABLEF 4
85#define CK_SELECTF 8
86#define SETARM_IDLE_SHIFT
87
88/* DPLL control registers */
89#define DPLL_CTL (0xfffecf00)
90
91/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
92#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
93#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
94#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
95#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
96#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
97
98/*
99 * ---------------------------------------------------------------------------
100 * UPLD
101 * ---------------------------------------------------------------------------
102 */
103#define ULPD_REG_BASE (0xfffe0800)
104#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
105#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
106#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
107# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
108# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
109#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
110# define SOFT_UDC_REQ (1 << 4)
111# define SOFT_USB_CLK_REQ (1 << 3)
112# define SOFT_DPLL_REQ (1 << 0)
113#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
114#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
115#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
116#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
117#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
118# define DIS_MMC2_DPLL_REQ (1 << 11)
119# define DIS_MMC1_DPLL_REQ (1 << 10)
120# define DIS_UART3_DPLL_REQ (1 << 9)
121# define DIS_UART2_DPLL_REQ (1 << 8)
122# define DIS_UART1_DPLL_REQ (1 << 7)
123# define DIS_USB_HOST_DPLL_REQ (1 << 6)
124#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
125#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
126
127/*
128 * ---------------------------------------------------------------------------
129 * Watchdog timer
130 * ---------------------------------------------------------------------------
131 */
132
133/* Watchdog timer within the OMAP3.2 gigacell */
134#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
135#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
136#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
137#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
138#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
139
140/*
141 * ---------------------------------------------------------------------------
142 * Interrupts
143 * ---------------------------------------------------------------------------
144 */
145#ifdef CONFIG_ARCH_OMAP1
146
147/*
148 * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
149 * or something similar.. -- PFM.
150 */
151
152#define OMAP_IH1_BASE 0xfffecb00
153#define OMAP_IH2_BASE 0xfffe0000
154
155#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
156#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
157#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
158#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
159#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
160#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
161#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
162
163#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
164#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
165#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
166#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
167#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
168#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
169#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
170
171#define IRQ_ITR_REG_OFFSET 0x00
172#define IRQ_MIR_REG_OFFSET 0x04
173#define IRQ_SIR_IRQ_REG_OFFSET 0x10
174#define IRQ_SIR_FIQ_REG_OFFSET 0x14
175#define IRQ_CONTROL_REG_OFFSET 0x18
176#define IRQ_ISR_REG_OFFSET 0x9c
177#define IRQ_ILR0_REG_OFFSET 0x1c
178#define IRQ_GMR_REG_OFFSET 0xa0
179
180#endif
181
182/*
183 * ----------------------------------------------------------------------------
184 * System control registers
185 * ----------------------------------------------------------------------------
186 */
187#define MOD_CONF_CTRL_0 0xfffe1080
188#define MOD_CONF_CTRL_1 0xfffe1110
189
190/*
191 * ----------------------------------------------------------------------------
192 * Pin multiplexing registers
193 * ----------------------------------------------------------------------------
194 */
195#define FUNC_MUX_CTRL_0 0xfffe1000
196#define FUNC_MUX_CTRL_1 0xfffe1004
197#define FUNC_MUX_CTRL_2 0xfffe1008
198#define COMP_MODE_CTRL_0 0xfffe100c
199#define FUNC_MUX_CTRL_3 0xfffe1010
200#define FUNC_MUX_CTRL_4 0xfffe1014
201#define FUNC_MUX_CTRL_5 0xfffe1018
202#define FUNC_MUX_CTRL_6 0xfffe101C
203#define FUNC_MUX_CTRL_7 0xfffe1020
204#define FUNC_MUX_CTRL_8 0xfffe1024
205#define FUNC_MUX_CTRL_9 0xfffe1028
206#define FUNC_MUX_CTRL_A 0xfffe102C
207#define FUNC_MUX_CTRL_B 0xfffe1030
208#define FUNC_MUX_CTRL_C 0xfffe1034
209#define FUNC_MUX_CTRL_D 0xfffe1038
210#define PULL_DWN_CTRL_0 0xfffe1040
211#define PULL_DWN_CTRL_1 0xfffe1044
212#define PULL_DWN_CTRL_2 0xfffe1048
213#define PULL_DWN_CTRL_3 0xfffe104c
214#define PULL_DWN_CTRL_4 0xfffe10ac
215
216/* OMAP-1610 specific multiplexing registers */
217#define FUNC_MUX_CTRL_E 0xfffe1090
218#define FUNC_MUX_CTRL_F 0xfffe1094
219#define FUNC_MUX_CTRL_10 0xfffe1098
220#define FUNC_MUX_CTRL_11 0xfffe109c
221#define FUNC_MUX_CTRL_12 0xfffe10a0
222#define PU_PD_SEL_0 0xfffe10b4
223#define PU_PD_SEL_1 0xfffe10b8
224#define PU_PD_SEL_2 0xfffe10bc
225#define PU_PD_SEL_3 0xfffe10c0
226#define PU_PD_SEL_4 0xfffe10c4
227
228/* Timer32K for 1610 and 1710*/
229#define OMAP_TIMER32K_BASE 0xFFFBC400
230
231/*
232 * ---------------------------------------------------------------------------
233 * TIPB bus interface
234 * ---------------------------------------------------------------------------
235 */
236#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
237#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
238#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
239#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
240
241/*
242 * ----------------------------------------------------------------------------
243 * MPUI interface
244 * ----------------------------------------------------------------------------
245 */
246#define MPUI_BASE (0xfffec900)
247#define MPUI_CTRL (MPUI_BASE + 0x0)
248#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
249#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
250#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
251#define MPUI_STATUS_REG (MPUI_BASE + 0x10)
252#define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
253#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
254#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
255
256/*
257 * ----------------------------------------------------------------------------
258 * LED Pulse Generator
259 * ----------------------------------------------------------------------------
260 */
261#define OMAP_LPG1_BASE 0xfffbd000
262#define OMAP_LPG2_BASE 0xfffbd800
263#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
264#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
265#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
266#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
267
268/*
269 * ----------------------------------------------------------------------------
270 * Pulse-Width Light
271 * ----------------------------------------------------------------------------
272 */
273#define OMAP_PWL_BASE 0xfffb5800
274#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)
275#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)
276
277/*
278 * ---------------------------------------------------------------------------
279 * Processor specific defines
280 * ---------------------------------------------------------------------------
281 */
282
283#include <mach/omap7xx.h>
284#include <mach/omap1510.h>
285#include <mach/omap16xx.h>
286#include <mach/omap24xx.h>
287#include <mach/omap34xx.h>
288#include <mach/omap44xx.h>
289
290#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
new file mode 100644
index 000000000000..7e5319f907d1
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -0,0 +1,287 @@
1/*
2 * arch/arm/plat-omap/include/mach/io.h
3 *
4 * IO definitions for TI OMAP processors and boards
5 *
6 * Copied from arch/arm/mach-sa1100/include/mach/io.h
7 * Copyright (C) 1997-1999 Russell King
8 *
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 *
32 * Modifications:
33 * 06-12-1997 RMK Created.
34 * 07-04-1999 RMK Major cleanup
35 */
36
37#ifndef __ASM_ARM_ARCH_IO_H
38#define __ASM_ARM_ARCH_IO_H
39
40#include <mach/hardware.h>
41
42#define IO_SPACE_LIMIT 0xffffffff
43
44/*
45 * We don't actually have real ISA nor PCI buses, but there is so many
46 * drivers out there that might just work if we fake them...
47 */
48#define __io(a) __typesafe_io(a)
49#define __mem_pci(a) (a)
50
51/*
52 * ----------------------------------------------------------------------------
53 * I/O mapping
54 * ----------------------------------------------------------------------------
55 */
56
57#ifdef __ASSEMBLER__
58#define IOMEM(x) (x)
59#else
60#define IOMEM(x) ((void __force __iomem *)(x))
61#endif
62
63#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
64#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
65
66#define OMAP2_L3_IO_OFFSET 0x90000000
67#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
68
69
70#define OMAP2_L4_IO_OFFSET 0xb2000000
71#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
72
73#define OMAP4_L3_IO_OFFSET 0xb4000000
74#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
75
76#define OMAP4_L3_PER_IO_OFFSET 0xb1100000
77#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
78
79#define OMAP4_GPMC_IO_OFFSET 0xa9000000
80#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
81
82#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
83#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
84
85/*
86 * ----------------------------------------------------------------------------
87 * Omap1 specific IO mapping
88 * ----------------------------------------------------------------------------
89 */
90
91#define OMAP1_IO_PHYS 0xFFFB0000
92#define OMAP1_IO_SIZE 0x40000
93#define OMAP1_IO_VIRT (OMAP1_IO_PHYS - OMAP1_IO_OFFSET)
94
95/*
96 * ----------------------------------------------------------------------------
97 * Omap2 specific IO mapping
98 * ----------------------------------------------------------------------------
99 */
100
101/* We map both L3 and L4 on OMAP2 */
102#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
103#define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
104#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
105#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
106#define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
107#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
108
109#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
110#define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
111#define L4_WK_243X_SIZE SZ_1M
112#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE
113#define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
114 /* 0x6e000000 --> 0xfe000000 */
115#define OMAP243X_GPMC_SIZE SZ_1M
116#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
117 /* 0x6D000000 --> 0xfd000000 */
118#define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
119#define OMAP243X_SDRC_SIZE SZ_1M
120#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
121 /* 0x6c000000 --> 0xfc000000 */
122#define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
123#define OMAP243X_SMS_SIZE SZ_1M
124
125/* DSP */
126#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
127#define DSP_MEM_24XX_VIRT 0xe0000000
128#define DSP_MEM_24XX_SIZE 0x28000
129#define DSP_IPI_24XX_PHYS OMAP2420_DSP_IPI_BASE /* 0x59000000 */
130#define DSP_IPI_24XX_VIRT 0xe1000000
131#define DSP_IPI_24XX_SIZE SZ_4K
132#define DSP_MMU_24XX_PHYS OMAP2420_DSP_MMU_BASE /* 0x5a000000 */
133#define DSP_MMU_24XX_VIRT 0xe2000000
134#define DSP_MMU_24XX_SIZE SZ_4K
135
136/*
137 * ----------------------------------------------------------------------------
138 * Omap3 specific IO mapping
139 * ----------------------------------------------------------------------------
140 */
141
142/* We map both L3 and L4 on OMAP3 */
143#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */
144#define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET)
145#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
146
147#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */
148#define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
149#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
150
151/*
152 * Need to look at the Size 4M for L4.
153 * VPOM3430 was not working for Int controller
154 */
155
156#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 --> 0xfa300000 */
157#define L4_WK_34XX_VIRT (L4_WK_34XX_PHYS + OMAP2_L4_IO_OFFSET)
158#define L4_WK_34XX_SIZE SZ_1M
159
160#define L4_PER_34XX_PHYS L4_PER_34XX_BASE
161 /* 0x49000000 --> 0xfb000000 */
162#define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
163#define L4_PER_34XX_SIZE SZ_1M
164
165#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE
166 /* 0x54000000 --> 0xfe800000 */
167#define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET)
168#define L4_EMU_34XX_SIZE SZ_8M
169
170#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE
171 /* 0x6e000000 --> 0xfe000000 */
172#define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
173#define OMAP34XX_GPMC_SIZE SZ_1M
174
175#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE
176 /* 0x6c000000 --> 0xfc000000 */
177#define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
178#define OMAP343X_SMS_SIZE SZ_1M
179
180#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE
181 /* 0x6D000000 --> 0xfd000000 */
182#define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
183#define OMAP343X_SDRC_SIZE SZ_1M
184
185/* DSP */
186#define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */
187#define DSP_MEM_34XX_VIRT 0xe0000000
188#define DSP_MEM_34XX_SIZE 0x28000
189#define DSP_IPI_34XX_PHYS OMAP34XX_DSP_IPI_BASE /* 0x59000000 */
190#define DSP_IPI_34XX_VIRT 0xe1000000
191#define DSP_IPI_34XX_SIZE SZ_4K
192#define DSP_MMU_34XX_PHYS OMAP34XX_DSP_MMU_BASE /* 0x5a000000 */
193#define DSP_MMU_34XX_VIRT 0xe2000000
194#define DSP_MMU_34XX_SIZE SZ_4K
195
196/*
197 * ----------------------------------------------------------------------------
198 * Omap4 specific IO mapping
199 * ----------------------------------------------------------------------------
200 */
201
202/* We map both L3 and L4 on OMAP4 */
203#define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */
204#define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET)
205#define L3_44XX_SIZE SZ_1M
206
207#define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */
208#define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
209#define L4_44XX_SIZE SZ_4M
210
211
212#define L4_WK_44XX_PHYS L4_WK_44XX_BASE /* 0x4a300000 --> 0xfc300000 */
213#define L4_WK_44XX_VIRT (L4_WK_44XX_PHYS + OMAP2_L4_IO_OFFSET)
214#define L4_WK_44XX_SIZE SZ_1M
215
216#define L4_PER_44XX_PHYS L4_PER_44XX_BASE
217 /* 0x48000000 --> 0xfa000000 */
218#define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
219#define L4_PER_44XX_SIZE SZ_4M
220
221#define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE
222 /* 0x49000000 --> 0xfb000000 */
223#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
224#define L4_ABE_44XX_SIZE SZ_1M
225
226#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE
227 /* 0x54000000 --> 0xfe800000 */
228#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
229#define L4_EMU_44XX_SIZE SZ_8M
230
231#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE
232 /* 0x50000000 --> 0xf9000000 */
233#define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET)
234#define OMAP44XX_GPMC_SIZE SZ_1M
235
236
237#define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE
238 /* 0x4c000000 --> 0xfd100000 */
239#define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
240#define OMAP44XX_EMIF1_SIZE SZ_1M
241
242#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
243 /* 0x4d000000 --> 0xfd200000 */
244#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
245#define OMAP44XX_EMIF2_SIZE SZ_1M
246
247#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
248 /* 0x4e000000 --> 0xfd300000 */
249#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
250#define OMAP44XX_DMM_SIZE SZ_1M
251/*
252 * ----------------------------------------------------------------------------
253 * Omap specific register access
254 * ----------------------------------------------------------------------------
255 */
256
257#ifndef __ASSEMBLER__
258
259/*
260 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
261 */
262
263extern u8 omap_readb(u32 pa);
264extern u16 omap_readw(u32 pa);
265extern u32 omap_readl(u32 pa);
266extern void omap_writeb(u8 v, u32 pa);
267extern void omap_writew(u16 v, u32 pa);
268extern void omap_writel(u32 v, u32 pa);
269
270struct omap_sdrc_params;
271
272extern void omap1_map_common_io(void);
273extern void omap1_init_common_hw(void);
274
275extern void omap2_map_common_io(void);
276extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
277 struct omap_sdrc_params *sdrc_cs1);
278
279#define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
280#define __arch_iounmap(v) omap_iounmap(v)
281
282void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
283void omap_iounmap(volatile void __iomem *addr);
284
285#endif
286
287#endif
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
new file mode 100644
index 000000000000..6a6d0281e1d5
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -0,0 +1,487 @@
1/*
2 * arch/arm/plat-omap/include/mach/irqs.h
3 *
4 * Copyright (C) Greg Lonnon 2001
5 * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
25 * are different.
26 */
27
28#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
29#define __ASM_ARCH_OMAP15XX_IRQS_H
30
31/*
32 * IRQ numbers for interrupt handler 1
33 *
34 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
35 *
36 */
37#define INT_CAMERA 1
38#define INT_FIQ 3
39#define INT_RTDX 6
40#define INT_DSP_MMU_ABORT 7
41#define INT_HOST 8
42#define INT_ABORT 9
43#define INT_BRIDGE_PRIV 13
44#define INT_GPIO_BANK1 14
45#define INT_UART3 15
46#define INT_TIMER3 16
47#define INT_DMA_CH0_6 19
48#define INT_DMA_CH1_7 20
49#define INT_DMA_CH2_8 21
50#define INT_DMA_CH3 22
51#define INT_DMA_CH4 23
52#define INT_DMA_CH5 24
53#define INT_DMA_LCD 25
54#define INT_TIMER1 26
55#define INT_WD_TIMER 27
56#define INT_BRIDGE_PUB 28
57#define INT_TIMER2 30
58#define INT_LCD_CTRL 31
59
60/*
61 * OMAP-1510 specific IRQ numbers for interrupt handler 1
62 */
63#define INT_1510_IH2_IRQ 0
64#define INT_1510_RES2 2
65#define INT_1510_SPI_TX 4
66#define INT_1510_SPI_RX 5
67#define INT_1510_DSP_MAILBOX1 10
68#define INT_1510_DSP_MAILBOX2 11
69#define INT_1510_RES12 12
70#define INT_1510_LB_MMU 17
71#define INT_1510_RES18 18
72#define INT_1510_LOCAL_BUS 29
73
74/*
75 * OMAP-1610 specific IRQ numbers for interrupt handler 1
76 */
77#define INT_1610_IH2_IRQ 0
78#define INT_1610_IH2_FIQ 2
79#define INT_1610_McBSP2_TX 4
80#define INT_1610_McBSP2_RX 5
81#define INT_1610_DSP_MAILBOX1 10
82#define INT_1610_DSP_MAILBOX2 11
83#define INT_1610_LCD_LINE 12
84#define INT_1610_GPTIMER1 17
85#define INT_1610_GPTIMER2 18
86#define INT_1610_SSR_FIFO_0 29
87
88/*
89 * OMAP-7xx specific IRQ numbers for interrupt handler 1
90 */
91#define INT_7XX_IH2_FIQ 0
92#define INT_7XX_IH2_IRQ 1
93#define INT_7XX_USB_NON_ISO 2
94#define INT_7XX_USB_ISO 3
95#define INT_7XX_ICR 4
96#define INT_7XX_EAC 5
97#define INT_7XX_GPIO_BANK1 6
98#define INT_7XX_GPIO_BANK2 7
99#define INT_7XX_GPIO_BANK3 8
100#define INT_7XX_McBSP2TX 10
101#define INT_7XX_McBSP2RX 11
102#define INT_7XX_McBSP2RX_OVF 12
103#define INT_7XX_LCD_LINE 14
104#define INT_7XX_GSM_PROTECT 15
105#define INT_7XX_TIMER3 16
106#define INT_7XX_GPIO_BANK5 17
107#define INT_7XX_GPIO_BANK6 18
108#define INT_7XX_SPGIO_WR 29
109
110/*
111 * IRQ numbers for interrupt handler 2
112 *
113 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
114 */
115#define IH2_BASE 32
116
117#define INT_KEYBOARD (1 + IH2_BASE)
118#define INT_uWireTX (2 + IH2_BASE)
119#define INT_uWireRX (3 + IH2_BASE)
120#define INT_I2C (4 + IH2_BASE)
121#define INT_MPUIO (5 + IH2_BASE)
122#define INT_USB_HHC_1 (6 + IH2_BASE)
123#define INT_McBSP3TX (10 + IH2_BASE)
124#define INT_McBSP3RX (11 + IH2_BASE)
125#define INT_McBSP1TX (12 + IH2_BASE)
126#define INT_McBSP1RX (13 + IH2_BASE)
127#define INT_UART1 (14 + IH2_BASE)
128#define INT_UART2 (15 + IH2_BASE)
129#define INT_BT_MCSI1TX (16 + IH2_BASE)
130#define INT_BT_MCSI1RX (17 + IH2_BASE)
131#define INT_SOSSI_MATCH (19 + IH2_BASE)
132#define INT_USB_W2FC (20 + IH2_BASE)
133#define INT_1WIRE (21 + IH2_BASE)
134#define INT_OS_TIMER (22 + IH2_BASE)
135#define INT_MMC (23 + IH2_BASE)
136#define INT_GAUGE_32K (24 + IH2_BASE)
137#define INT_RTC_TIMER (25 + IH2_BASE)
138#define INT_RTC_ALARM (26 + IH2_BASE)
139#define INT_MEM_STICK (27 + IH2_BASE)
140
141/*
142 * OMAP-1510 specific IRQ numbers for interrupt handler 2
143 */
144#define INT_1510_DSP_MMU (28 + IH2_BASE)
145#define INT_1510_COM_SPI_RO (31 + IH2_BASE)
146
147/*
148 * OMAP-1610 specific IRQ numbers for interrupt handler 2
149 */
150#define INT_1610_FAC (0 + IH2_BASE)
151#define INT_1610_USB_HHC_2 (7 + IH2_BASE)
152#define INT_1610_USB_OTG (8 + IH2_BASE)
153#define INT_1610_SoSSI (9 + IH2_BASE)
154#define INT_1610_SoSSI_MATCH (19 + IH2_BASE)
155#define INT_1610_DSP_MMU (28 + IH2_BASE)
156#define INT_1610_McBSP2RX_OF (31 + IH2_BASE)
157#define INT_1610_STI (32 + IH2_BASE)
158#define INT_1610_STI_WAKEUP (33 + IH2_BASE)
159#define INT_1610_GPTIMER3 (34 + IH2_BASE)
160#define INT_1610_GPTIMER4 (35 + IH2_BASE)
161#define INT_1610_GPTIMER5 (36 + IH2_BASE)
162#define INT_1610_GPTIMER6 (37 + IH2_BASE)
163#define INT_1610_GPTIMER7 (38 + IH2_BASE)
164#define INT_1610_GPTIMER8 (39 + IH2_BASE)
165#define INT_1610_GPIO_BANK2 (40 + IH2_BASE)
166#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
167#define INT_1610_MMC2 (42 + IH2_BASE)
168#define INT_1610_CF (43 + IH2_BASE)
169#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
170#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
171#define INT_1610_SPI (49 + IH2_BASE)
172#define INT_1610_DMA_CH6 (53 + IH2_BASE)
173#define INT_1610_DMA_CH7 (54 + IH2_BASE)
174#define INT_1610_DMA_CH8 (55 + IH2_BASE)
175#define INT_1610_DMA_CH9 (56 + IH2_BASE)
176#define INT_1610_DMA_CH10 (57 + IH2_BASE)
177#define INT_1610_DMA_CH11 (58 + IH2_BASE)
178#define INT_1610_DMA_CH12 (59 + IH2_BASE)
179#define INT_1610_DMA_CH13 (60 + IH2_BASE)
180#define INT_1610_DMA_CH14 (61 + IH2_BASE)
181#define INT_1610_DMA_CH15 (62 + IH2_BASE)
182#define INT_1610_NAND (63 + IH2_BASE)
183#define INT_1610_SHA1MD5 (91 + IH2_BASE)
184
185/*
186 * OMAP-7xx specific IRQ numbers for interrupt handler 2
187 */
188#define INT_7XX_HW_ERRORS (0 + IH2_BASE)
189#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE)
190#define INT_7XX_CFCD (2 + IH2_BASE)
191#define INT_7XX_CFIREQ (3 + IH2_BASE)
192#define INT_7XX_I2C (4 + IH2_BASE)
193#define INT_7XX_PCC (5 + IH2_BASE)
194#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE)
195#define INT_7XX_SPI_100K_1 (7 + IH2_BASE)
196#define INT_7XX_SYREN_SPI (8 + IH2_BASE)
197#define INT_7XX_VLYNQ (9 + IH2_BASE)
198#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE)
199#define INT_7XX_McBSP1TX (11 + IH2_BASE)
200#define INT_7XX_McBSP1RX (12 + IH2_BASE)
201#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
202#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
203#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE)
204#define INT_7XX_MCSI (16 + IH2_BASE)
205#define INT_7XX_uWireTX (17 + IH2_BASE)
206#define INT_7XX_uWireRX (18 + IH2_BASE)
207#define INT_7XX_SMC_CD (19 + IH2_BASE)
208#define INT_7XX_SMC_IREQ (20 + IH2_BASE)
209#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE)
210#define INT_7XX_TIMER32K (22 + IH2_BASE)
211#define INT_7XX_MMC_SDIO (23 + IH2_BASE)
212#define INT_7XX_UPLD (24 + IH2_BASE)
213#define INT_7XX_USB_HHC_1 (27 + IH2_BASE)
214#define INT_7XX_USB_HHC_2 (28 + IH2_BASE)
215#define INT_7XX_USB_GENI (29 + IH2_BASE)
216#define INT_7XX_USB_OTG (30 + IH2_BASE)
217#define INT_7XX_CAMERA_IF (31 + IH2_BASE)
218#define INT_7XX_RNG (32 + IH2_BASE)
219#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
220#define INT_7XX_DBB_RF_EN (34 + IH2_BASE)
221#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE)
222#define INT_7XX_SHA1_MD5 (36 + IH2_BASE)
223#define INT_7XX_SPI_100K_2 (37 + IH2_BASE)
224#define INT_7XX_RNG_IDLE (38 + IH2_BASE)
225#define INT_7XX_MPUIO (39 + IH2_BASE)
226#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
227#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
228#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
229#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE)
230#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
231#define INT_7XX_DMA_CH6 (53 + IH2_BASE)
232#define INT_7XX_DMA_CH7 (54 + IH2_BASE)
233#define INT_7XX_DMA_CH8 (55 + IH2_BASE)
234#define INT_7XX_DMA_CH9 (56 + IH2_BASE)
235#define INT_7XX_DMA_CH10 (57 + IH2_BASE)
236#define INT_7XX_DMA_CH11 (58 + IH2_BASE)
237#define INT_7XX_DMA_CH12 (59 + IH2_BASE)
238#define INT_7XX_DMA_CH13 (60 + IH2_BASE)
239#define INT_7XX_DMA_CH14 (61 + IH2_BASE)
240#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
241#define INT_7XX_NAND (63 + IH2_BASE)
242
243#define INT_24XX_SYS_NIRQ 7
244#define INT_24XX_SDMA_IRQ0 12
245#define INT_24XX_SDMA_IRQ1 13
246#define INT_24XX_SDMA_IRQ2 14
247#define INT_24XX_SDMA_IRQ3 15
248#define INT_24XX_CAM_IRQ 24
249#define INT_24XX_DSS_IRQ 25
250#define INT_24XX_MAIL_U0_MPU 26
251#define INT_24XX_DSP_UMA 27
252#define INT_24XX_DSP_MMU 28
253#define INT_24XX_GPIO_BANK1 29
254#define INT_24XX_GPIO_BANK2 30
255#define INT_24XX_GPIO_BANK3 31
256#define INT_24XX_GPIO_BANK4 32
257#define INT_24XX_GPIO_BANK5 33
258#define INT_24XX_MAIL_U3_MPU 34
259#define INT_24XX_GPTIMER1 37
260#define INT_24XX_GPTIMER2 38
261#define INT_24XX_GPTIMER3 39
262#define INT_24XX_GPTIMER4 40
263#define INT_24XX_GPTIMER5 41
264#define INT_24XX_GPTIMER6 42
265#define INT_24XX_GPTIMER7 43
266#define INT_24XX_GPTIMER8 44
267#define INT_24XX_GPTIMER9 45
268#define INT_24XX_GPTIMER10 46
269#define INT_24XX_GPTIMER11 47
270#define INT_24XX_GPTIMER12 48
271#define INT_24XX_SHA1MD5 51
272#define INT_24XX_MCBSP4_IRQ_TX 54
273#define INT_24XX_MCBSP4_IRQ_RX 55
274#define INT_24XX_I2C1_IRQ 56
275#define INT_24XX_I2C2_IRQ 57
276#define INT_24XX_HDQ_IRQ 58
277#define INT_24XX_MCBSP1_IRQ_TX 59
278#define INT_24XX_MCBSP1_IRQ_RX 60
279#define INT_24XX_MCBSP2_IRQ_TX 62
280#define INT_24XX_MCBSP2_IRQ_RX 63
281#define INT_24XX_SPI1_IRQ 65
282#define INT_24XX_SPI2_IRQ 66
283#define INT_24XX_UART1_IRQ 72
284#define INT_24XX_UART2_IRQ 73
285#define INT_24XX_UART3_IRQ 74
286#define INT_24XX_USB_IRQ_GEN 75
287#define INT_24XX_USB_IRQ_NISO 76
288#define INT_24XX_USB_IRQ_ISO 77
289#define INT_24XX_USB_IRQ_HGEN 78
290#define INT_24XX_USB_IRQ_HSOF 79
291#define INT_24XX_USB_IRQ_OTG 80
292#define INT_24XX_MCBSP5_IRQ_TX 81
293#define INT_24XX_MCBSP5_IRQ_RX 82
294#define INT_24XX_MMC_IRQ 83
295#define INT_24XX_MMC2_IRQ 86
296#define INT_24XX_MCBSP3_IRQ_TX 89
297#define INT_24XX_MCBSP3_IRQ_RX 90
298#define INT_24XX_SPI3_IRQ 91
299
300#define INT_243X_MCBSP2_IRQ 16
301#define INT_243X_MCBSP3_IRQ 17
302#define INT_243X_MCBSP4_IRQ 18
303#define INT_243X_MCBSP5_IRQ 19
304#define INT_243X_MCBSP1_IRQ 64
305#define INT_243X_HS_USB_MC 92
306#define INT_243X_HS_USB_DMA 93
307#define INT_243X_CARKIT_IRQ 94
308
309#define INT_34XX_BENCH_MPU_EMUL 3
310#define INT_34XX_ST_MCBSP2_IRQ 4
311#define INT_34XX_ST_MCBSP3_IRQ 5
312#define INT_34XX_SSM_ABORT_IRQ 6
313#define INT_34XX_SYS_NIRQ 7
314#define INT_34XX_D2D_FW_IRQ 8
315#define INT_34XX_PRCM_MPU_IRQ 11
316#define INT_34XX_MCBSP1_IRQ 16
317#define INT_34XX_MCBSP2_IRQ 17
318#define INT_34XX_MCBSP3_IRQ 22
319#define INT_34XX_MCBSP4_IRQ 23
320#define INT_34XX_CAM_IRQ 24
321#define INT_34XX_MCBSP5_IRQ 27
322#define INT_34XX_GPIO_BANK1 29
323#define INT_34XX_GPIO_BANK2 30
324#define INT_34XX_GPIO_BANK3 31
325#define INT_34XX_GPIO_BANK4 32
326#define INT_34XX_GPIO_BANK5 33
327#define INT_34XX_GPIO_BANK6 34
328#define INT_34XX_USIM_IRQ 35
329#define INT_34XX_WDT3_IRQ 36
330#define INT_34XX_SPI4_IRQ 48
331#define INT_34XX_SHA1MD52_IRQ 49
332#define INT_34XX_FPKA_READY_IRQ 50
333#define INT_34XX_SHA1MD51_IRQ 51
334#define INT_34XX_RNG_IRQ 52
335#define INT_34XX_I2C3_IRQ 61
336#define INT_34XX_FPKA_ERROR_IRQ 64
337#define INT_34XX_PBIAS_IRQ 75
338#define INT_34XX_OHCI_IRQ 76
339#define INT_34XX_EHCI_IRQ 77
340#define INT_34XX_TLL_IRQ 78
341#define INT_34XX_PARTHASH_IRQ 79
342#define INT_34XX_MMC3_IRQ 94
343#define INT_34XX_GPT12_IRQ 95
344
345#define INT_34XX_BENCH_MPU_EMUL 3
346
347
348#define IRQ_GIC_START 32
349#define INT_44XX_LOCALTIMER_IRQ 29
350#define INT_44XX_LOCALWDT_IRQ 30
351
352#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START)
353#define INT_44XX_SSM_ABORT_IRQ (6 + IRQ_GIC_START)
354#define INT_44XX_SYS_NIRQ (7 + IRQ_GIC_START)
355#define INT_44XX_D2D_FW_IRQ (8 + IRQ_GIC_START)
356#define INT_44XX_PRCM_MPU_IRQ (11 + IRQ_GIC_START)
357#define INT_44XX_SDMA_IRQ0 (12 + IRQ_GIC_START)
358#define INT_44XX_SDMA_IRQ1 (13 + IRQ_GIC_START)
359#define INT_44XX_SDMA_IRQ2 (14 + IRQ_GIC_START)
360#define INT_44XX_SDMA_IRQ3 (15 + IRQ_GIC_START)
361#define INT_44XX_ISS_IRQ (24 + IRQ_GIC_START)
362#define INT_44XX_DSS_IRQ (25 + IRQ_GIC_START)
363#define INT_44XX_MAIL_U0_MPU (26 + IRQ_GIC_START)
364#define INT_44XX_DSP_MMU (28 + IRQ_GIC_START)
365#define INT_44XX_GPTIMER1 (37 + IRQ_GIC_START)
366#define INT_44XX_GPTIMER2 (38 + IRQ_GIC_START)
367#define INT_44XX_GPTIMER3 (39 + IRQ_GIC_START)
368#define INT_44XX_GPTIMER4 (40 + IRQ_GIC_START)
369#define INT_44XX_GPTIMER5 (41 + IRQ_GIC_START)
370#define INT_44XX_GPTIMER6 (42 + IRQ_GIC_START)
371#define INT_44XX_GPTIMER7 (43 + IRQ_GIC_START)
372#define INT_44XX_GPTIMER8 (44 + IRQ_GIC_START)
373#define INT_44XX_GPTIMER9 (45 + IRQ_GIC_START)
374#define INT_44XX_GPTIMER10 (46 + IRQ_GIC_START)
375#define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START)
376#define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START)
377#define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START)
378#define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START)
379#define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START)
380#define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START)
381#define INT_44XX_SPI1_IRQ (65 + IRQ_GIC_START)
382#define INT_44XX_SPI2_IRQ (66 + IRQ_GIC_START)
383#define INT_44XX_HSI_1_IRQ0 (67 + IRQ_GIC_START)
384#define INT_44XX_HSI_2_IRQ1 (68 + IRQ_GIC_START)
385#define INT_44XX_HSI_1_DMAIRQ (71 + IRQ_GIC_START)
386#define INT_44XX_UART1_IRQ (72 + IRQ_GIC_START)
387#define INT_44XX_UART2_IRQ (73 + IRQ_GIC_START)
388#define INT_44XX_UART3_IRQ (74 + IRQ_GIC_START)
389#define INT_44XX_UART4_IRQ (70 + IRQ_GIC_START)
390#define INT_44XX_USB_IRQ_NISO (76 + IRQ_GIC_START)
391#define INT_44XX_USB_IRQ_ISO (77 + IRQ_GIC_START)
392#define INT_44XX_USB_IRQ_HGEN (78 + IRQ_GIC_START)
393#define INT_44XX_USB_IRQ_HSOF (79 + IRQ_GIC_START)
394#define INT_44XX_USB_IRQ_OTG (80 + IRQ_GIC_START)
395#define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START)
396#define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START)
397#define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START)
398#define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START)
399#define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START)
400#define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START)
401#define INT_44XX_SPI3_IRQ (91 + IRQ_GIC_START)
402#define INT_44XX_SPI5_IRQ (69 + IRQ_GIC_START)
403
404#define INT_44XX_MCBSP5_IRQ (16 + IRQ_GIC_START)
405#define INT_44xX_MCBSP1_IRQ (17 + IRQ_GIC_START)
406#define INT_44XX_MCBSP2_IRQ (22 + IRQ_GIC_START)
407#define INT_44XX_MCBSP3_IRQ (23 + IRQ_GIC_START)
408#define INT_44XX_MCBSP4_IRQ (27 + IRQ_GIC_START)
409#define INT_44XX_HS_USB_MC (92 + IRQ_GIC_START)
410#define INT_44XX_HS_USB_DMA (93 + IRQ_GIC_START)
411
412#define INT_44XX_GPIO_BANK1 (29 + IRQ_GIC_START)
413#define INT_44XX_GPIO_BANK2 (30 + IRQ_GIC_START)
414#define INT_44XX_GPIO_BANK3 (31 + IRQ_GIC_START)
415#define INT_44XX_GPIO_BANK4 (32 + IRQ_GIC_START)
416#define INT_44XX_GPIO_BANK5 (33 + IRQ_GIC_START)
417#define INT_44XX_GPIO_BANK6 (34 + IRQ_GIC_START)
418#define INT_44XX_USIM_IRQ (35 + IRQ_GIC_START)
419#define INT_44XX_WDT3_IRQ (36 + IRQ_GIC_START)
420#define INT_44XX_SPI4_IRQ (48 + IRQ_GIC_START)
421#define INT_44XX_SHA1MD52_IRQ (49 + IRQ_GIC_START)
422#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START)
423#define INT_44XX_SHA1MD51_IRQ (51 + IRQ_GIC_START)
424#define INT_44XX_RNG_IRQ (52 + IRQ_GIC_START)
425#define INT_44XX_MMC5_IRQ (59 + IRQ_GIC_START)
426#define INT_44XX_I2C3_IRQ (61 + IRQ_GIC_START)
427#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START)
428#define INT_44XX_PBIAS_IRQ (75 + IRQ_GIC_START)
429#define INT_44XX_OHCI_IRQ (76 + IRQ_GIC_START)
430#define INT_44XX_EHCI_IRQ (77 + IRQ_GIC_START)
431#define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START)
432#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START)
433#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START)
434#define INT_44XX_MMC4_IRQ (96 + IRQ_GIC_START)
435
436
437/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
438 * 16 MPUIO lines */
439#define OMAP_MAX_GPIO_LINES 192
440#define IH_GPIO_BASE (128 + IH2_BASE)
441#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
442#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
443
444/* External FPGA handles interrupts on Innovator boards */
445#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
446#ifdef CONFIG_MACH_OMAP_INNOVATOR
447#define OMAP_FPGA_NR_IRQS 24
448#else
449#define OMAP_FPGA_NR_IRQS 0
450#endif
451#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
452
453/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
454#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END)
455#ifdef CONFIG_TWL4030_CORE
456#define TWL4030_BASE_NR_IRQS 8
457#define TWL4030_PWR_NR_IRQS 8
458#else
459#define TWL4030_BASE_NR_IRQS 0
460#define TWL4030_PWR_NR_IRQS 0
461#endif
462#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
463#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END
464#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
465
466/* External TWL4030 gpio interrupts are optional */
467#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END
468#ifdef CONFIG_GPIO_TWL4030
469#define TWL4030_GPIO_NR_IRQS 18
470#else
471#define TWL4030_GPIO_NR_IRQS 0
472#endif
473#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
474
475/* Total number of interrupts depends on the enabled blocks above */
476#define NR_IRQS TWL4030_GPIO_IRQ_END
477
478#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
479
480#ifndef __ASSEMBLY__
481extern void omap_init_irq(void);
482extern int omap_irq_pending(void);
483#endif
484
485#include <mach/hardware.h>
486
487#endif
diff --git a/arch/arm/plat-omap/include/plat/memory.h b/arch/arm/plat-omap/include/plat/memory.h
new file mode 100644
index 000000000000..9ad41dc484c1
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/memory.h
@@ -0,0 +1,96 @@
1/*
2 * arch/arm/plat-omap/include/mach/memory.h
3 *
4 * Memory map for OMAP-1510 and 1610
5 *
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Author: Greg Lonnon <glonnon@ridgerun.com>
8 *
9 * This file was derived from arch/arm/mach-intergrator/include/mach/memory.h
10 * Copyright (C) 1999 ARM Limited
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32
33#ifndef __ASM_ARCH_MEMORY_H
34#define __ASM_ARCH_MEMORY_H
35
36/*
37 * Physical DRAM offset.
38 */
39#if defined(CONFIG_ARCH_OMAP1)
40#define PHYS_OFFSET UL(0x10000000)
41#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
42 defined(CONFIG_ARCH_OMAP4)
43#define PHYS_OFFSET UL(0x80000000)
44#endif
45
46/*
47 * Bus address is physical address, except for OMAP-1510 Local Bus.
48 * OMAP-1510 bus address is translated into a Local Bus address if the
49 * OMAP bus type is lbus. We do the address translation based on the
50 * device overriding the defaults used in the dma-mapping API.
51 * Note that the is_lbus_device() test is not very efficient on 1510
52 * because of the strncmp().
53 */
54#ifdef CONFIG_ARCH_OMAP15XX
55
56/*
57 * OMAP-1510 Local Bus address offset
58 */
59#define OMAP1510_LB_OFFSET UL(0x30000000)
60
61#define virt_to_lbus(x) ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
62#define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
63#define is_lbus_device(dev) (cpu_is_omap15xx() && dev && (strncmp(dev_name(dev), "ohci", 4) == 0))
64
65#define __arch_page_to_dma(dev, page) \
66 ({ dma_addr_t __dma = page_to_phys(page); \
67 if (is_lbus_device(dev)) \
68 __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \
69 __dma; })
70
71#define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \
72 lbus_to_virt(addr) : \
73 __phys_to_virt(addr)); })
74
75#define __arch_virt_to_dma(dev, addr) ({ unsigned long __addr = (unsigned long)(addr); \
76 (dma_addr_t) (is_lbus_device(dev) ? \
77 virt_to_lbus(__addr) : \
78 __virt_to_phys(__addr)); })
79
80#endif /* CONFIG_ARCH_OMAP15XX */
81
82/* Override the ARM default */
83#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
84
85#if (CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE == 0)
86#undef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
87#define CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE 2
88#endif
89
90#define CONSISTENT_DMA_SIZE \
91 (((CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE + 1) & ~1) * 1024 * 1024)
92
93#endif
94
95#endif
96
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
new file mode 100644
index 000000000000..dcaa8fde7063
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -0,0 +1,51 @@
1/*
2 * OMAP4 machine specific smp.h
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc.
5 *
6 * Author:
7 * Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
9 * Interface functions needed for the SMP. This file is based on arm
10 * realview smp platform.
11 * Copyright (c) 2003 ARM Limited.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17#ifndef OMAP_ARCH_SMP_H
18#define OMAP_ARCH_SMP_H
19
20#include <asm/hardware/gic.h>
21
22/*
23 * set_event() is used to wake up secondary core from wfe using sev. ROM
24 * code puts the second core into wfe(standby).
25 *
26 */
27#define set_event() __asm__ __volatile__ ("sev" : : : "memory")
28
29/* Needed for secondary core boot */
30extern void omap_secondary_startup(void);
31
32/*
33 * We use Soft IRQ1 as the IPI
34 */
35static inline void smp_cross_call(const struct cpumask *mask)
36{
37 gic_raise_softirq(mask, 1);
38}
39
40/*
41 * Read MPIDR: Multiprocessor affinity register
42 */
43#define hard_smp_processor_id() \
44 ({ \
45 unsigned int cpunum; \
46 __asm__("mrc p15, 0, %0, c0, c0, 5" \
47 : "=r" (cpunum)); \
48 cpunum &= 0x0F; \
49 })
50
51#endif
diff --git a/arch/arm/plat-omap/include/plat/system.h b/arch/arm/plat-omap/include/plat/system.h
new file mode 100644
index 000000000000..ed8ec7477261
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/system.h
@@ -0,0 +1,51 @@
1/*
2 * Copied from arch/arm/mach-sa1100/include/mach/system.h
3 * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
4 */
5#ifndef __ASM_ARCH_SYSTEM_H
6#define __ASM_ARCH_SYSTEM_H
7#include <linux/clk.h>
8
9#include <asm/mach-types.h>
10#include <mach/hardware.h>
11
12#include <mach/prcm.h>
13
14#ifndef CONFIG_MACH_VOICEBLUE
15#define voiceblue_reset() do {} while (0)
16#else
17extern void voiceblue_reset(void);
18#endif
19
20static inline void arch_idle(void)
21{
22 cpu_do_idle();
23}
24
25static inline void omap1_arch_reset(char mode)
26{
27 /*
28 * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
29 * "Global Software Reset Affects Traffic Controller Frequency".
30 */
31 if (cpu_is_omap5912()) {
32 omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
33 DPLL_CTL);
34 omap_writew(0x8, ARM_RSTCT1);
35 }
36
37 if (machine_is_voiceblue())
38 voiceblue_reset();
39 else
40 omap_writew(1, ARM_RSTCT1);
41}
42
43static inline void arch_reset(char mode, const char *cmd)
44{
45 if (!cpu_class_is_omap2())
46 omap1_arch_reset(mode);
47 else
48 omap_prcm_arch_reset(mode);
49}
50
51#endif
diff --git a/arch/arm/plat-omap/include/plat/timex.h b/arch/arm/plat-omap/include/plat/timex.h
new file mode 100644
index 000000000000..6d35767bc48f
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/timex.h
@@ -0,0 +1,41 @@
1/*
2 * arch/arm/plat-omap/include/mach/timex.h
3 *
4 * Copyright (C) 2000 RidgeRun, Inc.
5 * Author: Greg Lonnon <glonnon@ridgerun.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#if !defined(__ASM_ARCH_OMAP_TIMEX_H)
29#define __ASM_ARCH_OMAP_TIMEX_H
30
31/*
32 * OMAP 32KHz timer updates time one jiffie at a time from a secondary timer,
33 * and that's why the CLOCK_TICK_RATE is not 32768.
34 */
35#ifdef CONFIG_OMAP_32K_TIMER
36#define CLOCK_TICK_RATE (CONFIG_OMAP_32K_TIMER_HZ)
37#else
38#define CLOCK_TICK_RATE (HZ * 100000UL)
39#endif
40
41#endif /* __ASM_ARCH_OMAP_TIMEX_H */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
new file mode 100644
index 000000000000..ddf7b88dec4d
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -0,0 +1,84 @@
1/*
2 * arch/arm/plat-omap/include/mach/uncompress.h
3 *
4 * Serial port stubs for kernel decompress status messages
5 *
6 * Initially based on:
7 * linux-2.4.15-rmk1-dsplinux1.6/arch/arm/plat-omap/include/mach1510/uncompress.h
8 * Copyright (C) 2000 RidgeRun, Inc.
9 * Author: Greg Lonnon <glonnon@ridgerun.com>
10 *
11 * Rewritten by:
12 * Author: <source@mvista.com>
13 * 2004 (c) MontaVista Software, Inc.
14 *
15 * This file is licensed under the terms of the GNU General Public License
16 * version 2. This program is licensed "as is" without any warranty of any
17 * kind, whether express or implied.
18 */
19
20#include <linux/types.h>
21#include <linux/serial_reg.h>
22#include <mach/serial.h>
23
24unsigned int system_rev;
25
26#define UART_OMAP_MDR1 0x08 /* mode definition register */
27#define OMAP_ID_730 0x355F
28#define OMAP_ID_850 0x362C
29#define ID_MASK 0x7fff
30#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
31#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
32
33static void putc(int c)
34{
35 volatile u8 * uart = 0;
36 int shift = 2;
37
38#ifdef CONFIG_MACH_OMAP_PALMTE
39 return;
40#endif
41
42#ifdef CONFIG_ARCH_OMAP
43#ifdef CONFIG_OMAP_LL_DEBUG_UART3
44 uart = (volatile u8 *)(OMAP_UART3_BASE);
45#elif defined(CONFIG_OMAP_LL_DEBUG_UART2)
46 uart = (volatile u8 *)(OMAP_UART2_BASE);
47#else
48 uart = (volatile u8 *)(OMAP_UART1_BASE);
49#endif
50
51#ifdef CONFIG_ARCH_OMAP1
52 /* Determine which serial port to use */
53 do {
54 /* MMU is not on, so cpu_is_omapXXXX() won't work here */
55 unsigned int omap_id = omap_get_id();
56
57 if (omap_id == OMAP_ID_730 || omap_id == OMAP_ID_850)
58 shift = 0;
59
60 if (check_port(uart, shift))
61 break;
62 /* Silent boot if no serial ports are enabled. */
63 return;
64 } while (0);
65#endif /* CONFIG_ARCH_OMAP1 */
66#endif
67
68 /*
69 * Now, xmit each character
70 */
71 while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
72 barrier();
73 uart[UART_TX << shift] = c;
74}
75
76static inline void flush(void)
77{
78}
79
80/*
81 * nothing to do
82 */
83#define arch_decomp_setup()
84#define arch_decomp_wdog()
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