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authorPaul Walmsley <paul@pwsan.com>2010-01-26 22:13:02 -0500
committerPaul Walmsley <paul@pwsan.com>2010-01-26 22:13:02 -0500
commitf0271d65f9ac511d2e3e1fdbcd7418a5a7df0769 (patch)
tree11955198152ab0fcef09adc276dd98e3dc5c898c /arch/arm/plat-omap/include/plat/powerdomain.h
parent915aad89fcc57a03511c69915b3876f4e53074ee (diff)
OMAP clockdomain/powerdomain: improve documentation
This patch only affects documentation; no functional changes are included. Clean up comments in the current clockdomain, powerdomain code and header files. This mostly involves conversion to kerneldoc format, although some clarifications are also included. Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/plat-omap/include/plat/powerdomain.h')
-rw-r--r--arch/arm/plat-omap/include/plat/powerdomain.h40
1 files changed, 18 insertions, 22 deletions
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index 87e13f88994f..e15c7e9da975 100644
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -68,40 +68,36 @@
68struct clockdomain; 68struct clockdomain;
69struct powerdomain; 69struct powerdomain;
70 70
71/**
72 * struct powerdomain - OMAP powerdomain
73 * @name: Powerdomain name
74 * @omap_chip: represents the OMAP chip types containing this pwrdm
75 * @prcm_offs: the address offset from CM_BASE/PRM_BASE
76 * @pwrsts: Possible powerdomain power states
77 * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
78 * @flags: Powerdomain flags
79 * @banks: Number of software-controllable memory banks in this powerdomain
80 * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
81 * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
82 * @pwrdm_clkdms: Clockdomains in this powerdomain
83 * @node: list_head linking all powerdomains
84 * @state:
85 * @state_counter:
86 * @timer:
87 * @state_timer:
88 */
71struct powerdomain { 89struct powerdomain {
72
73 /* Powerdomain name */
74 const char *name; 90 const char *name;
75
76 /* Used to represent the OMAP chip types containing this pwrdm */
77 const struct omap_chip_id omap_chip; 91 const struct omap_chip_id omap_chip;
78
79 /* the address offset from CM_BASE/PRM_BASE */
80 const s16 prcm_offs; 92 const s16 prcm_offs;
81
82 /* Possible powerdomain power states */
83 const u8 pwrsts; 93 const u8 pwrsts;
84
85 /* Possible logic power states when pwrdm in RETENTION */
86 const u8 pwrsts_logic_ret; 94 const u8 pwrsts_logic_ret;
87
88 /* Powerdomain flags */
89 const u8 flags; 95 const u8 flags;
90
91 /* Number of software-controllable memory banks in this powerdomain */
92 const u8 banks; 96 const u8 banks;
93
94 /* Possible memory bank pwrstates when pwrdm in RETENTION */
95 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS]; 97 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
96
97 /* Possible memory bank pwrstates when pwrdm is ON */
98 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS]; 98 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
99
100 /* Clockdomains in this powerdomain */
101 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; 99 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
102
103 struct list_head node; 100 struct list_head node;
104
105 int state; 101 int state;
106 unsigned state_counter[PWRDM_MAX_PWRSTS]; 102 unsigned state_counter[PWRDM_MAX_PWRSTS];
107 103