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authorAfzal Mohammed <afzal@ti.com>2012-09-29 02:56:13 -0400
committerAfzal Mohammed <afzal@ti.com>2012-10-15 05:12:05 -0400
commitbc3668ea046be9e841eecfab04bddfa759e765d6 (patch)
tree48dd86e24b260351feed63499d277dc61e7f5a98 /arch/arm/plat-omap/include/plat/gpmc.h
parentb6ab13e7d6d2778702baea7433d0bd9f234d5083 (diff)
ARM: OMAP2+: nand: header cleanup
For common arm zImage existing nand header file in platform specific location was moved to generic platform data location, but it contained more than platform data, remove it. New local header has been created for exposing functions. Also move gpmc-nand platform data to platform header meant for nand from gpmc header file Signed-off-by: Afzal Mohammed <afzal@ti.com>
Diffstat (limited to 'arch/arm/plat-omap/include/plat/gpmc.h')
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc.h28
1 files changed, 2 insertions, 26 deletions
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index f7e0990eaf37..4b06bb4531a2 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -11,6 +11,8 @@
11#ifndef __OMAP2_GPMC_H 11#ifndef __OMAP2_GPMC_H
12#define __OMAP2_GPMC_H 12#define __OMAP2_GPMC_H
13 13
14#include <linux/platform_data/mtd-nand-omap2.h>
15
14/* Maximum Number of Chip Selects */ 16/* Maximum Number of Chip Selects */
15#define GPMC_CS_NUM 8 17#define GPMC_CS_NUM 8
16 18
@@ -86,16 +88,6 @@
86#define PREFETCH_FIFOTHRESHOLD_MAX 0x40 88#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
87#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) 89#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
88 90
89enum omap_ecc {
90 /* 1-bit ecc: stored at end of spare area */
91 OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
92 OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
93 /* 1-bit ecc: stored at beginning of spare area as romcode */
94 OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
95 OMAP_ECC_BCH4_CODE_HW, /* 4-bit BCH ecc code */
96 OMAP_ECC_BCH8_CODE_HW, /* 8-bit BCH ecc code */
97};
98
99/* 91/*
100 * Note that all values in this struct are in nanoseconds except sync_clk 92 * Note that all values in this struct are in nanoseconds except sync_clk
101 * (which is in picoseconds), while the register values are in gpmc_fck cycles. 93 * (which is in picoseconds), while the register values are in gpmc_fck cycles.
@@ -133,22 +125,6 @@ struct gpmc_timings {
133 u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */ 125 u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
134}; 126};
135 127
136struct gpmc_nand_regs {
137 void __iomem *gpmc_status;
138 void __iomem *gpmc_nand_command;
139 void __iomem *gpmc_nand_address;
140 void __iomem *gpmc_nand_data;
141 void __iomem *gpmc_prefetch_config1;
142 void __iomem *gpmc_prefetch_config2;
143 void __iomem *gpmc_prefetch_control;
144 void __iomem *gpmc_prefetch_status;
145 void __iomem *gpmc_ecc_config;
146 void __iomem *gpmc_ecc_control;
147 void __iomem *gpmc_ecc_size_config;
148 void __iomem *gpmc_ecc1_result;
149 void __iomem *gpmc_bch_result0;
150};
151
152extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs); 128extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
153extern int gpmc_get_client_irq(unsigned irq_config); 129extern int gpmc_get_client_irq(unsigned irq_config);
154 130