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authorSascha Hauer <s.hauer@pengutronix.de>2010-02-10 05:11:37 -0500
committerSascha Hauer <s.hauer@pengutronix.de>2010-02-10 05:11:37 -0500
commitfed9b63ca5aa999e618140cc1cc6bd73f212ec9b (patch)
tree1dc078e208d879a65f8cc2515e0817a109272d59 /arch/arm/plat-mxc
parentd2831d1f543489ef97a20e6e65f625e195b521bf (diff)
parent3d48e1d0e8701d004ce7e1dd66088f42e429d079 (diff)
Merge branch 'mx51-baseport-sascha' of git://kernel.ubuntu.com/amitk/mx51-upstream into mxc-master
Diffstat (limited to 'arch/arm/plat-mxc')
-rw-r--r--arch/arm/plat-mxc/Kconfig16
-rw-r--r--arch/arm/plat-mxc/Makefile3
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/debug-macro.S9
-rw-r--r--arch/arm/plat-mxc/include/mach/entry-macro.S34
-rw-r--r--arch/arm/plat-mxc/include/mach/hardware.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx51.h326
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v3.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/irqs.h9
-rw-r--r--arch/arm/plat-mxc/include/mach/memory.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/mx51.h454
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h13
-rw-r--r--arch/arm/plat-mxc/include/mach/timex.h2
-rw-r--r--arch/arm/plat-mxc/time.c41
-rw-r--r--arch/arm/plat-mxc/tzic.c172
15 files changed, 1079 insertions, 20 deletions
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 8b0a1ee039fa..cea51a0ae9f7 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -41,6 +41,13 @@ config ARCH_MXC91231
41 help 41 help
42 This enables support for systems based on the Freescale MXC91231 family 42 This enables support for systems based on the Freescale MXC91231 family
43 43
44config ARCH_MX5
45 bool "MX5-based"
46 select CPU_V7
47 select COMMON_CLKDEV
48 help
49 This enables support for systems based on the Freescale i.MX51 family
50
44endchoice 51endchoice
45 52
46source "arch/arm/mach-mx1/Kconfig" 53source "arch/arm/mach-mx1/Kconfig"
@@ -48,6 +55,7 @@ source "arch/arm/mach-mx2/Kconfig"
48source "arch/arm/mach-mx3/Kconfig" 55source "arch/arm/mach-mx3/Kconfig"
49source "arch/arm/mach-mx25/Kconfig" 56source "arch/arm/mach-mx25/Kconfig"
50source "arch/arm/mach-mxc91231/Kconfig" 57source "arch/arm/mach-mxc91231/Kconfig"
58source "arch/arm/mach-mx5/Kconfig"
51 59
52endmenu 60endmenu
53 61
@@ -62,6 +70,14 @@ config MXC_IRQ_PRIOR
62 requirements for timing. 70 requirements for timing.
63 Say N here, unless you have a specialized requirement. 71 Say N here, unless you have a specialized requirement.
64 72
73config MXC_TZIC
74 bool "Enable TrustZone Interrupt Controller"
75 depends on ARCH_MX51
76 help
77 This will be automatically selected for all processors
78 containing this interrupt controller.
79 Say N here only if you are really sure.
80
65config MXC_PWM 81config MXC_PWM
66 tristate "Enable PWM driver" 82 tristate "Enable PWM driver"
67 depends on ARCH_MXC 83 depends on ARCH_MXC
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 7322bca8f5fb..a4bc6cb26aa4 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -5,6 +5,9 @@
5# Common support 5# Common support
6obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o 6obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o
7 7
8# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o)
9obj-$(CONFIG_MXC_TZIC) += tzic.o
10
8obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o 11obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o
9obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o 12obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o
10CFLAGS_iomux-mx1-mx2.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS 13CFLAGS_iomux-mx1-mx2.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 4bf1068ffad9..2941472582d2 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -20,14 +20,17 @@ extern void mx25_map_io(void);
20extern void mx27_map_io(void); 20extern void mx27_map_io(void);
21extern void mx31_map_io(void); 21extern void mx31_map_io(void);
22extern void mx35_map_io(void); 22extern void mx35_map_io(void);
23extern void mx51_map_io(void);
23extern void mxc91231_map_io(void); 24extern void mxc91231_map_io(void);
24extern void mxc_init_irq(void __iomem *); 25extern void mxc_init_irq(void __iomem *);
26extern void tzic_init_irq(void __iomem *);
25extern void mx1_init_irq(void); 27extern void mx1_init_irq(void);
26extern void mx21_init_irq(void); 28extern void mx21_init_irq(void);
27extern void mx25_init_irq(void); 29extern void mx25_init_irq(void);
28extern void mx27_init_irq(void); 30extern void mx27_init_irq(void);
29extern void mx31_init_irq(void); 31extern void mx31_init_irq(void);
30extern void mx35_init_irq(void); 32extern void mx35_init_irq(void);
33extern void mx51_init_irq(void);
31extern void mxc91231_init_irq(void); 34extern void mxc91231_init_irq(void);
32extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); 35extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
33extern int mx1_clocks_init(unsigned long fref); 36extern int mx1_clocks_init(unsigned long fref);
@@ -36,6 +39,8 @@ extern int mx25_clocks_init(void);
36extern int mx27_clocks_init(unsigned long fref); 39extern int mx27_clocks_init(unsigned long fref);
37extern int mx31_clocks_init(unsigned long fref); 40extern int mx31_clocks_init(unsigned long fref);
38extern int mx35_clocks_init(void); 41extern int mx35_clocks_init(void);
42extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
43 unsigned long ckih1, unsigned long ckih2);
39extern int mxc91231_clocks_init(unsigned long fref); 44extern int mxc91231_clocks_init(unsigned long fref);
40extern int mxc_register_gpios(void); 45extern int mxc_register_gpios(void);
41extern int mxc_register_device(struct platform_device *pdev, void *data); 46extern int mxc_register_device(struct platform_device *pdev, void *data);
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 916d4fcb2ef2..133d66bfb533 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -45,6 +45,15 @@
45#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) 45#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
46#endif 46#endif
47 47
48#ifdef CONFIG_ARCH_MX5
49#ifdef UART_PADDR
50#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
51#endif
52#include <mach/mx51.h>
53#define UART_PADDR MX51_UART1_BASE_ADDR
54#define UART_VADDR MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR)
55#endif
56
48#ifdef CONFIG_ARCH_MXC91231 57#ifdef CONFIG_ARCH_MXC91231
49#ifdef UART_PADDR 58#ifdef UART_PADDR
50#error "CONFIG_DEBUG_LL is incompatible with multiple archs" 59#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index 7cf290efe768..aeb08697726b 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org> 2 * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
4 */ 4 */
5 5
6/* 6/*
@@ -18,11 +18,16 @@
18 .endm 18 .endm
19 19
20 .macro get_irqnr_preamble, base, tmp 20 .macro get_irqnr_preamble, base, tmp
21#ifndef CONFIG_MXC_TZIC
21 ldr \base, =avic_base 22 ldr \base, =avic_base
22 ldr \base, [\base] 23 ldr \base, [\base]
23#ifdef CONFIG_MXC_IRQ_PRIOR 24#ifdef CONFIG_MXC_IRQ_PRIOR
24 ldr r4, [\base, #AVIC_NIMASK] 25 ldr r4, [\base, #AVIC_NIMASK]
25#endif 26#endif
27#elif defined CONFIG_MXC_TZIC
28 ldr \base, =tzic_base
29 ldr \base, [\base]
30#endif /* CONFIG_MXC_TZIC */
26 .endm 31 .endm
27 32
28 .macro arch_ret_to_user, tmp1, tmp2 33 .macro arch_ret_to_user, tmp1, tmp2
@@ -32,6 +37,7 @@
32 @ and returns its number in irqnr 37 @ and returns its number in irqnr
33 @ and returns if an interrupt occured in irqstat 38 @ and returns if an interrupt occured in irqstat
34 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 39 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
40#ifndef CONFIG_MXC_TZIC
35 @ Load offset & priority of the highest priority 41 @ Load offset & priority of the highest priority
36 @ interrupt pending from AVIC_NIVECSR 42 @ interrupt pending from AVIC_NIVECSR
37 ldr \irqstat, [\base, #0x40] 43 ldr \irqstat, [\base, #0x40]
@@ -45,6 +51,32 @@
45 strne \tmp, [\base, #AVIC_NIMASK] 51 strne \tmp, [\base, #AVIC_NIMASK]
46 streq r4, [\base, #AVIC_NIMASK] 52 streq r4, [\base, #AVIC_NIMASK]
47#endif 53#endif
54#elif defined CONFIG_MXC_TZIC
55 @ Load offset & priority of the highest priority
56 @ interrupt pending.
57 @ 0xD80 is HIPND0 register
58 mov \irqnr, #0
59 mov \irqstat, #0x0D80
601000:
61 ldr \tmp, [\irqstat, \base]
62 cmp \tmp, #0
63 bne 1001f
64 addeq \irqnr, \irqnr, #32
65 addeq \irqstat, \irqstat, #4
66 cmp \irqnr, #128
67 blo 1000b
68 b 2001f
691001: mov \irqstat, #1
701002: tst \tmp, \irqstat
71 bne 2002f
72 movs \tmp, \tmp, lsr #1
73 addne \irqnr, \irqnr, #1
74 bne 1002b
752001:
76 mov \irqnr, #0
772002:
78 movs \irqnr, \irqnr
79#endif
48 .endm 80 .endm
49 81
50 @ irq priority table (not used) 82 @ irq priority table (not used)
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index db14c56930a3..ebadf4ac43fc 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -27,6 +27,10 @@
27 (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\ 27 (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\
28 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)) 28 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0))
29 29
30#ifdef CONFIG_ARCH_MX5
31#include <mach/mx51.h>
32#endif
33
30#ifdef CONFIG_ARCH_MX3 34#ifdef CONFIG_ARCH_MX3
31#include <mach/mx3x.h> 35#include <mach/mx3x.h>
32#include <mach/mx31.h> 36#include <mach/mx31.h>
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
new file mode 100644
index 000000000000..b4f975e6a665
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -0,0 +1,326 @@
1/*
2 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#ifndef __MACH_IOMUX_MX51_H__
13#define __MACH_IOMUX_MX51_H__
14
15#include <mach/iomux-v3.h>
16
17/*
18 * various IOMUX alternate output functions (1-7)
19 */
20typedef enum iomux_config {
21 IOMUX_CONFIG_ALT0,
22 IOMUX_CONFIG_ALT1,
23 IOMUX_CONFIG_ALT2,
24 IOMUX_CONFIG_ALT3,
25 IOMUX_CONFIG_ALT4,
26 IOMUX_CONFIG_ALT5,
27 IOMUX_CONFIG_ALT6,
28 IOMUX_CONFIG_ALT7,
29 IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
30 IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */
31} iomux_pin_cfg_t;
32
33/* Pad control groupings */
34#define MX51_UART1_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_DSE_HIGH)
36#define MX51_UART2_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
37 PAD_CTL_SRE_FAST)
38#define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
39 PAD_CTL_SRE_FAST)
40
41/*
42 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
43 * If <padname> or <padmode> refers to a GPIO, it is named
44 * GPIO_<unit>_<num> see also iomux-v3.h
45 */
46
47/*
48 * FIXME: This was converted using scripts from existing Freescale code to
49 * this form used upstream. Need to verify the name format.
50 */
51
52/* PAD MUX ALT INPSE PATH PADCTRL */
53
54#define MX51_PAD_GPIO_2_0__EIM_D16 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL)
55#define MX51_PAD_GPIO_2_1__EIM_D17 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, NO_PAD_CTRL)
56#define MX51_PAD_GPIO_2_2__EIM_D18 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, NO_PAD_CTRL)
57#define MX51_PAD_GPIO_2_3__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL)
58#define MX51_PAD_GPIO_2_4__EIM_D20 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL)
59#define MX51_PAD_GPIO_2_5__EIM_D21 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, NO_PAD_CTRL)
60#define MX51_PAD_GPIO_2_6__EIM_D22 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL)
61#define MX51_PAD_GPIO_2_7__EIM_D23 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL)
62
63/* Babbage UART3 */
64#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
65#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
66#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
67#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
68
69#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, 0x0, 0, NO_PAD_CTRL)
70#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, 0x0, 0, NO_PAD_CTRL)
71#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL)
72#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL)
73
74#define MX51_PAD_GPIO_2_10__EIM_A16 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL)
75#define MX51_PAD_GPIO_2_11__EIM_A17 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL)
76#define MX51_PAD_GPIO_2_12__EIM_A18 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL)
77#define MX51_PAD_GPIO_2_13__EIM_A19 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL)
78#define MX51_PAD_GPIO_2_14__EIM_A20 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, NO_PAD_CTRL)
79#define MX51_PAD_GPIO_2_15__EIM_A21 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL)
80#define MX51_PAD_GPIO_2_16__EIM_A22 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL)
81#define MX51_PAD_GPIO_2_17__EIM_A23 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL)
82
83#define MX51_PAD_GPIO_2_18__EIM_A24 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL)
84#define MX51_PAD_GPIO_2_19__EIM_A25 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL)
85#define MX51_PAD_GPIO_2_20__EIM_A26 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL)
86#define MX51_PAD_GPIO_2_21__EIM_A27 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, NO_PAD_CTRL)
87#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL)
88#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL)
89#define MX51_PAD_GPIO_2_22__EIM_EB2 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL)
90#define MX51_PAD_GPIO_2_23__EIM_EB3 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL)
91
92#define MX51_PAD_GPIO_2_24__EIM_OE IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL)
93#define MX51_PAD_GPIO_2_25__EIM_CS0 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL)
94#define MX51_PAD_GPIO_2_26__EIM_CS1 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL)
95#define MX51_PAD_GPIO_2_27__EIM_CS2 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL)
96#define MX51_PAD_GPIO_2_28__EIM_CS3 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL)
97#define MX51_PAD_GPIO_2_29__EIM_CS4 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL)
98#define MX51_PAD_GPIO_2_30__EIM_CS5 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL)
99#define MX51_PAD_GPIO_2_31__EIM_DTACK IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL)
100
101#define MX51_PAD_GPIO_3_1__EIM_LBA IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
102#define MX51_PAD_GPIO_3_2__EIM_CRE IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
103#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
104#define MX51_PAD_GPIO_3_3__NANDF_WE_B IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL)
105#define MX51_PAD_GPIO_3_4__NANDF_RE_B IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL)
106#define MX51_PAD_GPIO_3_5__NANDF_ALE IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL)
107#define MX51_PAD_GPIO_3_6__NANDF_CLE IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL)
108#define MX51_PAD_GPIO_3_7__NANDF_WP_B IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL)
109#define MX51_PAD_GPIO_3_8__NANDF_RB0 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL)
110#define MX51_PAD_GPIO_3_9__NANDF_RB1 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL)
111#define MX51_PAD_GPIO_3_10__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL)
112#define MX51_PAD_GPIO_3_11__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL)
113#define MX51_PAD_GPIO_3_12__GPIO_NAND IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
114/* REVISIT: Not sure of these values
115
116 #define MX51_PAD_GPIO_1___NANDF_RB4 IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL)
117 #define MX51_PAD_GPIO_3_13__NANDF_RB5 IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
118 #define MX51_PAD_GPIO_3_15__NANDF_RB7 IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
119*/
120#define MX51_PAD_GPIO_3_14__NANDF_RB6 IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
121#define MX51_PAD_GPIO_3_16__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
122#define MX51_PAD_GPIO_3_17__NANDF_CS1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
123#define MX51_PAD_GPIO_3_18__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
124#define MX51_PAD_GPIO_3_19__NANDF_CS3 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
125#define MX51_PAD_GPIO_3_20__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
126#define MX51_PAD_GPIO_3_21__NANDF_CS5 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
127#define MX51_PAD_GPIO_3_22__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
128#define MX51_PAD_GPIO_3_23__NANDF_CS7 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
129#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
130#define MX51_PAD_GPIO_3_25__NANDF_D15 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
131#define MX51_PAD_GPIO_3_26__NANDF_D14 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
132#define MX51_PAD_GPIO_3_27__NANDF_D13 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
133#define MX51_PAD_GPIO_3_28__NANDF_D12 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL)
134#define MX51_PAD_GPIO_3_29__NANDF_D11 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
135#define MX51_PAD_GPIO_3_30__NANDF_D10 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
136#define MX51_PAD_GPIO_3_31__NANDF_D9 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
137#define MX51_PAD_GPIO_4_0__NANDF_D8 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL)
138#define MX51_PAD_GPIO_4_1__NANDF_D7 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
139#define MX51_PAD_GPIO_4_2__NANDF_D6 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
140#define MX51_PAD_GPIO_4_3__NANDF_D5 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL)
141#define MX51_PAD_GPIO_4_4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
142#define MX51_PAD_GPIO_4_5__NANDF_D3 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
143#define MX51_PAD_GPIO_4_6__NANDF_D2 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
144#define MX51_PAD_GPIO_4_7__NANDF_D1 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
145#define MX51_PAD_GPIO_4_8__NANDF_D0 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL)
146#define MX51_PAD_GPIO_3_12__CSI1_D8 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL)
147#define MX51_PAD_GPIO_3_13__CSI1_D9 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL)
148#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL)
149#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL)
150#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL)
151#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL)
152#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL)
153#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
154#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
155#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
156#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
157#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
158#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
159#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
160#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
161#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
162#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
163#define MX51_PAD_GPIO_4_9__CSI2_D12 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL)
164#define MX51_PAD_GPIO_4_10__CSI2_D13 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL)
165#define MX51_PAD_GPIO_4_11__CSI2_D14 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL)
166#define MX51_PAD_GPIO_4_12__CSI2_D15 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
167#define MX51_PAD_GPIO_4_11__CSI2_D16 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL)
168#define MX51_PAD_GPIO_4_12__CSI2_D17 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL)
169#define MX51_PAD_GPIO_4_11__CSI2_D18 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL)
170#define MX51_PAD_GPIO_4_12__CSI2_D19 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL)
171#define MX51_PAD_GPIO_4_13__CSI2_VSYNC IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL)
172#define MX51_PAD_GPIO_4_14__CSI2_HSYNC IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL)
173#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL)
174#define MX51_PAD_CSI2_PKE0__CSI2_PKE0 IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
175#define MX51_PAD_GPIO_4_16__I2C1_CLK IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL)
176#define MX51_PAD_GPIO_4_17__I2C1_DAT IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL)
177#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL)
178#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL)
179#define MX51_PAD_GPIO_4_20__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL)
180#define MX51_PAD_GPIO_4_21__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL)
181#define MX51_PAD_GPIO_4_22__CSPI1_MOSI IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL)
182#define MX51_PAD_GPIO_4_23__CSPI1_MISO IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL)
183#define MX51_PAD_GPIO_4_24__CSPI1_SS0 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL)
184#define MX51_PAD_GPIO_4_25__CSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL)
185#define MX51_PAD_GPIO_4_26__CSPI1_RDY IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL)
186#define MX51_PAD_GPIO_4_27__CSPI1_SCLK IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
187
188/* Babbage UART1 */
189#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
190#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
191#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
192#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL)
193
194/* Babbage UART2 */
195#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
196#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL)
197
198#define MX51_PAD_GPIO_1_22__UART3_RXD IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
199#define MX51_PAD_GPIO_1_23__UART3_TXD IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
200#define MX51_PAD_GPIO_1_24__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL)
201#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
202#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
203#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
204#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
205#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
206#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
207#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
208#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
209#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
210#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
211#define MX51_PAD_GPIO_1_25__USBH1_CLK IOMUX_PAD(0x678, 0x278, 2, 0x0, 0, NO_PAD_CTRL)
212#define MX51_PAD_GPIO_1_26__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, 2, 0x0, 0, NO_PAD_CTRL)
213#define MX51_PAD_GPIO_1_27__USBH1_STP IOMUX_PAD(0x680, 0x280, 2, 0x0, 0, NO_PAD_CTRL)
214#define MX51_PAD_GPIO_1_28__USBH1_NXT IOMUX_PAD(0x684, 0x284, 2, 0x0, 0, NO_PAD_CTRL)
215#define MX51_PAD_GPIO_1_11__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 2, 0x0, 0, NO_PAD_CTRL)
216#define MX51_PAD_GPIO_1_12__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 2, 0x0, 0, NO_PAD_CTRL)
217#define MX51_PAD_GPIO_1_13__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 2, 0x0, 0, NO_PAD_CTRL)
218#define MX51_PAD_GPIO_1_14__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 2, 0x0, 0, NO_PAD_CTRL)
219#define MX51_PAD_GPIO_1_15__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 2, 0x0, 0, NO_PAD_CTRL)
220#define MX51_PAD_GPIO_1_16__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 2, 0x0, 0, NO_PAD_CTRL)
221#define MX51_PAD_GPIO_1_17__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 2, 0x0, 0, NO_PAD_CTRL)
222#define MX51_PAD_GPIO_1_18__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 2, 0x0, 0, NO_PAD_CTRL)
223#define MX51_PAD_GPIO_3_0__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
224#define MX51_PAD_GPIO_3_1__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL)
225#define MX51_PAD_GPIO_3_2__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL)
226#define MX51_PAD_GPIO_3_3__DI1_D0_CS IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL)
227#define MX51_PAD_GPIO_3_4__DI1_D1_CS IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL)
228#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL)
229#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL)
230#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL)
231#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL)
232#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
233#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
234#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
235#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL)
236#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL)
237#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL)
238#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL)
239#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL)
240#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL)
241#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL)
242#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL)
243#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL)
244#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL)
245#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL)
246#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL)
247#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL)
248#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL)
249#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL)
250#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL)
251#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL)
252#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL)
253#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL)
254#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL)
255#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL)
256#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL)
257#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL)
258#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL)
259#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL)
260#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL)
261#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL)
262#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL)
263#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL)
264#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL)
265#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL)
266#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL)
267#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL)
268#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL)
269#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL)
270#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL)
271#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL)
272#define MX51_PAD_GPIO_1_19__DISP2_DAT6 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL)
273#define MX51_PAD_GPIO_1_29__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL)
274#define MX51_PAD_GPIO_1_30__DISP2_DAT8 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL)
275#define MX51_PAD_GPIO_1_31__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL)
276#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL)
277#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL)
278#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL)
279#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
280#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
281#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
282#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL)
283#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL)
284#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL)
285#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL)
286#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL)
287#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL)
288#define MX51_PAD_GPIO_1_0__GPIO1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL)
289#define MX51_PAD_GPIO_1_1__GPIO1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL)
290#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL)
291#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL)
292#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL)
293#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL)
294#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL)
295#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL)
296#define MX51_PAD_GPIO_1_2__GPIO1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL)
297#define MX51_PAD_GPIO_1_3__GPIO1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL)
298#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
299#define MX51_PAD_GPIO_1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
300#define MX51_PAD_GPIO_1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
301#define MX51_PAD_GPIO_1_6__GPIO1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
302#define MX51_PAD_GPIO_1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, NO_PAD_CTRL)
303#define MX51_PAD_GPIO_1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \
304 (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS))
305#define MX51_PAD_GPIO_1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
306
307/* EIM */
308#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL)
309#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL)
310#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL)
311#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL)
312#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL)
313#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL)
314#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL)
315#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL)
316
317#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL)
318#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL)
319#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL)
320#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL)
321#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL)
322#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL)
323#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL)
324#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL)
325
326#endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index 1deda0184892..f2f73d31d5ba 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -81,11 +81,13 @@ struct pad_desc {
81 81
82#define PAD_CTL_ODE (1 << 3) 82#define PAD_CTL_ODE (1 << 3)
83 83
84#define PAD_CTL_DSE_STANDARD (0 << 1) 84#define PAD_CTL_DSE_LOW (0 << 1)
85#define PAD_CTL_DSE_HIGH (1 << 1) 85#define PAD_CTL_DSE_MED (1 << 1)
86#define PAD_CTL_DSE_MAX (2 << 1) 86#define PAD_CTL_DSE_HIGH (2 << 1)
87#define PAD_CTL_DSE_MAX (3 << 1)
87 88
88#define PAD_CTL_SRE_FAST (1 << 0) 89#define PAD_CTL_SRE_FAST (1 << 0)
90#define PAD_CTL_SRE_SLOW (0 << 0)
89 91
90/* 92/*
91 * setups a single pad in the iomuxer 93 * setups a single pad in the iomuxer
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index 0cb347645db4..a3ad643de5a1 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -12,9 +12,13 @@
12#define __ASM_ARCH_MXC_IRQS_H__ 12#define __ASM_ARCH_MXC_IRQS_H__
13 13
14/* 14/*
15 * So far all i.MX SoCs have 64 internal interrupts 15 * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64
16 */ 16 */
17#ifdef CONFIG_MXC_TZIC
18#define MXC_INTERNAL_IRQS 128
19#else
17#define MXC_INTERNAL_IRQS 64 20#define MXC_INTERNAL_IRQS 64
21#endif
18 22
19#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS 23#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
20 24
@@ -26,6 +30,8 @@
26#define MXC_GPIO_IRQS (32 * 3) 30#define MXC_GPIO_IRQS (32 * 3)
27#elif defined CONFIG_ARCH_MX25 31#elif defined CONFIG_ARCH_MX25
28#define MXC_GPIO_IRQS (32 * 4) 32#define MXC_GPIO_IRQS (32 * 4)
33#elif defined CONFIG_ARCH_MX5
34#define MXC_GPIO_IRQS (32 * 4)
29#elif defined CONFIG_ARCH_MXC91231 35#elif defined CONFIG_ARCH_MXC91231
30#define MXC_GPIO_IRQS (32 * 4) 36#define MXC_GPIO_IRQS (32 * 4)
31#endif 37#endif
@@ -51,6 +57,7 @@
51#else 57#else
52#define MX3_IPU_IRQS 0 58#define MX3_IPU_IRQS 0
53#endif 59#endif
60/* REVISIT: Add IPU irqs on IMX51 */
54 61
55#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS) 62#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
56 63
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 002eb91ab235..7cae9cb6208d 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -16,6 +16,7 @@
16#define MX25_PHYS_OFFSET UL(0x80000000) 16#define MX25_PHYS_OFFSET UL(0x80000000)
17#define MX27_PHYS_OFFSET UL(0xa0000000) 17#define MX27_PHYS_OFFSET UL(0xa0000000)
18#define MX3x_PHYS_OFFSET UL(0x80000000) 18#define MX3x_PHYS_OFFSET UL(0x80000000)
19#define MX51_PHYS_OFFSET UL(0x90000000)
19#define MXC91231_PHYS_OFFSET UL(0x90000000) 20#define MXC91231_PHYS_OFFSET UL(0x90000000)
20 21
21#if !defined(CONFIG_RUNTIME_PHYS_OFFSET) 22#if !defined(CONFIG_RUNTIME_PHYS_OFFSET)
@@ -31,6 +32,8 @@
31# define PHYS_OFFSET MX3x_PHYS_OFFSET 32# define PHYS_OFFSET MX3x_PHYS_OFFSET
32# elif defined CONFIG_ARCH_MXC91231 33# elif defined CONFIG_ARCH_MXC91231
33# define PHYS_OFFSET MXC91231_PHYS_OFFSET 34# define PHYS_OFFSET MXC91231_PHYS_OFFSET
35# elif defined CONFIG_ARCH_MX5
36# define PHYS_OFFSET MX51_PHYS_OFFSET
34# endif 37# endif
35#endif 38#endif
36 39
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
new file mode 100644
index 000000000000..771532b6b4a6
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -0,0 +1,454 @@
1#ifndef __ASM_ARCH_MXC_MX51_H__
2#define __ASM_ARCH_MXC_MX51_H__
3
4/*
5 * MX51 memory map:
6 *
7 *
8 * Virt Phys Size What
9 * ---------------------------------------------------------------------------
10 * FA3E0000 1FFE0000 128K IRAM (SCCv2 RAM)
11 * 30000000 256M GPU
12 * 40000000 512M IPU
13 * FA200000 60000000 1M DEBUG
14 * FB100000 70000000 1M SPBA 0
15 * FB000000 73F00000 1M AIPS 1
16 * FB200000 83F00000 1M AIPS 2
17 * FA100000 8FFFC000 16K TZIC (interrupt controller)
18 * 90000000 256M CSD0 SDRAM/DDR
19 * A0000000 256M CSD1 SDRAM/DDR
20 * B0000000 128M CS0 Flash
21 * B8000000 128M CS1 Flash
22 * C0000000 128M CS2 Flash
23 * C8000000 64M CS3 Flash
24 * CC000000 32M CS4 SRAM
25 * CE000000 32M CS5 SRAM
26 * F9000000 CFFF0000 64K NFC (NAND Flash AXI)
27 *
28 */
29
30/*
31 * IRAM
32 */
33#define MX51_IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
34#define MX51_IRAM_BASE_ADDR_VIRT 0xFA3E0000
35#define MX51_IRAM_PARTITIONS 16
36#define MX51_IRAM_PARTITIONS_TO1 12
37#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */
38
39/*
40 * NFC
41 */
42#define MX51_NFC_AXI_BASE_ADDR 0xCFFF0000 /* NAND flash AXI */
43#define MX51_NFC_AXI_BASE_ADDR_VIRT 0xF9000000
44#define MX51_NFC_AXI_SIZE SZ_64K
45
46/*
47 * Graphics Memory of GPU
48 */
49#define MX51_GPU_BASE_ADDR 0x20000000
50#define MX51_GPU2D_BASE_ADDR 0xD0000000
51
52#define MX51_TZIC_BASE_ADDR 0x8FFFC000
53#define MX51_TZIC_BASE_ADDR_VIRT 0xFA100000
54#define MX51_TZIC_SIZE SZ_16K
55
56#define MX51_DEBUG_BASE_ADDR 0x60000000
57#define MX51_DEBUG_BASE_ADDR_VIRT 0xFA200000
58#define MX51_DEBUG_SIZE SZ_1M
59#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00001000)
60#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00002000)
61#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00003000)
62#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00004000)
63#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00005000)
64#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00006000)
65#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00007000)
66#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00008000)
67
68/*
69 * SPBA global module enabled #0
70 */
71#define MX51_SPBA0_BASE_ADDR 0x70000000
72#define MX51_SPBA0_BASE_ADDR_VIRT 0xFB100000
73#define MX51_SPBA0_SIZE SZ_1M
74
75#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00004000)
76#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00008000)
77#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0000C000)
78#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000)
79#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00014000)
80#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00020000)
81#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00024000)
82#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00028000)
83#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00030000)
84#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00034000)
85#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00038000)
86#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0003C000)
87
88/*
89 * defines for SPBA modules
90 */
91#define MX51_SPBA_SDHC1 0x04
92#define MX51_SPBA_SDHC2 0x08
93#define MX51_SPBA_UART3 0x0C
94#define MX51_SPBA_CSPI1 0x10
95#define MX51_SPBA_SSI2 0x14
96#define MX51_SPBA_SDHC3 0x20
97#define MX51_SPBA_SDHC4 0x24
98#define MX51_SPBA_SPDIF 0x28
99#define MX51_SPBA_ATA 0x30
100#define MX51_SPBA_SLIM 0x34
101#define MX51_SPBA_HSI2C 0x38
102#define MX51_SPBA_CTRL 0x3C
103
104/*
105 * AIPS 1
106 */
107#define MX51_AIPS1_BASE_ADDR 0x73F00000
108#define MX51_AIPS1_BASE_ADDR_VIRT 0xFB000000
109#define MX51_AIPS1_SIZE SZ_1M
110
111#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00080000)
112#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00084000)
113#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00088000)
114#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0008C000)
115#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00090000)
116#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00094000)
117#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00098000)
118#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0009C000)
119#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A0000)
120#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A4000)
121#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A8000)
122#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000AC000)
123#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B0000)
124#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B4000)
125#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B8000)
126#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000BC000)
127#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000C0000)
128#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D0000)
129#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D4000)
130#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D8000)
131
132/*
133 * Defines for modules using static and dynamic DMA channels
134 */
135#define MX51_MXC_DMA_CHANNEL_IRAM 30
136#define MX51_MXC_DMA_CHANNEL_SPDIF_TX MXC_DMA_DYNAMIC_CHANNEL
137#define MX51_MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL
138#define MX51_MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL
139#define MX51_MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL
140#define MX51_MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL
141#define MX51_MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL
142#define MX51_MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL
143#define MX51_MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL
144#define MX51_MXC_DMA_CHANNEL_MMC2 MXC_DMA_DYNAMIC_CHANNEL
145#define MX51_MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL
146#define MX51_MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL
147#define MX51_MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL
148#ifdef CONFIG_SDMA_IRAM
149#define MX51_MXC_DMA_CHANNEL_SSI2_TX (MX51_MXC_DMA_CHANNEL_IRAM + 1)
150#else /*CONFIG_SDMA_IRAM */
151#define MX51_MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL
152#endif /*CONFIG_SDMA_IRAM */
153#define MX51_MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL
154#define MX51_MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL
155#define MX51_MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL
156#define MX51_MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL
157#define MX51_MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL
158#define MX51_MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL
159#define MX51_MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL
160#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL
161#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL
162
163/*
164 * AIPS 2
165 */
166#define MX51_AIPS2_BASE_ADDR 0x83F00000
167#define MX51_AIPS2_BASE_ADDR_VIRT 0xFB200000
168#define MX51_AIPS2_SIZE SZ_1M
169
170#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00080000)
171#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00084000)
172#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00088000)
173#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00094000)
174#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00098000)
175#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x0009C000)
176#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A0000)
177#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A4000)
178#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A8000)
179#define MX51_CSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000AC000)
180#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B0000)
181#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B4000)
182#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B8000)
183#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000BC000)
184#define MX51_CSPI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C0000)
185#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C4000)
186#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C8000)
187#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000CC000)
188#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D0000)
189#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D8000)
190#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D9000)
191#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DA000)
192#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DB000)
193#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DBF00)
194#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DC000)
195#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E0000)
196#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E4000)
197#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E8000)
198#define MX51_MXC_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000EC000)
199#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F0000)
200#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F4000)
201#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F8000)
202
203/*
204 * Memory regions and CS
205 */
206#define MX51_GPU_CTRL_BASE_ADDR 0x30000000
207#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
208#define MX51_CSD0_BASE_ADDR 0x90000000
209#define MX51_CSD1_BASE_ADDR 0xA0000000
210#define MX51_CS0_BASE_ADDR 0xB0000000
211#define MX51_CS1_BASE_ADDR 0xB8000000
212#define MX51_CS2_BASE_ADDR 0xC0000000
213#define MX51_CS3_BASE_ADDR 0xC8000000
214#define MX51_CS4_BASE_ADDR 0xCC000000
215#define MX51_CS5_BASE_ADDR 0xCE000000
216
217/* Does given address belongs to the specified memory region? */
218#define ADDRESS_IN_REGION(addr, start, size) \
219 (((addr) >= (start)) && ((addr) < (start)+(size)))
220
221/* Does given address belongs to the specified named `module'? */
222#define MX51_IS_MODULE(addr, module) \
223 ADDRESS_IN_REGION(addr, MX51_ ## module ## _BASE_ADDR, \
224 MX51_ ## module ## _SIZE)
225/*
226 * This macro defines the physical to virtual address mapping for all the
227 * peripheral modules. It is used by passing in the physical address as x
228 * and returning the virtual address. If the physical address is not mapped,
229 * it returns 0xDEADBEEF
230 */
231
232#define MX51_IO_ADDRESS(x) \
233 (void __iomem *) \
234 (MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) : \
235 MX51_IS_MODULE(x, TZIC) ? MX51_TZIC_IO_ADDRESS(x) : \
236 MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \
237 MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \
238 MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \
239 MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \
240 MX51_IS_MODULE(x, NFC_AXI) ? MX51_NFC_AXI_IO_ADDRESS(x) : \
241 0xDEADBEEF)
242
243/*
244 * define the address mapping macros: in physical address order
245 */
246#define MX51_IRAM_IO_ADDRESS(x) \
247 (((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT)
248
249#define MX51_TZIC_IO_ADDRESS(x) \
250 (((x) - MX51_TZIC_BASE_ADDR) + MX51_TZIC_BASE_ADDR_VIRT)
251
252#define MX51_DEBUG_IO_ADDRESS(x) \
253 (((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT)
254
255#define MX51_SPBA0_IO_ADDRESS(x) \
256 (((x) - MX51_SPBA0_BASE_ADDR) + MX51_SPBA0_BASE_ADDR_VIRT)
257
258#define MX51_AIPS1_IO_ADDRESS(x) \
259 (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)
260
261#define MX51_AIPS2_IO_ADDRESS(x) \
262 (((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT)
263
264#define MX51_NFC_AXI_IO_ADDRESS(x) \
265 (((x) - MX51_NFC_AXI_BASE_ADDR) + MX51_NFC_AXI_BASE_ADDR_VIRT)
266
267#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0
268
269/*
270 * DMA request assignments
271 */
272#define MX51_DMA_REQ_SSI3_TX1 47
273#define MX51_DMA_REQ_SSI3_RX1 46
274#define MX51_DMA_REQ_SPDIF 45
275#define MX51_DMA_REQ_UART3_TX 44
276#define MX51_DMA_REQ_UART3_RX 43
277#define MX51_DMA_REQ_SLIM_B_TX 42
278#define MX51_DMA_REQ_SDHC4 41
279#define MX51_DMA_REQ_SDHC3 40
280#define MX51_DMA_REQ_CSPI_TX 39
281#define MX51_DMA_REQ_CSPI_RX 38
282#define MX51_DMA_REQ_SSI3_TX2 37
283#define MX51_DMA_REQ_IPU 36
284#define MX51_DMA_REQ_SSI3_RX2 35
285#define MX51_DMA_REQ_EPIT2 34
286#define MX51_DMA_REQ_CTI2_1 33
287#define MX51_DMA_REQ_EMI_WR 32
288#define MX51_DMA_REQ_CTI2_0 31
289#define MX51_DMA_REQ_EMI_RD 30
290#define MX51_DMA_REQ_SSI1_TX1 29
291#define MX51_DMA_REQ_SSI1_RX1 28
292#define MX51_DMA_REQ_SSI1_TX2 27
293#define MX51_DMA_REQ_SSI1_RX2 26
294#define MX51_DMA_REQ_SSI2_TX1 25
295#define MX51_DMA_REQ_SSI2_RX1 24
296#define MX51_DMA_REQ_SSI2_TX2 23
297#define MX51_DMA_REQ_SSI2_RX2 22
298#define MX51_DMA_REQ_SDHC2 21
299#define MX51_DMA_REQ_SDHC1 20
300#define MX51_DMA_REQ_UART1_TX 19
301#define MX51_DMA_REQ_UART1_RX 18
302#define MX51_DMA_REQ_UART2_TX 17
303#define MX51_DMA_REQ_UART2_RX 16
304#define MX51_DMA_REQ_GPU 15
305#define MX51_DMA_REQ_EXTREQ1 14
306#define MX51_DMA_REQ_FIRI_TX 13
307#define MX51_DMA_REQ_FIRI_RX 12
308#define MX51_DMA_REQ_HS_I2C_RX 11
309#define MX51_DMA_REQ_HS_I2C_TX 10
310#define MX51_DMA_REQ_CSPI2_TX 9
311#define MX51_DMA_REQ_CSPI2_RX 8
312#define MX51_DMA_REQ_CSPI1_TX 7
313#define MX51_DMA_REQ_CSPI1_RX 6
314#define MX51_DMA_REQ_SLIM_B 5
315#define MX51_DMA_REQ_ATA_TX_END 4
316#define MX51_DMA_REQ_ATA_TX 3
317#define MX51_DMA_REQ_ATA_RX 2
318#define MX51_DMA_REQ_GPC 1
319#define MX51_DMA_REQ_VPU 0
320
321/*
322 * Interrupt numbers
323 */
324#define MX51_MXC_INT_BASE 0
325#define MX51_MXC_INT_RESV0 0
326#define MX51_MXC_INT_MMC_SDHC1 1
327#define MX51_MXC_INT_MMC_SDHC2 2
328#define MX51_MXC_INT_MMC_SDHC3 3
329#define MX51_MXC_INT_MMC_SDHC4 4
330#define MX51_MXC_INT_RESV5 5
331#define MX51_MXC_INT_SDMA 6
332#define MX51_MXC_INT_IOMUX 7
333#define MX51_MXC_INT_NFC 8
334#define MX51_MXC_INT_VPU 9
335#define MX51_MXC_INT_IPU_ERR 10
336#define MX51_MXC_INT_IPU_SYN 11
337#define MX51_MXC_INT_GPU 12
338#define MX51_MXC_INT_RESV13 13
339#define MX51_MXC_INT_USB_H1 14
340#define MX51_MXC_INT_EMI 15
341#define MX51_MXC_INT_USB_H2 16
342#define MX51_MXC_INT_USB_H3 17
343#define MX51_MXC_INT_USB_OTG 18
344#define MX51_MXC_INT_SAHARA_H0 19
345#define MX51_MXC_INT_SAHARA_H1 20
346#define MX51_MXC_INT_SCC_SMN 21
347#define MX51_MXC_INT_SCC_STZ 22
348#define MX51_MXC_INT_SCC_SCM 23
349#define MX51_MXC_INT_SRTC_NTZ 24
350#define MX51_MXC_INT_SRTC_TZ 25
351#define MX51_MXC_INT_RTIC 26
352#define MX51_MXC_INT_CSU 27
353#define MX51_MXC_INT_SLIM_B 28
354#define MX51_MXC_INT_SSI1 29
355#define MX51_MXC_INT_SSI2 30
356#define MX51_MXC_INT_UART1 31
357#define MX51_MXC_INT_UART2 32
358#define MX51_MXC_INT_UART3 33
359#define MX51_MXC_INT_RESV34 34
360#define MX51_MXC_INT_RESV35 35
361#define MX51_MXC_INT_CSPI1 36
362#define MX51_MXC_INT_CSPI2 37
363#define MX51_MXC_INT_CSPI 38
364#define MX51_MXC_INT_GPT 39
365#define MX51_MXC_INT_EPIT1 40
366#define MX51_MXC_INT_EPIT2 41
367#define MX51_MXC_INT_GPIO1_INT7 42
368#define MX51_MXC_INT_GPIO1_INT6 43
369#define MX51_MXC_INT_GPIO1_INT5 44
370#define MX51_MXC_INT_GPIO1_INT4 45
371#define MX51_MXC_INT_GPIO1_INT3 46
372#define MX51_MXC_INT_GPIO1_INT2 47
373#define MX51_MXC_INT_GPIO1_INT1 48
374#define MX51_MXC_INT_GPIO1_INT0 49
375#define MX51_MXC_INT_GPIO1_LOW 50
376#define MX51_MXC_INT_GPIO1_HIGH 51
377#define MX51_MXC_INT_GPIO2_LOW 52
378#define MX51_MXC_INT_GPIO2_HIGH 53
379#define MX51_MXC_INT_GPIO3_LOW 54
380#define MX51_MXC_INT_GPIO3_HIGH 55
381#define MX51_MXC_INT_GPIO4_LOW 56
382#define MX51_MXC_INT_GPIO4_HIGH 57
383#define MX51_MXC_INT_WDOG1 58
384#define MX51_MXC_INT_WDOG2 59
385#define MX51_MXC_INT_KPP 60
386#define MX51_MXC_INT_PWM1 61
387#define MX51_MXC_INT_I2C1 62
388#define MX51_MXC_INT_I2C2 63
389#define MX51_MXC_INT_HS_I2C 64
390#define MX51_MXC_INT_RESV65 65
391#define MX51_MXC_INT_RESV66 66
392#define MX51_MXC_INT_SIM_IPB 67
393#define MX51_MXC_INT_SIM_DAT 68
394#define MX51_MXC_INT_IIM 69
395#define MX51_MXC_INT_ATA 70
396#define MX51_MXC_INT_CCM1 71
397#define MX51_MXC_INT_CCM2 72
398#define MX51_MXC_INT_GPC1 73
399#define MX51_MXC_INT_GPC2 74
400#define MX51_MXC_INT_SRC 75
401#define MX51_MXC_INT_NM 76
402#define MX51_MXC_INT_PMU 77
403#define MX51_MXC_INT_CTI_IRQ 78
404#define MX51_MXC_INT_CTI1_TG0 79
405#define MX51_MXC_INT_CTI1_TG1 80
406#define MX51_MXC_INT_MCG_ERR 81
407#define MX51_MXC_INT_MCG_TMR 82
408#define MX51_MXC_INT_MCG_FUNC 83
409#define MX51_MXC_INT_GPU2_IRQ 84
410#define MX51_MXC_INT_GPU2_BUSY 85
411#define MX51_MXC_INT_RESV86 86
412#define MX51_MXC_INT_FEC 87
413#define MX51_MXC_INT_OWIRE 88
414#define MX51_MXC_INT_CTI1_TG2 89
415#define MX51_MXC_INT_SJC 90
416#define MX51_MXC_INT_SPDIF 91
417#define MX51_MXC_INT_TVE 92
418#define MX51_MXC_INT_FIRI 93
419#define MX51_MXC_INT_PWM2 94
420#define MX51_MXC_INT_SLIM_EXP 95
421#define MX51_MXC_INT_SSI3 96
422#define MX51_MXC_INT_EMI_BOOT 97
423#define MX51_MXC_INT_CTI1_TG3 98
424#define MX51_MXC_INT_SMC_RX 99
425#define MX51_MXC_INT_VPU_IDLE 100
426#define MX51_MXC_INT_EMI_NFC 101
427#define MX51_MXC_INT_GPU_IDLE 102
428
429/* silicon revisions specific to i.MX51 */
430#define MX51_CHIP_REV_1_0 0x10
431#define MX51_CHIP_REV_1_1 0x11
432#define MX51_CHIP_REV_1_2 0x12
433#define MX51_CHIP_REV_1_3 0x13
434#define MX51_CHIP_REV_2_0 0x20
435#define MX51_CHIP_REV_2_1 0x21
436#define MX51_CHIP_REV_2_2 0x22
437#define MX51_CHIP_REV_2_3 0x23
438#define MX51_CHIP_REV_3_0 0x30
439#define MX51_CHIP_REV_3_1 0x31
440#define MX51_CHIP_REV_3_2 0x32
441
442/* Mandatory defines used globally */
443
444#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
445
446extern unsigned int system_rev;
447
448static inline unsigned int mx51_revision(void)
449{
450 return system_rev;
451}
452#endif
453
454#endif /* __ASM_ARCH_MXC_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 800ae2a33b15..a790bf212972 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -30,6 +30,7 @@
30#define MXC_CPU_MX27 27 30#define MXC_CPU_MX27 27
31#define MXC_CPU_MX31 31 31#define MXC_CPU_MX31 31
32#define MXC_CPU_MX35 35 32#define MXC_CPU_MX35 35
33#define MXC_CPU_MX51 51
33#define MXC_CPU_MXC91231 91231 34#define MXC_CPU_MXC91231 91231
34 35
35#ifndef __ASSEMBLY__ 36#ifndef __ASSEMBLY__
@@ -108,6 +109,18 @@ extern unsigned int __mxc_cpu_type;
108# define cpu_is_mx35() (0) 109# define cpu_is_mx35() (0)
109#endif 110#endif
110 111
112#ifdef CONFIG_ARCH_MX5
113# ifdef mxc_cpu_type
114# undef mxc_cpu_type
115# define mxc_cpu_type __mxc_cpu_type
116# else
117# define mxc_cpu_type MXC_CPU_MX51
118# endif
119# define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51)
120#else
121# define cpu_is_mx51() (0)
122#endif
123
111#ifdef CONFIG_ARCH_MXC91231 124#ifdef CONFIG_ARCH_MXC91231
112# ifdef mxc_cpu_type 125# ifdef mxc_cpu_type
113# undef mxc_cpu_type 126# undef mxc_cpu_type
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index 527a6c24788e..024416ed11cd 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -28,6 +28,8 @@
28#define CLOCK_TICK_RATE 16625000 28#define CLOCK_TICK_RATE 16625000
29#elif defined CONFIG_ARCH_MX25 29#elif defined CONFIG_ARCH_MX25
30#define CLOCK_TICK_RATE 16000000 30#define CLOCK_TICK_RATE 16000000
31#elif defined CONFIG_ARCH_MX5
32#define CLOCK_TICK_RATE 8000000
31#elif defined CONFIG_ARCH_MXC91231 33#elif defined CONFIG_ARCH_MXC91231
32#define CLOCK_TICK_RATE 13000000 34#define CLOCK_TICK_RATE 13000000
33#endif 35#endif
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 844567ee35fe..c1ce51abdba6 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -30,9 +30,15 @@
30#include <asm/mach/time.h> 30#include <asm/mach/time.h>
31#include <mach/common.h> 31#include <mach/common.h>
32 32
33/*
34 * There are 2 versions of the timer hardware on Freescale MXC hardware.
35 * Version 1: MX1/MXL, MX21, MX27.
36 * Version 2: MX25, MX31, MX35, MX37, MX51
37 */
38
33/* defines common for all i.MX */ 39/* defines common for all i.MX */
34#define MXC_TCTL 0x00 40#define MXC_TCTL 0x00
35#define MXC_TCTL_TEN (1 << 0) 41#define MXC_TCTL_TEN (1 << 0) /* Enable module */
36#define MXC_TPRER 0x04 42#define MXC_TPRER 0x04
37 43
38/* MX1, MX21, MX27 */ 44/* MX1, MX21, MX27 */
@@ -47,8 +53,8 @@
47#define MX2_TSTAT_CAPT (1 << 1) 53#define MX2_TSTAT_CAPT (1 << 1)
48#define MX2_TSTAT_COMP (1 << 0) 54#define MX2_TSTAT_COMP (1 << 0)
49 55
50/* MX31, MX35, MX25, MXC91231 */ 56/* MX31, MX35, MX25, MXC91231, MX5 */
51#define MX3_TCTL_WAITEN (1 << 3) 57#define MX3_TCTL_WAITEN (1 << 3) /* Wait enable mode */
52#define MX3_TCTL_CLK_IPG (1 << 6) 58#define MX3_TCTL_CLK_IPG (1 << 6)
53#define MX3_TCTL_FRR (1 << 9) 59#define MX3_TCTL_FRR (1 << 9)
54#define MX3_IR 0x0c 60#define MX3_IR 0x0c
@@ -57,6 +63,9 @@
57#define MX3_TCN 0x24 63#define MX3_TCN 0x24
58#define MX3_TCMP 0x10 64#define MX3_TCMP 0x10
59 65
66#define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
67#define timer_is_v2() (!timer_is_v1())
68
60static struct clock_event_device clockevent_mxc; 69static struct clock_event_device clockevent_mxc;
61static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; 70static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
62 71
@@ -66,7 +75,7 @@ static inline void gpt_irq_disable(void)
66{ 75{
67 unsigned int tmp; 76 unsigned int tmp;
68 77
69 if (cpu_is_mx3() || cpu_is_mx25()) 78 if (timer_is_v2())
70 __raw_writel(0, timer_base + MX3_IR); 79 __raw_writel(0, timer_base + MX3_IR);
71 else { 80 else {
72 tmp = __raw_readl(timer_base + MXC_TCTL); 81 tmp = __raw_readl(timer_base + MXC_TCTL);
@@ -76,7 +85,7 @@ static inline void gpt_irq_disable(void)
76 85
77static inline void gpt_irq_enable(void) 86static inline void gpt_irq_enable(void)
78{ 87{
79 if (cpu_is_mx3() || cpu_is_mx25()) 88 if (timer_is_v2())
80 __raw_writel(1<<0, timer_base + MX3_IR); 89 __raw_writel(1<<0, timer_base + MX3_IR);
81 else { 90 else {
82 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, 91 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
@@ -86,11 +95,13 @@ static inline void gpt_irq_enable(void)
86 95
87static void gpt_irq_acknowledge(void) 96static void gpt_irq_acknowledge(void)
88{ 97{
89 if (cpu_is_mx1()) 98 if (timer_is_v1()) {
90 __raw_writel(0, timer_base + MX1_2_TSTAT); 99 if (cpu_is_mx1())
91 if (cpu_is_mx2()) 100 __raw_writel(0, timer_base + MX1_2_TSTAT);
92 __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT); 101 else
93 if (cpu_is_mx3() || cpu_is_mx25()) 102 __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
103 timer_base + MX1_2_TSTAT);
104 } else if (timer_is_v2())
94 __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT); 105 __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT);
95} 106}
96 107
@@ -117,7 +128,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk)
117{ 128{
118 unsigned int c = clk_get_rate(timer_clk); 129 unsigned int c = clk_get_rate(timer_clk);
119 130
120 if (cpu_is_mx3() || cpu_is_mx25()) 131 if (timer_is_v2())
121 clocksource_mxc.read = mx3_get_cycles; 132 clocksource_mxc.read = mx3_get_cycles;
122 133
123 clocksource_mxc.mult = clocksource_hz2mult(c, 134 clocksource_mxc.mult = clocksource_hz2mult(c,
@@ -180,7 +191,7 @@ static void mxc_set_mode(enum clock_event_mode mode,
180 191
181 if (mode != clockevent_mode) { 192 if (mode != clockevent_mode) {
182 /* Set event time into far-far future */ 193 /* Set event time into far-far future */
183 if (cpu_is_mx3() || cpu_is_mx25()) 194 if (timer_is_v2())
184 __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3, 195 __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3,
185 timer_base + MX3_TCMP); 196 timer_base + MX3_TCMP);
186 else 197 else
@@ -233,7 +244,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
233 struct clock_event_device *evt = &clockevent_mxc; 244 struct clock_event_device *evt = &clockevent_mxc;
234 uint32_t tstat; 245 uint32_t tstat;
235 246
236 if (cpu_is_mx3() || cpu_is_mx25()) 247 if (timer_is_v2())
237 tstat = __raw_readl(timer_base + MX3_TSTAT); 248 tstat = __raw_readl(timer_base + MX3_TSTAT);
238 else 249 else
239 tstat = __raw_readl(timer_base + MX1_2_TSTAT); 250 tstat = __raw_readl(timer_base + MX1_2_TSTAT);
@@ -264,7 +275,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
264{ 275{
265 unsigned int c = clk_get_rate(timer_clk); 276 unsigned int c = clk_get_rate(timer_clk);
266 277
267 if (cpu_is_mx3() || cpu_is_mx25()) 278 if (timer_is_v2())
268 clockevent_mxc.set_next_event = mx3_set_next_event; 279 clockevent_mxc.set_next_event = mx3_set_next_event;
269 280
270 clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, 281 clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
@@ -296,7 +307,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
296 __raw_writel(0, timer_base + MXC_TCTL); 307 __raw_writel(0, timer_base + MXC_TCTL);
297 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ 308 __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
298 309
299 if (cpu_is_mx3() || cpu_is_mx25()) 310 if (timer_is_v2())
300 tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN; 311 tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN;
301 else 312 else
302 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; 313 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
new file mode 100644
index 000000000000..afa6709db0b3
--- /dev/null
+++ b/arch/arm/plat-mxc/tzic.c
@@ -0,0 +1,172 @@
1/*
2 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/device.h>
16#include <linux/errno.h>
17#include <linux/io.h>
18
19#include <asm/mach/irq.h>
20
21#include <mach/hardware.h>
22
23/*
24 *****************************************
25 * TZIC Registers *
26 *****************************************
27 */
28
29#define TZIC_INTCNTL 0x0000 /* Control register */
30#define TZIC_INTTYPE 0x0004 /* Controller Type register */
31#define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */
32#define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */
33#define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */
34#define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */
35#define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
36#define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
37#define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
38#define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */
39#define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */
40#define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */
41#define TZIC_PND0 0x0D00 /* Pending Register 0 */
42#define TZIC_HIPND0 0x0D80 /* High Priority Pending Register */
43#define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */
44#define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */
45#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
46
47void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
48
49/**
50 * tzic_mask_irq() - Disable interrupt number "irq" in the TZIC
51 *
52 * @param irq interrupt source number
53 */
54static void tzic_mask_irq(unsigned int irq)
55{
56 int index, off;
57
58 index = irq >> 5;
59 off = irq & 0x1F;
60 __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index));
61}
62
63/**
64 * tzic_unmask_irq() - Enable interrupt number "irq" in the TZIC
65 *
66 * @param irq interrupt source number
67 */
68static void tzic_unmask_irq(unsigned int irq)
69{
70 int index, off;
71
72 index = irq >> 5;
73 off = irq & 0x1F;
74 __raw_writel(1 << off, tzic_base + TZIC_ENSET0(index));
75}
76
77static unsigned int wakeup_intr[4];
78
79/**
80 * tzic_set_wake_irq() - Set interrupt number "irq" in the TZIC as a wake-up source.
81 *
82 * @param irq interrupt source number
83 * @param enable enable as wake-up if equal to non-zero
84 * disble as wake-up if equal to zero
85 *
86 * @return This function returns 0 on success.
87 */
88static int tzic_set_wake_irq(unsigned int irq, unsigned int enable)
89{
90 unsigned int index, off;
91
92 index = irq >> 5;
93 off = irq & 0x1F;
94
95 if (index > 3)
96 return -EINVAL;
97
98 if (enable)
99 wakeup_intr[index] |= (1 << off);
100 else
101 wakeup_intr[index] &= ~(1 << off);
102
103 return 0;
104}
105
106static struct irq_chip mxc_tzic_chip = {
107 .name = "MXC_TZIC",
108 .ack = tzic_mask_irq,
109 .mask = tzic_mask_irq,
110 .unmask = tzic_unmask_irq,
111 .set_wake = tzic_set_wake_irq,
112};
113
114/*
115 * This function initializes the TZIC hardware and disables all the
116 * interrupts. It registers the interrupt enable and disable functions
117 * to the kernel for each interrupt source.
118 */
119void __init tzic_init_irq(void __iomem *irqbase)
120{
121 int i;
122
123 tzic_base = irqbase;
124 /* put the TZIC into the reset value with
125 * all interrupts disabled
126 */
127 i = __raw_readl(tzic_base + TZIC_INTCNTL);
128
129 __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL);
130 __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK);
131 __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL);
132
133 for (i = 0; i < 4; i++)
134 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
135
136 /* disable all interrupts */
137 for (i = 0; i < 4; i++)
138 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
139
140 /* all IRQ no FIQ Warning :: No selection */
141
142 for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
143 set_irq_chip(i, &mxc_tzic_chip);
144 set_irq_handler(i, handle_level_irq);
145 set_irq_flags(i, IRQF_VALID);
146 }
147
148 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
149}
150
151/**
152 * tzic_enable_wake() - enable wakeup interrupt
153 *
154 * @param is_idle 1 if called in idle loop (ENSET0 register);
155 * 0 to be used when called from low power entry
156 * @return 0 if successful; non-zero otherwise
157 */
158int tzic_enable_wake(int is_idle)
159{
160 unsigned int i, v;
161
162 __raw_writel(1, tzic_base + TZIC_DSMINT);
163 if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0))
164 return -EAGAIN;
165
166 for (i = 0; i < 4; i++) {
167 v = is_idle ? __raw_readl(TZIC_ENSET0(i)) : wakeup_intr[i];
168 __raw_writel(v, TZIC_WAKEUP0(i));
169 }
170
171 return 0;
172}
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