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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2009-03-13 17:44:51 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-03-13 17:44:51 -0400
commit97fb44eb6bc01f4ffed4300e475aa15e44877375 (patch)
tree481ed6efd0babe7185cae04f2fd295426b36411d /arch/arm/plat-mxc
parente4707dd3e9d0cb57597b6568a5e51fea5d6fca41 (diff)
parent148854c65ea8046b045672fd49f4333aefaa3ab5 (diff)
Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into devel
Conflicts: arch/arm/mach-at91/gpio.c
Diffstat (limited to 'arch/arm/plat-mxc')
-rw-r--r--arch/arm/plat-mxc/Kconfig10
-rw-r--r--arch/arm/plat-mxc/Makefile3
-rw-r--r--arch/arm/plat-mxc/clock.c54
-rw-r--r--arch/arm/plat-mxc/cpu.c11
-rw-r--r--arch/arm/plat-mxc/devices.c1
-rw-r--r--arch/arm/plat-mxc/dma-mx1-mx2.c2
-rw-r--r--arch/arm/plat-mxc/gpio.c2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx27ads.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31ads.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31moboard.h45
-rw-r--r--arch/arm/plat-mxc/include/mach/board-qong.h22
-rw-r--r--arch/arm/plat-mxc/include/mach/clkdev.h7
-rw-r--r--arch/arm/plat-mxc/include/mach/clock.h6
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h10
-rw-r--r--arch/arm/plat-mxc/include/mach/debug-macro.S3
-rw-r--r--arch/arm/plat-mxc/include/mach/hardware.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/imxfb.h86
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h416
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx1.h166
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx21.h126
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx27.h207
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx2x.h237
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx3.h74
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux.h127
-rw-r--r--arch/arm/plat-mxc/include/mach/memory.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/mx21.h78
-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h200
-rw-r--r--arch/arm/plat-mxc/include/mach/mx2x.h200
-rw-r--r--arch/arm/plat-mxc/include/mach/mx31.h329
-rw-r--r--arch/arm/plat-mxc/include/mach/mx35.h29
-rw-r--r--arch/arm/plat-mxc/include/mach/mx3x.h290
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h74
-rw-r--r--arch/arm/plat-mxc/iomux-mx1-mx2.c2
-rw-r--r--arch/arm/plat-mxc/pwm.c300
-rw-r--r--arch/arm/plat-mxc/time.c32
35 files changed, 2202 insertions, 965 deletions
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 9cc2b16fdf79..17d0e9906d5f 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -3,7 +3,7 @@ if ARCH_MXC
3menu "Freescale MXC Implementations" 3menu "Freescale MXC Implementations"
4 4
5choice 5choice
6 prompt "MXC/iMX Base Type" 6 prompt "Freescale CPU family:"
7 default ARCH_MX3 7 default ARCH_MX3
8 8
9config ARCH_MX1 9config ARCH_MX1
@@ -15,12 +15,14 @@ config ARCH_MX1
15config ARCH_MX2 15config ARCH_MX2
16 bool "MX2-based" 16 bool "MX2-based"
17 select CPU_ARM926T 17 select CPU_ARM926T
18 select COMMON_CLKDEV
18 help 19 help
19 This enables support for systems based on the Freescale i.MX2 family 20 This enables support for systems based on the Freescale i.MX2 family
20 21
21config ARCH_MX3 22config ARCH_MX3
22 bool "MX3-based" 23 bool "MX3-based"
23 select CPU_V6 24 select CPU_V6
25 select COMMON_CLKDEV
24 help 26 help
25 This enables support for systems based on the Freescale i.MX3 family 27 This enables support for systems based on the Freescale i.MX3 family
26 28
@@ -43,4 +45,10 @@ config MXC_IRQ_PRIOR
43 requirements for timing. 45 requirements for timing.
44 Say N here, unless you have a specialized requirement. 46 Say N here, unless you have a specialized requirement.
45 47
48config MXC_PWM
49 tristate "Enable PWM driver"
50 depends on ARCH_MXC
51 help
52 Enable support for the i.MX PWM controller(s).
53
46endif 54endif
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index db74a929179d..564fd4ebf38a 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -3,7 +3,8 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := irq.o clock.o gpio.o time.o devices.o 6obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o
7 7
8obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o 8obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o
9obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o 9obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o
10obj-$(CONFIG_MXC_PWM) += pwm.o
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 0a38f0b396eb..92e13566cd4f 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -48,6 +48,11 @@ static DEFINE_MUTEX(clocks_mutex);
48 *-------------------------------------------------------------------------*/ 48 *-------------------------------------------------------------------------*/
49 49
50/* 50/*
51 * All the code inside #ifndef CONFIG_COMMON_CLKDEV can be removed once all
52 * MXC architectures have switched to using clkdev.
53 */
54#ifndef CONFIG_COMMON_CLKDEV
55/*
51 * Retrieve a clock by name. 56 * Retrieve a clock by name.
52 * 57 *
53 * Note that we first try to use device id on the bus 58 * Note that we first try to use device id on the bus
@@ -110,6 +115,7 @@ found:
110 return clk; 115 return clk;
111} 116}
112EXPORT_SYMBOL(clk_get); 117EXPORT_SYMBOL(clk_get);
118#endif
113 119
114static void __clk_disable(struct clk *clk) 120static void __clk_disable(struct clk *clk)
115{ 121{
@@ -187,6 +193,7 @@ unsigned long clk_get_rate(struct clk *clk)
187} 193}
188EXPORT_SYMBOL(clk_get_rate); 194EXPORT_SYMBOL(clk_get_rate);
189 195
196#ifndef CONFIG_COMMON_CLKDEV
190/* Decrement the clock's module reference count */ 197/* Decrement the clock's module reference count */
191void clk_put(struct clk *clk) 198void clk_put(struct clk *clk)
192{ 199{
@@ -194,6 +201,7 @@ void clk_put(struct clk *clk)
194 module_put(clk->owner); 201 module_put(clk->owner);
195} 202}
196EXPORT_SYMBOL(clk_put); 203EXPORT_SYMBOL(clk_put);
204#endif
197 205
198/* Round the requested clock rate to the nearest supported 206/* Round the requested clock rate to the nearest supported
199 * rate that is less than or equal to the requested rate. 207 * rate that is less than or equal to the requested rate.
@@ -257,6 +265,7 @@ struct clk *clk_get_parent(struct clk *clk)
257} 265}
258EXPORT_SYMBOL(clk_get_parent); 266EXPORT_SYMBOL(clk_get_parent);
259 267
268#ifndef CONFIG_COMMON_CLKDEV
260/* 269/*
261 * Add a new clock to the clock tree. 270 * Add a new clock to the clock tree.
262 */ 271 */
@@ -327,4 +336,49 @@ static int __init mxc_setup_proc_entry(void)
327} 336}
328 337
329late_initcall(mxc_setup_proc_entry); 338late_initcall(mxc_setup_proc_entry);
339#endif /* CONFIG_PROC_FS */
340#endif
341
342/*
343 * Get the resulting clock rate from a PLL register value and the input
344 * frequency. PLLs with this register layout can at least be found on
345 * MX1, MX21, MX27 and MX31
346 *
347 * mfi + mfn / (mfd + 1)
348 * f = 2 * f_ref * --------------------
349 * pd + 1
350 */
351unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
352{
353 long long ll;
354 int mfn_abs;
355 unsigned int mfi, mfn, mfd, pd;
356
357 mfi = (reg_val >> 10) & 0xf;
358 mfn = reg_val & 0x3ff;
359 mfd = (reg_val >> 16) & 0x3ff;
360 pd = (reg_val >> 26) & 0xf;
361
362 mfi = mfi <= 5 ? 5 : mfi;
363
364 mfn_abs = mfn;
365
366#if !defined CONFIG_ARCH_MX1 && !defined CONFIG_ARCH_MX21
367 if (mfn >= 0x200) {
368 mfn |= 0xFFFFFE00;
369 mfn_abs = -mfn;
370 }
330#endif 371#endif
372
373 freq *= 2;
374 freq /= pd + 1;
375
376 ll = (unsigned long long)freq * mfn_abs;
377
378 do_div(ll, mfd + 1);
379 if (mfn < 0)
380 ll = -ll;
381 ll = (freq * mfi) + ll;
382
383 return ll;
384}
diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c
new file mode 100644
index 000000000000..386e0d52cf58
--- /dev/null
+++ b/arch/arm/plat-mxc/cpu.c
@@ -0,0 +1,11 @@
1
2#include <linux/module.h>
3
4unsigned int __mxc_cpu_type;
5EXPORT_SYMBOL(__mxc_cpu_type);
6
7void mxc_set_cpu_type(unsigned int type)
8{
9 __mxc_cpu_type = type;
10}
11
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
index c66748267c45..56f2fb5cc456 100644
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/plat-mxc/devices.c
@@ -19,6 +19,7 @@
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <mach/common.h>
22 23
23int __init mxc_register_device(struct platform_device *pdev, void *data) 24int __init mxc_register_device(struct platform_device *pdev, void *data)
24{ 25{
diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c
index a9bab15f0fd0..e364a5ed10f1 100644
--- a/arch/arm/plat-mxc/dma-mx1-mx2.c
+++ b/arch/arm/plat-mxc/dma-mx1-mx2.c
@@ -802,7 +802,7 @@ static int __init imx_dma_init(void)
802 int ret = 0; 802 int ret = 0;
803 int i; 803 int i;
804 804
805 dma_clk = clk_get(NULL, "dma_clk"); 805 dma_clk = clk_get(NULL, "dma");
806 clk_enable(dma_clk); 806 clk_enable(dma_clk);
807 807
808 /* reset DMA module */ 808 /* reset DMA module */
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index ccbd94adc668..c6483bad8a26 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -200,8 +200,8 @@ static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
200static int mxc_gpio_direction_output(struct gpio_chip *chip, 200static int mxc_gpio_direction_output(struct gpio_chip *chip,
201 unsigned offset, int value) 201 unsigned offset, int value)
202{ 202{
203 _set_gpio_direction(chip, offset, 1);
204 mxc_gpio_set(chip, offset, value); 203 mxc_gpio_set(chip, offset, value);
204 _set_gpio_direction(chip, offset, 1);
205 return 0; 205 return 0;
206} 206}
207 207
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
index 8f34a05afc87..1cac9d1135cd 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
@@ -48,7 +48,8 @@
48 * Base address of PBC controller, CS4 48 * Base address of PBC controller, CS4
49 */ 49 */
50#define PBC_BASE_ADDRESS 0xEB000000 50#define PBC_BASE_ADDRESS 0xEB000000
51#define PBC_REG_ADDR(offset) (PBC_BASE_ADDRESS + (offset)) 51#define PBC_REG_ADDR(offset) (void __force __iomem *) \
52 (PBC_BASE_ADDRESS + (offset))
52 53
53/* 54/*
54 * PBC Interupt name definitions 55 * PBC Interupt name definitions
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
index 451d510d08c3..318c72ada13d 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
@@ -11,6 +11,8 @@
11#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ 11#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
12#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ 12#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
13 13
14#include <mach/hardware.h>
15
14/* Base address of PBC controller */ 16/* Base address of PBC controller */
15#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) 17#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR)
16/* Offsets for the PBC Controller register */ 18/* Offsets for the PBC Controller register */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
new file mode 100644
index 000000000000..f8aef1babb75
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
@@ -0,0 +1,45 @@
1/*
2 * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
20#define __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
21
22/* mandatory for CONFIG_LL_DEBUG */
23
24#define MXC_LL_UART_PADDR UART1_BASE_ADDR
25#define MXC_LL_UART_VADDR (AIPI_BASE_ADDR_VIRT + 0x0A000)
26
27#ifndef __ASSEMBLY__
28
29enum mx31moboard_boards {
30 MX31NOBOARD = 0,
31 MX31DEVBOARD = 1,
32 MX31MARXBOT = 2,
33};
34
35/*
36 * This CPU module needs a baseboard to work. After basic initializing
37 * its own devices, it calls baseboard's init function.
38 */
39
40extern void mx31moboard_devboard_init(void);
41extern void mx31moboard_marxbot_init(void);
42
43#endif
44
45#endif /* __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-qong.h b/arch/arm/plat-mxc/include/mach/board-qong.h
new file mode 100644
index 000000000000..4ff762dd45cf
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-qong.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_QONG_H__
12#define __ASM_ARCH_MXC_BOARD_QONG_H__
13
14/* mandatory for CONFIG_LL_DEBUG */
15
16#define MXC_LL_UART_PADDR UART1_BASE_ADDR
17#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
18
19/* NOR FLASH */
20#define QONG_NOR_SIZE (128*1024*1024)
21
22#endif /* __ASM_ARCH_MXC_BOARD_QONG_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/clkdev.h b/arch/arm/plat-mxc/include/mach/clkdev.h
new file mode 100644
index 000000000000..04b37a89801c
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_MACH_CLKDEV_H
2#define __ASM_MACH_CLKDEV_H
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do { } while (0)
6
7#endif
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
index d21f78e78819..43a82d0c534d 100644
--- a/arch/arm/plat-mxc/include/mach/clock.h
+++ b/arch/arm/plat-mxc/include/mach/clock.h
@@ -26,9 +26,13 @@
26struct module; 26struct module;
27 27
28struct clk { 28struct clk {
29#ifndef CONFIG_COMMON_CLKDEV
30 /* As soon as i.MX1 and i.MX31 switched to clkdev, this
31 * block can go away */
29 struct list_head node; 32 struct list_head node;
30 struct module *owner; 33 struct module *owner;
31 const char *name; 34 const char *name;
35#endif
32 int id; 36 int id;
33 /* Source clock this clk depends on */ 37 /* Source clock this clk depends on */
34 struct clk *parent; 38 struct clk *parent;
@@ -63,5 +67,7 @@ struct clk {
63int clk_register(struct clk *clk); 67int clk_register(struct clk *clk);
64void clk_unregister(struct clk *clk); 68void clk_unregister(struct clk *clk);
65 69
70unsigned long mxc_decode_pll(unsigned int pll, u32 f_ref);
71
66#endif /* __ASSEMBLY__ */ 72#endif /* __ASSEMBLY__ */
67#endif /* __ASM_ARCH_MXC_CLOCK_H__ */ 73#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 6350287a59b9..b2f9b72644db 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -12,12 +12,18 @@
12#define __ASM_ARCH_MXC_COMMON_H__ 12#define __ASM_ARCH_MXC_COMMON_H__
13 13
14struct platform_device; 14struct platform_device;
15struct clk;
15 16
16extern void mxc_map_io(void); 17extern void mxc_map_io(void);
17extern void mxc_init_irq(void); 18extern void mxc_init_irq(void);
18extern void mxc_timer_init(const char *clk_timer); 19extern void mxc_timer_init(struct clk *timer_clk);
19extern int mxc_clocks_init(unsigned long fref); 20extern int mx1_clocks_init(unsigned long fref);
21extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
22extern int mx27_clocks_init(unsigned long fref);
23extern int mx31_clocks_init(unsigned long fref);
24extern int mx35_clocks_init(void);
20extern int mxc_register_gpios(void); 25extern int mxc_register_gpios(void);
21extern int mxc_register_device(struct platform_device *pdev, void *data); 26extern int mxc_register_device(struct platform_device *pdev, void *data);
27extern void mxc_set_cpu_type(unsigned int type);
22 28
23#endif 29#endif
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 602768b427e2..4f773148bc20 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -31,6 +31,9 @@
31#ifdef CONFIG_MACH_MX31_3DS 31#ifdef CONFIG_MACH_MX31_3DS
32#include <mach/board-mx31pdk.h> 32#include <mach/board-mx31pdk.h>
33#endif 33#endif
34#ifdef CONFIG_MACH_QONG
35#include <mach/board-qong.h>
36#endif
34 .macro addruart,rx 37 .macro addruart,rx
35 mrc p15, 0, \rx, c1, c0 38 mrc p15, 0, \rx, c1, c0
36 tst \rx, #1 @ MMU enabled? 39 tst \rx, #1 @ MMU enabled?
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index a612d8bb73c8..42e4ee37ca1f 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -23,10 +23,16 @@
23#include <asm/sizes.h> 23#include <asm/sizes.h>
24 24
25#ifdef CONFIG_ARCH_MX3 25#ifdef CONFIG_ARCH_MX3
26# include <mach/mx31.h> 26#include <mach/mx3x.h>
27#include <mach/mx31.h>
28#include <mach/mx35.h>
27#endif 29#endif
28 30
29#ifdef CONFIG_ARCH_MX2 31#ifdef CONFIG_ARCH_MX2
32# include <mach/mx2x.h>
33# ifdef CONFIG_MACH_MX21
34# include <mach/mx21.h>
35# endif
30# ifdef CONFIG_MACH_MX27 36# ifdef CONFIG_MACH_MX27
31# include <mach/mx27.h> 37# include <mach/mx27.h>
32# endif 38# endif
diff --git a/arch/arm/plat-mxc/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h
new file mode 100644
index 000000000000..762a7b0430e2
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/imxfb.h
@@ -0,0 +1,86 @@
1/*
2 * This structure describes the machine which we are running on.
3 */
4
5#define PCR_TFT (1 << 31)
6#define PCR_COLOR (1 << 30)
7#define PCR_PBSIZ_1 (0 << 28)
8#define PCR_PBSIZ_2 (1 << 28)
9#define PCR_PBSIZ_4 (2 << 28)
10#define PCR_PBSIZ_8 (3 << 28)
11#define PCR_BPIX_1 (0 << 25)
12#define PCR_BPIX_2 (1 << 25)
13#define PCR_BPIX_4 (2 << 25)
14#define PCR_BPIX_8 (3 << 25)
15#define PCR_BPIX_12 (4 << 25)
16#define PCR_BPIX_16 (4 << 25)
17#define PCR_PIXPOL (1 << 24)
18#define PCR_FLMPOL (1 << 23)
19#define PCR_LPPOL (1 << 22)
20#define PCR_CLKPOL (1 << 21)
21#define PCR_OEPOL (1 << 20)
22#define PCR_SCLKIDLE (1 << 19)
23#define PCR_END_SEL (1 << 18)
24#define PCR_END_BYTE_SWAP (1 << 17)
25#define PCR_REV_VS (1 << 16)
26#define PCR_ACD_SEL (1 << 15)
27#define PCR_ACD(x) (((x) & 0x7f) << 8)
28#define PCR_SCLK_SEL (1 << 7)
29#define PCR_SHARP (1 << 6)
30#define PCR_PCD(x) ((x) & 0x3f)
31
32#define PWMR_CLS(x) (((x) & 0x1ff) << 16)
33#define PWMR_LDMSK (1 << 15)
34#define PWMR_SCR1 (1 << 10)
35#define PWMR_SCR0 (1 << 9)
36#define PWMR_CC_EN (1 << 8)
37#define PWMR_PW(x) ((x) & 0xff)
38
39#define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26)
40#define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16)
41#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8)
42#define LSCR1_GRAY2(x) (((x) & 0xf) << 4)
43#define LSCR1_GRAY1(x) (((x) & 0xf))
44
45#define DMACR_BURST (1 << 31)
46#define DMACR_HM(x) (((x) & 0xf) << 16)
47#define DMACR_TM(x) ((x) & 0xf)
48
49struct imx_fb_platform_data {
50 u_long pixclock;
51
52 u_short xres;
53 u_short yres;
54
55 u_int nonstd;
56 u_char bpp;
57 u_char hsync_len;
58 u_char left_margin;
59 u_char right_margin;
60
61 u_char vsync_len;
62 u_char upper_margin;
63 u_char lower_margin;
64 u_char sync;
65
66 u_int cmap_greyscale:1,
67 cmap_inverse:1,
68 cmap_static:1,
69 unused:29;
70
71 u_int pcr;
72 u_int pwmr;
73 u_int lscr1;
74 u_int dmacr;
75
76 u_char * fixed_screen_cpu;
77 dma_addr_t fixed_screen_dma;
78
79 int (*init)(struct platform_device*);
80 int (*exit)(struct platform_device*);
81
82 void (*lcd_power)(int);
83 void (*backlight_power)(int);
84};
85
86void set_imx_fb_info(struct imx_fb_platform_data *);
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
deleted file mode 100644
index 95a383be628e..000000000000
--- a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
+++ /dev/null
@@ -1,416 +0,0 @@
1/*
2 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef _MXC_GPIO_MX1_MX2_H
20#define _MXC_GPIO_MX1_MX2_H
21
22#include <linux/io.h>
23
24/*
25 * GPIO Module and I/O Multiplexer
26 * x = 0..3 for reg_A, reg_B, reg_C, reg_D
27 */
28#define VA_GPIO_BASE IO_ADDRESS(GPIO_BASE_ADDR)
29#define MXC_DDIR(x) (0x00 + ((x) << 8))
30#define MXC_OCR1(x) (0x04 + ((x) << 8))
31#define MXC_OCR2(x) (0x08 + ((x) << 8))
32#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
33#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
34#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
35#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
36#define MXC_DR(x) (0x1c + ((x) << 8))
37#define MXC_GIUS(x) (0x20 + ((x) << 8))
38#define MXC_SSR(x) (0x24 + ((x) << 8))
39#define MXC_ICR1(x) (0x28 + ((x) << 8))
40#define MXC_ICR2(x) (0x2c + ((x) << 8))
41#define MXC_IMR(x) (0x30 + ((x) << 8))
42#define MXC_ISR(x) (0x34 + ((x) << 8))
43#define MXC_GPR(x) (0x38 + ((x) << 8))
44#define MXC_SWR(x) (0x3c + ((x) << 8))
45#define MXC_PUEN(x) (0x40 + ((x) << 8))
46
47#ifdef CONFIG_ARCH_MX1
48# define GPIO_PORT_MAX 3
49#endif
50#ifdef CONFIG_ARCH_MX2
51# define GPIO_PORT_MAX 5
52#endif
53
54#ifndef GPIO_PORT_MAX
55# error "GPIO config port count unknown!"
56#endif
57
58#define GPIO_PIN_MASK 0x1f
59
60#define GPIO_PORT_SHIFT 5
61#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
62
63#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
64#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
65#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
66#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
67#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
68#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
69
70#define GPIO_OUT (1 << 8)
71#define GPIO_IN (0 << 8)
72#define GPIO_PUEN (1 << 9)
73
74#define GPIO_PF (1 << 10)
75#define GPIO_AF (1 << 11)
76
77#define GPIO_OCR_SHIFT 12
78#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
79#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
80#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
81#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
82#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
83
84#define GPIO_AOUT_SHIFT 14
85#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
86#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
87#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
88#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
89#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
90
91#define GPIO_BOUT_SHIFT 16
92#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
93#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
94#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
95#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
96#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
97
98extern void mxc_gpio_mode(int gpio_mode);
99extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
100 const char *label);
101extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
102
103/*-------------------------------------------------------------------------*/
104
105/* assignements for GPIO alternate/primary functions */
106
107/* FIXME: This list is not completed. The correct directions are
108 * missing on some (many) pins
109 */
110#ifdef CONFIG_ARCH_MX1
111#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_OUT | 0)
112#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0)
113#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_IN | 1)
114#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1)
115#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 2)
116#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3)
117#define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4)
118#define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5)
119#define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6)
120#define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7)
121#define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8)
122#define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9)
123#define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10)
124#define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11)
125#define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12)
126#define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13)
127#define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14)
128#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15)
129#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16)
130#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
131#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_OUT | 17)
132#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
133#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
134#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
135#define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21)
136#define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22)
137#define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23)
138#define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24)
139#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24)
140#define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25)
141#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25)
142#define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26)
143#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26)
144#define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27)
145#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27)
146#define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28)
147#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28)
148#define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29)
149#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29)
150#define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30)
151#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30)
152#define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31)
153#define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31)
154#define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
155#define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8)
156#define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9)
157#define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9)
158#define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10)
159#define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10)
160#define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11)
161#define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11)
162#define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12)
163#define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12)
164#define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
165#define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13)
166#define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14)
167#define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15)
168#define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_IN | GPIO_AF | 16)
169#define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_OUT | GPIO_AF | 17)
170#define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18)
171#define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19)
172#define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20)
173#define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21)
174#define PB22_PFUSBD_RCV (GPIO_PORTB | GPIO_PF | 22)
175#define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23)
176#define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24)
177#define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25)
178#define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26)
179#define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27)
180#define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_OUT | GPIO_PF | 28)
181#define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_IN | GPIO_PF | 29)
182#define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_OUT | GPIO_PF | 30)
183#define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_IN | GPIO_PF | 31)
184#define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3)
185#define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4)
186#define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_IN | GPIO_PF | 5)
187#define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
188#define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7)
189#define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8)
190#define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
191#define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_IN | GPIO_PF | 10)
192#define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
193#define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 12)
194#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13)
195#define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14)
196#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15)
197#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16)
198#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17)
199#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24)
200#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25)
201#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_IN | 26)
202#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27)
203#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28)
204#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_IN | 29)
205#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30)
206#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_IN | 31)
207#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 6)
208#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7)
209#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_IN | GPIO_AF | 7)
210#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7)
211#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8)
212#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_OUT | GPIO_AF | 8)
213#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8)
214#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9)
215#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_OUT | GPIO_AF | 9)
216#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_IN | 9)
217#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_OUT | GPIO_PF | 10)
218#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_OUT | GPIO_AF | 10)
219#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_OUT | 10)
220#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_OUT | GPIO_PF | 11)
221#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_OUT | GPIO_PF | 12)
222#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_OUT | GPIO_PF | 13)
223#define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_OUT | GPIO_PF | 14)
224#define PD15_PF_LD0 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 15)
225#define PD16_PF_LD1 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 16)
226#define PD17_PF_LD2 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
227#define PD18_PF_LD3 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
228#define PD19_PF_LD4 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 19)
229#define PD20_PF_LD5 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 20)
230#define PD21_PF_LD6 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 21)
231#define PD22_PF_LD7 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 22)
232#define PD23_PF_LD8 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 23)
233#define PD24_PF_LD9 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 24)
234#define PD25_PF_LD10 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25)
235#define PD26_PF_LD11 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26)
236#define PD27_PF_LD12 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27)
237#define PD28_PF_LD13 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28)
238#define PD29_PF_LD14 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29)
239#define PD30_PF_LD15 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 30)
240#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31)
241#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31)
242#endif
243
244#ifdef CONFIG_ARCH_MX2
245#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0)
246#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1)
247#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2)
248#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3)
249#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4)
250#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_OUT | GPIO_PF | 5)
251#define PA6_PF_LD0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 6)
252#define PA7_PF_LD1 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 7)
253#define PA8_PF_LD2 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 8)
254#define PA9_PF_LD3 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 9)
255#define PA10_PF_LD4 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 10)
256#define PA11_PF_LD5 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 11)
257#define PA12_PF_LD6 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 12)
258#define PA13_PF_LD7 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 13)
259#define PA14_PF_LD8 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 14)
260#define PA15_PF_LD9 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15)
261#define PA16_PF_LD10 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16)
262#define PA17_PF_LD11 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 17)
263#define PA18_PF_LD12 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 18)
264#define PA19_PF_LD13 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 19)
265#define PA20_PF_LD14 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 20)
266#define PA21_PF_LD15 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 21)
267#define PA22_PF_LD16 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 22)
268#define PA23_PF_LD17 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 23)
269#define PA24_PF_REV (GPIO_PORTA | GPIO_OUT | GPIO_PF | 24)
270#define PA25_PF_CLS (GPIO_PORTA | GPIO_OUT | GPIO_PF | 25)
271#define PA26_PF_PS (GPIO_PORTA | GPIO_OUT | GPIO_PF | 26)
272#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_OUT | GPIO_PF | 27)
273#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_OUT | GPIO_PF | 28)
274#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_OUT | GPIO_PF | 29)
275#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_OUT | GPIO_PF | 30)
276#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_OUT | GPIO_PF | 31)
277#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4)
278#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5)
279#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6)
280#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7)
281#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8)
282#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9)
283#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 10)
284#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 10)
285#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 11)
286#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 11)
287#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 12)
288#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 12)
289#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 13)
290#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_IN | GPIO_AF | 13)
291#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 14)
292#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_OUT | GPIO_PF | 15)
293#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_OUT | GPIO_PF | 16)
294#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 17)
295#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 18)
296#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 18)
297#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 19)
298#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 19)
299#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_OUT | GPIO_PF | 20)
300#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 20)
301#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_OUT | GPIO_PF | 21)
302#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_IN | GPIO_AF | 21)
303#define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22)
304#define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23)
305#define PB24_PF_USB_OC_B (GPIO_PORTB | GPIO_PF | 24)
306#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25)
307#define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26)
308#define PB27_PF_USBH1_OE_B (GPIO_PORTB | GPIO_PF | 27)
309#define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28)
310#define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29)
311#define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30)
312#define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31)
313#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_IN | GPIO_PF | 26)
314#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 28)
315#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 29)
316#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 31)
317#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_IN | GPIO_PF | 5)
318#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_IN | GPIO_PF | 6)
319#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7)
320#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8)
321#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
322#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10)
323#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
324#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12)
325#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13)
326#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 16)
327#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 17)
328#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 18)
329#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 19)
330#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 20)
331#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 21)
332#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 22)
333#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 23)
334#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 24)
335#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 25)
336#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 26)
337#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 27)
338#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 28)
339#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 29)
340#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 30)
341#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 31)
342#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
343#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
344#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
345#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
346#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
347#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
348#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
349#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
350#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
351#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
352#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
353#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
354#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
355#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
356#define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
357#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
358#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
359#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
360#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
361#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19)
362#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20)
363#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21)
364#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22)
365#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23)
366#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24)
367#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25)
368#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26)
369#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26)
370#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27)
371#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28)
372#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29)
373#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_IN | GPIO_PF | 30)
374#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_OUT | GPIO_PF | 31)
375#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
376#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0)
377#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1)
378#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2)
379#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
380#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4)
381#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
382#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7)
383#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
384#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9)
385#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
386#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11)
387#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
388#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13)
389#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
390#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15)
391#define PE16_AF_RTCK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 16)
392#define PE16_PF_RTCK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 16)
393#define PE18_PF_SDHC1_D0 (GPIO_PORTE | GPIO_PF | 18)
394#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_IN | GPIO_AF | 18)
395#define PE19_PF_SDHC1_D1 (GPIO_PORTE | GPIO_PF | 19)
396#define PE20_PF_SDHC1_D2 (GPIO_PORTE | GPIO_PF | 20)
397#define PE21_PF_SDHC1_D3 (GPIO_PORTE | GPIO_PF | 21)
398#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21)
399#define PE22_PF_SDHC1_CMD (GPIO_PORTE | GPIO_PF | 22)
400#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22)
401#define PE22_PF_SDHC1_CLK (GPIO_PORTE | GPIO_PF | 23)
402#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 23)
403#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24)
404#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25)
405#endif
406
407/* decode irq number to use with IMR(x), ISR(x) and friends */
408#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5)
409
410#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x)
411#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
412#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
413#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
414#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x)
415
416#endif /* _MXC_GPIO_MX1_MX2_H */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1.h b/arch/arm/plat-mxc/include/mach/iomux-mx1.h
new file mode 100644
index 000000000000..bf23305c19cc
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx1.h
@@ -0,0 +1,166 @@
1/*
2* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3*
4* This program is free software; you can redistribute it and/or
5* modify it under the terms of the GNU General Public License
6* as published by the Free Software Foundation; either version 2
7* of the License, or (at your option) any later version.
8* This program is distributed in the hope that it will be useful,
9* but WITHOUT ANY WARRANTY; without even the implied warranty of
10* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11* GNU General Public License for more details.
12*
13* You should have received a copy of the GNU General Public License
14* along with this program; if not, write to the Free Software
15* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16* MA 02110-1301, USA.
17*/
18
19#ifndef _MXC_IOMUX_MX1_H
20#define _MXC_IOMUX_MX1_H
21
22#ifndef GPIO_PORTA
23#error Please include mach/iomux.h
24#endif
25
26/* FIXME: This list is not completed. The correct directions are
27* missing on some (many) pins
28*/
29
30
31/* Primary GPIO pin functions */
32
33#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
34#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0)
35#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 1)
36#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1)
37#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 2)
38#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3)
39#define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4)
40#define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5)
41#define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6)
42#define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7)
43#define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8)
44#define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9)
45#define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10)
46#define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11)
47#define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12)
48#define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13)
49#define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14)
50#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
51#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
52#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
53#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
54#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
55#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
56#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
57#define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21)
58#define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22)
59#define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23)
60#define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24)
61#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24)
62#define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25)
63#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25)
64#define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26)
65#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26)
66#define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27)
67#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27)
68#define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28)
69#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28)
70#define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29)
71#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29)
72#define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30)
73#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30)
74#define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31)
75#define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31)
76#define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
77#define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8)
78#define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9)
79#define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9)
80#define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10)
81#define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10)
82#define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11)
83#define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11)
84#define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12)
85#define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12)
86#define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
87#define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13)
88#define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14)
89#define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15)
90#define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_AF | GPIO_IN | 16)
91#define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_AF | GPIO_OUT | 17)
92#define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18)
93#define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19)
94#define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20)
95#define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21)
96#define PB22_PF_USBD_RCV (GPIO_PORTB | GPIO_PF | 22)
97#define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23)
98#define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24)
99#define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25)
100#define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26)
101#define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27)
102#define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_PF | GPIO_OUT | 28)
103#define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_PF | GPIO_IN | 29)
104#define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_PF | GPIO_OUT | 30)
105#define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_PF | GPIO_IN | 31)
106#define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3)
107#define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4)
108#define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
109#define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_PF | GPIO_OUT | 6)
110#define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7)
111#define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8)
112#define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
113#define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_PF | GPIO_IN | 10)
114#define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
115#define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 12)
116#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13)
117#define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14)
118#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15)
119#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16)
120#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17)
121#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 24)
122#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 25)
123#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 26)
124#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 27)
125#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 28)
126#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 29)
127#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30)
128#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 31)
129#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 6)
130#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7)
131#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_AF | GPIO_IN | 7)
132#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7)
133#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8)
134#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_AF | GPIO_OUT | 8)
135#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8)
136#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9)
137#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_AF | GPIO_OUT | 9)
138#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 9)
139#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_PF | GPIO_OUT | 10)
140#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_AF | GPIO_OUT | 10)
141#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 10)
142#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_PF | GPIO_OUT | 11)
143#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_PF | GPIO_OUT | 12)
144#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 13)
145#define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 14)
146#define PD15_PF_LD0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 15)
147#define PD16_PF_LD1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 16)
148#define PD17_PF_LD2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
149#define PD18_PF_LD3 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
150#define PD19_PF_LD4 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19)
151#define PD20_PF_LD5 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20)
152#define PD21_PF_LD6 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21)
153#define PD22_PF_LD7 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22)
154#define PD23_PF_LD8 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 23)
155#define PD24_PF_LD9 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24)
156#define PD25_PF_LD10 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
157#define PD26_PF_LD11 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
158#define PD27_PF_LD12 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
159#define PD28_PF_LD13 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
160#define PD29_PF_LD14 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
161#define PD30_PF_LD15 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 30)
162#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31)
163#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31)
164
165
166#endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx21.h b/arch/arm/plat-mxc/include/mach/iomux-mx21.h
new file mode 100644
index 000000000000..63aaa972e275
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx21.h
@@ -0,0 +1,126 @@
1/*
2* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
3*
4* This program is free software; you can redistribute it and/or
5* modify it under the terms of the GNU General Public License
6* as published by the Free Software Foundation; either version 2
7* of the License, or (at your option) any later version.
8* This program is distributed in the hope that it will be useful,
9* but WITHOUT ANY WARRANTY; without even the implied warranty of
10* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11* GNU General Public License for more details.
12*
13* You should have received a copy of the GNU General Public License
14* along with this program; if not, write to the Free Software
15* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16* MA 02110-1301, USA.
17*/
18
19#ifndef _MXC_IOMUX_MX21_H
20#define _MXC_IOMUX_MX21_H
21
22#ifndef GPIO_PORTA
23#error Please include mach/iomux.h
24#endif
25
26
27/* Primary GPIO pin functions */
28
29#define PB22_PF_USBH1_BYP (GPIO_PORTB | GPIO_PF | 22)
30#define PB25_PF_USBH1_ON (GPIO_PORTB | GPIO_PF | 25)
31#define PC5_PF_USBOTG_SDA (GPIO_PORTC | GPIO_PF | 5)
32#define PC6_PF_USBOTG_SCL (GPIO_PORTC | GPIO_PF | 6)
33#define PC7_PF_USBOTG_ON (GPIO_PORTC | GPIO_PF | 7)
34#define PC8_PF_USBOTG_FS (GPIO_PORTC | GPIO_PF | 8)
35#define PC9_PF_USBOTG_OE (GPIO_PORTC | GPIO_PF | 9)
36#define PC10_PF_USBOTG_TXDM (GPIO_PORTC | GPIO_PF | 10)
37#define PC11_PF_USBOTG_TXDP (GPIO_PORTC | GPIO_PF | 11)
38#define PC12_PF_USBOTG_RXDM (GPIO_PORTC | GPIO_PF | 12)
39#define PC13_PF_USBOTG_RXDP (GPIO_PORTC | GPIO_PF | 13)
40#define PC16_PF_SAP_FS (GPIO_PORTC | GPIO_PF | 16)
41#define PC17_PF_SAP_RXD (GPIO_PORTC | GPIO_PF | 17)
42#define PC18_PF_SAP_TXD (GPIO_PORTC | GPIO_PF | 18)
43#define PC19_PF_SAP_CLK (GPIO_PORTC | GPIO_PF | 19)
44#define PE0_PF_TEST_WB2 (GPIO_PORTE | GPIO_PF | 0)
45#define PE1_PF_TEST_WB1 (GPIO_PORTE | GPIO_PF | 1)
46#define PE2_PF_TEST_WB0 (GPIO_PORTE | GPIO_PF | 2)
47#define PF1_PF_NFCE (GPIO_PORTF | GPIO_PF | 1)
48#define PF3_PF_NFCLE (GPIO_PORTF | GPIO_PF | 3)
49#define PF7_PF_NFIO0 (GPIO_PORTF | GPIO_PF | 7)
50#define PF8_PF_NFIO1 (GPIO_PORTF | GPIO_PF | 8)
51#define PF9_PF_NFIO2 (GPIO_PORTF | GPIO_PF | 9)
52#define PF10_PF_NFIO3 (GPIO_PORTF | GPIO_PF | 10)
53#define PF11_PF_NFIO4 (GPIO_PORTF | GPIO_PF | 11)
54#define PF12_PF_NFIO5 (GPIO_PORTF | GPIO_PF | 12)
55#define PF13_PF_NFIO6 (GPIO_PORTF | GPIO_PF | 13)
56#define PF14_PF_NFIO7 (GPIO_PORTF | GPIO_PF | 14)
57#define PF16_PF_RES (GPIO_PORTF | GPIO_PF | 16)
58
59/* Alternate GPIO pin functions */
60
61#define PA5_AF_BMI_CLK_CS (GPIO_PORTA | GPIO_AF | 5)
62#define PA6_AF_BMI_D0 (GPIO_PORTA | GPIO_AF | 6)
63#define PA7_AF_BMI_D1 (GPIO_PORTA | GPIO_AF | 7)
64#define PA8_AF_BMI_D2 (GPIO_PORTA | GPIO_AF | 8)
65#define PA9_AF_BMI_D3 (GPIO_PORTA | GPIO_AF | 9)
66#define PA10_AF_BMI_D4 (GPIO_PORTA | GPIO_AF | 10)
67#define PA11_AF_BMI_D5 (GPIO_PORTA | GPIO_AF | 11)
68#define PA12_AF_BMI_D6 (GPIO_PORTA | GPIO_AF | 12)
69#define PA13_AF_BMI_D7 (GPIO_PORTA | GPIO_AF | 13)
70#define PA14_AF_BMI_D8 (GPIO_PORTA | GPIO_AF | 14)
71#define PA15_AF_BMI_D9 (GPIO_PORTA | GPIO_AF | 15)
72#define PA16_AF_BMI_D10 (GPIO_PORTA | GPIO_AF | 16)
73#define PA17_AF_BMI_D11 (GPIO_PORTA | GPIO_AF | 17)
74#define PA18_AF_BMI_D12 (GPIO_PORTA | GPIO_AF | 18)
75#define PA19_AF_BMI_D13 (GPIO_PORTA | GPIO_AF | 19)
76#define PA20_AF_BMI_D14 (GPIO_PORTA | GPIO_AF | 20)
77#define PA21_AF_BMI_D15 (GPIO_PORTA | GPIO_AF | 21)
78#define PA22_AF_BMI_READ_REQ (GPIO_PORTA | GPIO_AF | 22)
79#define PA23_AF_BMI_WRITE (GPIO_PORTA | GPIO_AF | 23)
80#define PA29_AF_BMI_RX_FULL (GPIO_PORTA | GPIO_AF | 29)
81#define PA30_AF_BMI_READ (GPIO_PORTA | GPIO_AF | 30)
82
83/* AIN GPIO pin functions */
84
85#define PC14_AIN_SYS_CLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14)
86#define PD21_AIN_USBH2_FS (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21)
87#define PD22_AIN_USBH2_OE (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22)
88#define PD23_AIN_USBH2_TXDM (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23)
89#define PD24_AIN_USBH2_TXDP (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24)
90#define PE8_AIN_IR_TXD (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8)
91#define PF0_AIN_PC_RST (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0)
92#define PF1_AIN_PC_CE1 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1)
93#define PF2_AIN_PC_CE2 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2)
94#define PF3_AIN_PC_POE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3)
95#define PF4_AIN_PC_OE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4)
96#define PF5_AIN_PC_RW (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5)
97
98/* BIN GPIO pin functions */
99
100#define PC14_BIN_SYS_CLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14)
101#define PD27_BIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27)
102
103/* CIN GPIO pin functions */
104
105#define PB26_CIN_USBH1_RXDAT (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26)
106
107/* AOUT GPIO pin functions */
108
109#define PA29_AOUT_BMI_WAIT (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29)
110#define PD19_AOUT_USBH2_RXDM (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19)
111#define PD20_AOUT_USBH2_RXDP (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20)
112#define PD25_AOUT_EXT_DMAREQ (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25)
113#define PD26_AOUT_USBOTG_RXDAT (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26)
114#define PE9_AOUT_IR_RXD (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9)
115#define PF6_AOUT_PC_BVD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6)
116#define PF7_AOUT_PC_BVD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7)
117#define PF8_AOUT_PC_VS2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8)
118#define PF9_AOUT_PC_VS1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9)
119#define PF10_AOUT_PC_WP (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10)
120#define PF11_AOUT_PC_READY (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11)
121#define PF12_AOUT_PC_WAIT (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12)
122#define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13)
123#define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14)
124
125
126#endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx27.h b/arch/arm/plat-mxc/include/mach/iomux-mx27.h
new file mode 100644
index 000000000000..5ac158b70f61
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx27.h
@@ -0,0 +1,207 @@
1/*
2* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
4*
5* This program is free software; you can redistribute it and/or
6* modify it under the terms of the GNU General Public License
7* as published by the Free Software Foundation; either version 2
8* of the License, or (at your option) any later version.
9* This program is distributed in the hope that it will be useful,
10* but WITHOUT ANY WARRANTY; without even the implied warranty of
11* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12* GNU General Public License for more details.
13*
14* You should have received a copy of the GNU General Public License
15* along with this program; if not, write to the Free Software
16* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17* MA 02110-1301, USA.
18*/
19
20#ifndef _MXC_IOMUX_MX27_H
21#define _MXC_IOMUX_MX27_H
22
23#ifndef GPIO_PORTA
24#error Please include mach/iomux.h
25#endif
26
27
28/* Primary GPIO pin functions */
29
30#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0)
31#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1)
32#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2)
33#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3)
34#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4)
35#define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22)
36#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25)
37#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
38#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_PF | GPIO_IN | 6)
39#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7)
40#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8)
41#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
42#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10)
43#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
44#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12)
45#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13)
46#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 16)
47#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17)
48#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18)
49#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 19)
50#define PC25_AF_GPT5_TIN (GPIO_PORTC | GPIO_AF | 25)
51#define PC27_AF_GPT4_TIN (GPIO_PORTC | GPIO_AF | 27)
52#define PD0_PF_SD3_CMD (GPIO_PORTD | GPIO_PF | 0)
53#define PD1_PF_SD3_CLK (GPIO_PORTD | GPIO_PF | 1)
54#define PD2_PF_ATA_DATA0 (GPIO_PORTD | GPIO_PF | 2)
55#define PD3_PF_ATA_DATA1 (GPIO_PORTD | GPIO_PF | 3)
56#define PD4_PF_ATA_DATA2 (GPIO_PORTD | GPIO_PF | 4)
57#define PD5_PF_ATA_DATA3 (GPIO_PORTD | GPIO_PF | 5)
58#define PD6_PF_ATA_DATA4 (GPIO_PORTD | GPIO_PF | 6)
59#define PD7_PF_ATA_DATA5 (GPIO_PORTD | GPIO_PF | 7)
60#define PD8_PF_ATA_DATA6 (GPIO_PORTD | GPIO_PF | 8)
61#define PD9_PF_ATA_DATA7 (GPIO_PORTD | GPIO_PF | 9)
62#define PD10_PF_ATA_DATA8 (GPIO_PORTD | GPIO_PF | 10)
63#define PD11_PF_ATA_DATA9 (GPIO_PORTD | GPIO_PF | 11)
64#define PD12_PF_ATA_DATA10 (GPIO_PORTD | GPIO_PF | 12)
65#define PD13_PF_ATA_DATA11 (GPIO_PORTD | GPIO_PF | 13)
66#define PD14_PF_ATA_DATA12 (GPIO_PORTD | GPIO_PF | 14)
67#define PD15_PF_ATA_DATA13 (GPIO_PORTD | GPIO_PF | 15)
68#define PD16_PF_ATA_DATA14 (GPIO_PORTD | GPIO_PF | 16)
69#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0)
70#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1)
71#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2)
72#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24)
73#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25)
74#define PF1_PF_NFCLE (GPIO_PORTF | GPIO_PF | 1)
75#define PF3_PF_NFCE (GPIO_PORTF | GPIO_PF | 3)
76#define PF7_PF_PC_POE (GPIO_PORTF | GPIO_PF | 7)
77#define PF8_PF_PC_RW (GPIO_PORTF | GPIO_PF | 8)
78#define PF9_PF_PC_IOIS16 (GPIO_PORTF | GPIO_PF | 9)
79#define PF10_PF_PC_RST (GPIO_PORTF | GPIO_PF | 10)
80#define PF11_PF_PC_BVD2 (GPIO_PORTF | GPIO_PF | 11)
81#define PF12_PF_PC_BVD1 (GPIO_PORTF | GPIO_PF | 12)
82#define PF13_PF_PC_VS2 (GPIO_PORTF | GPIO_PF | 13)
83#define PF14_PF_PC_VS1 (GPIO_PORTF | GPIO_PF | 14)
84#define PF16_PF_PC_PWRON (GPIO_PORTF | GPIO_PF | 16)
85#define PF17_PF_PC_READY (GPIO_PORTF | GPIO_PF | 17)
86#define PF18_PF_PC_WAIT (GPIO_PORTF | GPIO_PF | 18)
87#define PF19_PF_PC_CD2 (GPIO_PORTF | GPIO_PF | 19)
88#define PF20_PF_PC_CD1 (GPIO_PORTF | GPIO_PF | 20)
89#define PF23_PF_ATA_DATA15 (GPIO_PORTF | GPIO_PF | 23)
90
91/* Alternate GPIO pin functions */
92
93#define PB4_AF_MSHC_DATA0 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 4)
94#define PB5_AF_MSHC_DATA1 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 5)
95#define PB6_AF_MSHC_DATA2 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 6)
96#define PB7_AF_MSHC_DATA4 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 7)
97#define PB8_AF_MSHC_BS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 8)
98#define PB9_AF_MSHC_SCLK (GPIO_PORTB | GPIO_AF | GPIO_OUT | 9)
99#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 10)
100#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 11)
101#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 12)
102#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 13)
103#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 18)
104#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 19)
105#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 20)
106#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 21)
107#define PC8_AF_FEC_MDIO (GPIO_PORTC | GPIO_AF | GPIO_IN | 8)
108#define PC24_AF_GPT5_TOUT (GPIO_PORTC | GPIO_AF | 24)
109#define PC26_AF_GPT4_TOUT (GPIO_PORTC | GPIO_AF | 26)
110#define PD1_AF_ETMTRACE_PKT15 (GPIO_PORTD | GPIO_AF | 1)
111#define PD6_AF_ETMTRACE_PKT14 (GPIO_PORTD | GPIO_AF | 6)
112#define PD7_AF_ETMTRACE_PKT13 (GPIO_PORTD | GPIO_AF | 7)
113#define PD9_AF_ETMTRACE_PKT12 (GPIO_PORTD | GPIO_AF | 9)
114#define PD2_AF_SD3_D0 (GPIO_PORTD | GPIO_AF | 2)
115#define PD3_AF_SD3_D1 (GPIO_PORTD | GPIO_AF | 3)
116#define PD4_AF_SD3_D2 (GPIO_PORTD | GPIO_AF | 4)
117#define PD5_AF_SD3_D3 (GPIO_PORTD | GPIO_AF | 5)
118#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_AF | GPIO_IN | 8)
119#define PD10_AF_ETMTRACE_PKT11 (GPIO_PORTD | GPIO_AF | 10)
120#define PD11_AF_ETMTRACE_PKT10 (GPIO_PORTD | GPIO_AF | 11)
121#define PD12_AF_ETMTRACE_PKT9 (GPIO_PORTD | GPIO_AF | 12)
122#define PD13_AF_ETMTRACE_PKT8 (GPIO_PORTD | GPIO_AF | 13)
123#define PD14_AF_ETMTRACE_PKT7 (GPIO_PORTD | GPIO_AF | 14)
124#define PD15_AF_ETMTRACE_PKT6 (GPIO_PORTD | GPIO_AF | 15)
125#define PD16_AF_ETMTRACE_PKT5 (GPIO_PORTD | GPIO_AF | 16)
126#define PF1_AF_ETMTRACE_PKT0 (GPIO_PORTF | GPIO_AF | 1)
127#define PF3_AF_ETMTRACE_PKT2 (GPIO_PORTF | GPIO_AF | 3)
128#define PF5_AF_ETMPIPESTAT11 (GPIO_PORTF | GPIO_AF | 5)
129#define PF7_AF_ATA_BUFFER_EN (GPIO_PORTF | GPIO_AF | 7)
130#define PF8_AF_ATA_IORDY (GPIO_PORTF | GPIO_AF | 8)
131#define PF9_AF_ATA_INTRQ (GPIO_PORTF | GPIO_AF | 9)
132#define PF10_AF_ATA_RESET (GPIO_PORTF | GPIO_AF | 10)
133#define PF11_AF_ATA_DMACK (GPIO_PORTF | GPIO_AF | 11)
134#define PF12_AF_ATA_DMAREQ (GPIO_PORTF | GPIO_AF | 12)
135#define PF13_AF_ATA_DA0 (GPIO_PORTF | GPIO_AF | 13)
136#define PF14_AF_ATA_DA1 (GPIO_PORTF | GPIO_AF | 14)
137#define PF15_AF_ETMTRACE_SYNC (GPIO_PORTF | GPIO_AF | 15)
138#define PF16_AF_ATA_DA2 (GPIO_PORTF | GPIO_AF | 16)
139#define PF17_AF_ATA_CS0 (GPIO_PORTF | GPIO_AF | 17)
140#define PF18_AF_ATA_CS1 (GPIO_PORTF | GPIO_AF | 18)
141#define PF19_AF_ATA_DIOW (GPIO_PORTF | GPIO_AF | 19)
142#define PF20_AF_ATA_DIOR (GPIO_PORTF | GPIO_AF | 20)
143#define PF22_AF_ETMTRACE_CLK (GPIO_PORTF | GPIO_AF | 22)
144#define PF23_AF_ETMTRACE_PKT4 (GPIO_PORTF | GPIO_AF | 23)
145
146/* AIN GPIO pin functions */
147
148#define PC14_AIN_SSI1_MCLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14)
149#define PC15_AIN_GPT6_TOUT (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15)
150#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0)
151#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1)
152#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2)
153#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3)
154#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9)
155#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16)
156#define PD27_AIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27)
157#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23)
158
159/* BIN GPIO pin functions */
160
161#define PC14_BIN_SSI2_MCLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14)
162
163/* CIN GPIO pin functions */
164
165#define PD2_CIN_SLCDC1_DAT0 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2)
166#define PD3_CIN_SLCDC1_DAT1 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3)
167#define PD4_CIN_SLCDC1_DAT2 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4)
168#define PD5_CIN_SLCDC1_DAT3 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5)
169#define PD6_CIN_SLCDC1_DAT4 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6)
170#define PD7_CIN_SLCDC1_DAT5 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7)
171#define PD8_CIN_SLCDC1_DAT6 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8)
172#define PD9_CIN_SLCDC1_DAT7 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9)
173#define PD10_CIN_SLCDC1_DAT8 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10)
174#define PD11_CIN_SLCDC1_DAT9 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11)
175#define PD12_CIN_SLCDC1_DAT10 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12)
176#define PD13_CIN_SLCDC1_DAT11 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13)
177#define PD14_CIN_SLCDC1_DAT12 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14)
178#define PD15_CIN_SLCDC1_DAT13 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15)
179#define PD16_CIN_SLCDC1_DAT14 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16)
180#define PD23_CIN_SLCDC1_DAT15 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23)
181#define PF27_CIN_EXT_DMA_GRANT (GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27)
182/* LCDC_TESTx on PBxx omitted, because it's not clear what they do */
183
184/* AOUT GPIO pin functions */
185
186#define PC14_AOUT_GPT6_TIN (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14)
187#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4)
188#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5)
189#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6)
190#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7)
191#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10)
192#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11)
193#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12)
194#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13)
195#define PD14_AOUT_FEC_RX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14)
196#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15)
197
198#define PC17_BOUT_PC_IOIS16 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17)
199#define PC18_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18)
200#define PC19_BOUT_PC_BVD1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19)
201#define PC28_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28)
202#define PC29_BOUT_PC_VS1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29)
203#define PC30_BOUT_PC_READY (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30)
204#define PC31_BOUT_PC_WAIT (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31)
205
206
207#endif /* _MXC_GPIO_MX1_MX2_H */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h
new file mode 100644
index 000000000000..fb5ae638e79f
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h
@@ -0,0 +1,237 @@
1/*
2* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
4*
5* This program is free software; you can redistribute it and/or
6* modify it under the terms of the GNU General Public License
7* as published by the Free Software Foundation; either version 2
8* of the License, or (at your option) any later version.
9* This program is distributed in the hope that it will be useful,
10* but WITHOUT ANY WARRANTY; without even the implied warranty of
11* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12* GNU General Public License for more details.
13*
14* You should have received a copy of the GNU General Public License
15* along with this program; if not, write to the Free Software
16* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17* MA 02110-1301, USA.
18*/
19
20#ifndef _MXC_IOMUX_MX2x_H
21#define _MXC_IOMUX_MX2x_H
22
23#ifndef GPIO_PORTA
24#error Please include mach/iomux.h
25#endif
26
27
28/* Primary GPIO pin functions */
29
30#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5)
31#define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6)
32#define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7)
33#define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8)
34#define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9)
35#define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10)
36#define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11)
37#define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12)
38#define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13)
39#define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14)
40#define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
41#define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
42#define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17)
43#define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18)
44#define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19)
45#define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20)
46#define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21)
47#define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22)
48#define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23)
49#define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24)
50#define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25)
51#define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26)
52#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27)
53#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28)
54#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29)
55#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30)
56#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31)
57#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4)
58#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5)
59#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6)
60#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7)
61#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8)
62#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9)
63#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 10)
64#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 11)
65#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 12)
66#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 13)
67#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 14)
68#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 15)
69#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 16)
70#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 17)
71#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 18)
72#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 19)
73#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 20)
74#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 21)
75#define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23)
76#define PB24_PF_USB_OC (GPIO_PORTB | GPIO_PF | 24)
77#define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26)
78#define PB27_PF_USBH1_OE (GPIO_PORTB | GPIO_PF | 27)
79#define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28)
80#define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29)
81#define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30)
82#define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31)
83#define PC14_PF_TOUT (GPIO_PORTC | GPIO_PF | 14)
84#define PC15_PF_TIN (GPIO_PORTC | GPIO_PF | 15)
85#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 20)
86#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 21)
87#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 22)
88#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 23)
89#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 24)
90#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 25)
91#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 26)
92#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 27)
93#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 28)
94#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 29)
95#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 30)
96#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31)
97#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
98#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
99#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | 19)
100#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | 20)
101#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | 21)
102#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | 22)
103#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | 23)
104#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | 24)
105#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
106#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
107#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
108#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
109#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
110#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 30)
111#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 31)
112#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 3)
113#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 4)
114#define PE5_PF_PWMO (GPIO_PORTE | GPIO_PF | 5)
115#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 6)
116#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 7)
117#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 8)
118#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 9)
119#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 10)
120#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 11)
121#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 12)
122#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 13)
123#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 14)
124#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 15)
125#define PE16_PF_RTCK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 16)
126#define PE17_PF_RESET_OUT (GPIO_PORTE | GPIO_PF | 17)
127#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18)
128#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19)
129#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20)
130#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21)
131#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22)
132#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23)
133#define PF0_PF_NRFB (GPIO_PORTF | GPIO_PF | 0)
134#define PF2_PF_NFWP (GPIO_PORTF | GPIO_PF | 2)
135#define PF4_PF_NFALE (GPIO_PORTF | GPIO_PF | 4)
136#define PF5_PF_NFRE (GPIO_PORTF | GPIO_PF | 5)
137#define PF6_PF_NFWE (GPIO_PORTF | GPIO_PF | 6)
138#define PF15_PF_CLKO (GPIO_PORTF | GPIO_PF | 15)
139#define PF21_PF_CS4 (GPIO_PORTF | GPIO_PF | 21)
140#define PF22_PF_CS5 (GPIO_PORTF | GPIO_PF | 22)
141
142/* Alternate GPIO pin functions */
143
144#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 26)
145#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 28)
146#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 29)
147#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 31)
148#define PC28_AF_SLCDC2_D0 (GPIO_PORTC | GPIO_AF | 28)
149#define PC29_AF_SLCDC2_RS (GPIO_PORTC | GPIO_AF | 29)
150#define PC30_AF_SLCDC2_CS (GPIO_PORTC | GPIO_AF | 30)
151#define PC31_AF_SLCDC2_CLK (GPIO_PORTC | GPIO_AF | 31)
152#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19)
153#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20)
154#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21)
155#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22)
156#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23)
157#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24)
158#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26)
159#define PE0_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 0)
160#define PE1_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 1)
161#define PE2_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 2)
162#define PE3_AF_KP_COL7 (GPIO_PORTE | GPIO_AF | 3)
163#define PE4_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 4)
164#define PE6_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 6)
165#define PE7_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 7)
166#define PE16_AF_OWIRE (GPIO_PORTE | GPIO_AF | 16)
167#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_AF | GPIO_IN | 18)
168#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_AF | GPIO_OUT | 21)
169#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_AF | GPIO_OUT | 22)
170#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_AF | GPIO_OUT | 23)
171
172/* AIN GPIO pin functions */
173
174#define PA6_AIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6)
175#define PA7_AIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7)
176#define PA8_AIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8)
177#define PA0_AIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
178#define PA11_AIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11)
179#define PA13_AIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13)
180#define PA15_AIN_SLCDC1_DAT9 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15)
181#define PA17_AIN_SLCDC1_DAT11 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
182#define PA19_AIN_SLCDC1_DAT13 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19)
183#define PA21_AIN_SLCDC1_DAT15 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21)
184#define PA22_AIN_EXT_DMAGRANT (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22)
185#define PA24_AIN_SLCDC1_D0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24)
186#define PA25_AIN_SLCDC1_RS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25)
187#define PA26_AIN_SLCDC1_CS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26)
188#define PA27_AIN_SLCDC1_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27)
189#define PB6_AIN_SLCDC1_D0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6)
190#define PB7_AIN_SLCDC1_RS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7)
191#define PB8_AIN_SLCDC1_CS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8)
192#define PB9_AIN_SLCDC1_CLK (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9)
193#define PB25_AIN_SLCDC1_DAT0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25)
194#define PB26_AIN_SLCDC1_DAT1 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26)
195#define PB27_AIN_SLCDC1_DAT2 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27)
196#define PB28_AIN_SLCDC1_DAT3 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28)
197#define PB29_AIN_SLCDC1_DAT4 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29)
198#define PB30_AIN_SLCDC1_DAT5 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30)
199#define PB31_AIN_SLCDC1_DAT6 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31)
200#define PC5_AIN_SLCDC1_DAT7 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5)
201#define PC6_AIN_SLCDC1_DAT8 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6)
202#define PC7_AIN_SLCDC1_DAT9 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7)
203#define PC8_AIN_SLCDC1_DAT10 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8)
204#define PC9_AIN_SLCDC1_DAT11 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9)
205#define PC10_AIN_SLCDC1_DAT12 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10)
206#define PC11_AIN_SLCDC1_DAT13 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11)
207#define PC12_AIN_SLCDC1_DAT14 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12)
208#define PC13_AIN_SLCDC1_DAT15 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13)
209#define PE5_AIN_PC_SPKOUT (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5)
210
211/* BIN GPIO pin functions */
212
213#define PE5_BIN_TOUT2 (GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5)
214
215/* CIN GPIO pin functions */
216
217#define PA14_CIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14)
218#define PA15_CIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15)
219#define PA16_CIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16)
220#define PA17_CIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17)
221#define PA18_CIN_SLCDC1_DAT4 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18)
222#define PA19_CIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19)
223#define PA20_CIN_SLCDC1_DAT6 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20)
224#define PA21_CIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21)
225#define PB30_CIN_UART4_CTS (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30)
226#define PE5_CIN_TOUT3 (GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5)
227
228/* AOUT GPIO pin functions */
229
230#define PB29_AOUT_UART4_RXD (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29)
231#define PB31_AOUT_UART4_RTS (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31)
232#define PC8_AOUT_USBOTG_TXR_INT (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 8)
233#define PC15_AOUT_WKGD (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15)
234#define PF21_AOUT_DTACK (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21)
235
236
237#endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index c9198c0aea18..ab838cfe94f9 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -92,7 +92,7 @@ enum iomux_gp_func {
92 MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, 92 MUX_EXTDMAREQ2_MBX_SEL = 1 << 15,
93 MUX_TAMPER_DETECT_EN = 1 << 16, 93 MUX_TAMPER_DETECT_EN = 1 << 16,
94 MUX_PGP_USB_4WIRE = 1 << 17, 94 MUX_PGP_USB_4WIRE = 1 << 17,
95 MUX_PGB_USB_COMMON = 1 << 18, 95 MUX_PGP_USB_COMMON = 1 << 18,
96 MUX_SDHC_MEMSTICK1 = 1 << 19, 96 MUX_SDHC_MEMSTICK1 = 1 << 19,
97 MUX_SDHC_MEMSTICK2 = 1 << 20, 97 MUX_SDHC_MEMSTICK2 = 1 << 20,
98 MUX_PGP_SPLL_BYP = 1 << 21, 98 MUX_PGP_SPLL_BYP = 1 << 21,
@@ -109,21 +109,44 @@ enum iomux_gp_func {
109}; 109};
110 110
111/* 111/*
112 * This function enables/disables the general purpose function for a particular 112 * setups a single pin:
113 * signal. 113 * - reserves the pin so that it is not claimed by another driver
114 * - setups the iomux according to the configuration
115 * - if the pin is configured as a GPIO, we claim it throug kernel gpiolib
116 */
117int mxc_iomux_setup_pin(const unsigned int pin, const char *label);
118/*
119 * setups mutliple pins
120 * convenient way to call the above function with tables
114 */ 121 */
115void iomux_config_gpr(enum iomux_gp_func , bool); 122int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
123 const char *label);
116 124
117/* 125/*
118 * set the mode for a IOMUX pin. 126 * releases a single pin:
127 * - make it available for a future use by another driver
128 * - frees the GPIO if the pin was configured as GPIO
129 * - DOES NOT reconfigure the IOMUX in its reset state
119 */ 130 */
120int mxc_iomux_mode(unsigned int); 131void mxc_iomux_release_pin(const unsigned int pin);
132/*
133 * releases multiple pins
134 * convenvient way to call the above function with tables
135 */
136void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count);
121 137
122/* 138/*
123 * This function enables/disables the general purpose function for a particular 139 * This function enables/disables the general purpose function for a particular
124 * signal. 140 * signal.
125 */ 141 */
126void mxc_iomux_set_gpr(enum iomux_gp_func, bool); 142void mxc_iomux_set_gpr(enum iomux_gp_func, bool en);
143
144/*
145 * This function only configures the iomux hardware.
146 * It is called by the setup functions and should not be called directly anymore.
147 * It is here visible for backward compatibility
148 */
149int mxc_iomux_mode(unsigned int pin_mode);
127 150
128#define IOMUX_PADNUM_MASK 0x1ff 151#define IOMUX_PADNUM_MASK 0x1ff
129#define IOMUX_GPIONUM_SHIFT 9 152#define IOMUX_GPIONUM_SHIFT 9
@@ -144,6 +167,11 @@ void mxc_iomux_set_gpr(enum iomux_gp_func, bool);
144 MXC_GPIO_IRQ_START) 167 MXC_GPIO_IRQ_START)
145 168
146/* 169/*
170 * The number of gpio devices among the pads
171 */
172#define GPIO_PORT_MAX 3
173
174/*
147 * This enumeration is constructed based on the Section 175 * This enumeration is constructed based on the Section
148 * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated 176 * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
149 * value is constructed based on the rules described above. 177 * value is constructed based on the rules described above.
@@ -480,6 +508,9 @@ enum iomux_pins {
480 MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327), 508 MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327),
481}; 509};
482 510
511#define PIN_MAX 327
512#define NB_PORTS 12 /* NB_PINS/32, we chose 32 pins per "PORT" */
513
483/* 514/*
484 * Convenience values for use with mxc_iomux_mode() 515 * Convenience values for use with mxc_iomux_mode()
485 * 516 *
@@ -507,7 +538,9 @@ enum iomux_pins {
507#define MX31_PIN_CSPI1_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC) 538#define MX31_PIN_CSPI1_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC)
508#define MX31_PIN_CSPI1_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC) 539#define MX31_PIN_CSPI1_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC)
509#define MX31_PIN_CSPI2_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC) 540#define MX31_PIN_CSPI2_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC)
541#define MX31_PIN_CSPI2_MOSI__SCL IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1)
510#define MX31_PIN_CSPI2_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC) 542#define MX31_PIN_CSPI2_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC)
543#define MX31_PIN_CSPI2_MISO__SDA IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1)
511#define MX31_PIN_CSPI2_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC) 544#define MX31_PIN_CSPI2_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC)
512#define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC) 545#define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC)
513#define MX31_PIN_CSPI2_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC) 546#define MX31_PIN_CSPI2_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC)
@@ -525,6 +558,33 @@ enum iomux_pins {
525#define MX31_PIN_SD1_DATA0__SD1_DATA0 IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC) 558#define MX31_PIN_SD1_DATA0__SD1_DATA0 IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC)
526#define MX31_PIN_SD1_CLK__SD1_CLK IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC) 559#define MX31_PIN_SD1_CLK__SD1_CLK IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC)
527#define MX31_PIN_SD1_CMD__SD1_CMD IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC) 560#define MX31_PIN_SD1_CMD__SD1_CMD IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC)
561#define MX31_PIN_LD0__LD0 IOMUX_MODE(MX31_PIN_LD0, IOMUX_CONFIG_FUNC)
562#define MX31_PIN_LD1__LD1 IOMUX_MODE(MX31_PIN_LD1, IOMUX_CONFIG_FUNC)
563#define MX31_PIN_LD2__LD2 IOMUX_MODE(MX31_PIN_LD2, IOMUX_CONFIG_FUNC)
564#define MX31_PIN_LD3__LD3 IOMUX_MODE(MX31_PIN_LD3, IOMUX_CONFIG_FUNC)
565#define MX31_PIN_LD4__LD4 IOMUX_MODE(MX31_PIN_LD4, IOMUX_CONFIG_FUNC)
566#define MX31_PIN_LD5__LD5 IOMUX_MODE(MX31_PIN_LD5, IOMUX_CONFIG_FUNC)
567#define MX31_PIN_LD6__LD6 IOMUX_MODE(MX31_PIN_LD6, IOMUX_CONFIG_FUNC)
568#define MX31_PIN_LD7__LD7 IOMUX_MODE(MX31_PIN_LD7, IOMUX_CONFIG_FUNC)
569#define MX31_PIN_LD8__LD8 IOMUX_MODE(MX31_PIN_LD8, IOMUX_CONFIG_FUNC)
570#define MX31_PIN_LD9__LD9 IOMUX_MODE(MX31_PIN_LD9, IOMUX_CONFIG_FUNC)
571#define MX31_PIN_LD10__LD10 IOMUX_MODE(MX31_PIN_LD10, IOMUX_CONFIG_FUNC)
572#define MX31_PIN_LD11__LD11 IOMUX_MODE(MX31_PIN_LD11, IOMUX_CONFIG_FUNC)
573#define MX31_PIN_LD12__LD12 IOMUX_MODE(MX31_PIN_LD12, IOMUX_CONFIG_FUNC)
574#define MX31_PIN_LD13__LD13 IOMUX_MODE(MX31_PIN_LD13, IOMUX_CONFIG_FUNC)
575#define MX31_PIN_LD14__LD14 IOMUX_MODE(MX31_PIN_LD14, IOMUX_CONFIG_FUNC)
576#define MX31_PIN_LD15__LD15 IOMUX_MODE(MX31_PIN_LD15, IOMUX_CONFIG_FUNC)
577#define MX31_PIN_LD16__LD16 IOMUX_MODE(MX31_PIN_LD16, IOMUX_CONFIG_FUNC)
578#define MX31_PIN_LD17__LD17 IOMUX_MODE(MX31_PIN_LD17, IOMUX_CONFIG_FUNC)
579#define MX31_PIN_VSYNC3__VSYNC3 IOMUX_MODE(MX31_PIN_VSYNC3, IOMUX_CONFIG_FUNC)
580#define MX31_PIN_HSYNC__HSYNC IOMUX_MODE(MX31_PIN_HSYNC, IOMUX_CONFIG_FUNC)
581#define MX31_PIN_FPSHIFT__FPSHIFT IOMUX_MODE(MX31_PIN_FPSHIFT, IOMUX_CONFIG_FUNC)
582#define MX31_PIN_DRDY0__DRDY0 IOMUX_MODE(MX31_PIN_DRDY0, IOMUX_CONFIG_FUNC)
583#define MX31_PIN_D3_REV__D3_REV IOMUX_MODE(MX31_PIN_D3_REV, IOMUX_CONFIG_FUNC)
584#define MX31_PIN_CONTRAST__CONTRAST IOMUX_MODE(MX31_PIN_CONTRAST, IOMUX_CONFIG_FUNC)
585#define MX31_PIN_D3_SPL__D3_SPL IOMUX_MODE(MX31_PIN_D3_SPL, IOMUX_CONFIG_FUNC)
586#define MX31_PIN_D3_CLS__D3_CLS IOMUX_MODE(MX31_PIN_D3_CLS, IOMUX_CONFIG_FUNC)
587#define MX31_PIN_LCS0__GPI03_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO)
528 588
529/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 589/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0
530 * cspi1_ss1*/ 590 * cspi1_ss1*/
diff --git a/arch/arm/plat-mxc/include/mach/iomux.h b/arch/arm/plat-mxc/include/mach/iomux.h
new file mode 100644
index 000000000000..171f8adc1109
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux.h
@@ -0,0 +1,127 @@
1/*
2* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
4*
5* This program is free software; you can redistribute it and/or
6* modify it under the terms of the GNU General Public License
7* as published by the Free Software Foundation; either version 2
8* of the License, or (at your option) any later version.
9* This program is distributed in the hope that it will be useful,
10* but WITHOUT ANY WARRANTY; without even the implied warranty of
11* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12* GNU General Public License for more details.
13*
14* You should have received a copy of the GNU General Public License
15* along with this program; if not, write to the Free Software
16* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17* MA 02110-1301, USA.
18*/
19
20#ifndef _MXC_IOMUX_H
21#define _MXC_IOMUX_H
22
23/*
24* GPIO Module and I/O Multiplexer
25* x = 0..3 for reg_A, reg_B, reg_C, reg_D
26*/
27#define VA_GPIO_BASE IO_ADDRESS(GPIO_BASE_ADDR)
28#define MXC_DDIR(x) (0x00 + ((x) << 8))
29#define MXC_OCR1(x) (0x04 + ((x) << 8))
30#define MXC_OCR2(x) (0x08 + ((x) << 8))
31#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
32#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
33#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
34#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
35#define MXC_DR(x) (0x1c + ((x) << 8))
36#define MXC_GIUS(x) (0x20 + ((x) << 8))
37#define MXC_SSR(x) (0x24 + ((x) << 8))
38#define MXC_ICR1(x) (0x28 + ((x) << 8))
39#define MXC_ICR2(x) (0x2c + ((x) << 8))
40#define MXC_IMR(x) (0x30 + ((x) << 8))
41#define MXC_ISR(x) (0x34 + ((x) << 8))
42#define MXC_GPR(x) (0x38 + ((x) << 8))
43#define MXC_SWR(x) (0x3c + ((x) << 8))
44#define MXC_PUEN(x) (0x40 + ((x) << 8))
45
46#ifdef CONFIG_ARCH_MX1
47# define GPIO_PORT_MAX 3
48#endif
49#ifdef CONFIG_ARCH_MX2
50# define GPIO_PORT_MAX 5
51#endif
52
53#ifndef GPIO_PORT_MAX
54# error "GPIO config port count unknown!"
55#endif
56
57#define GPIO_PIN_MASK 0x1f
58
59#define GPIO_PORT_SHIFT 5
60#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
61
62#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
63#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
64#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
65#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
66#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
67#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
68
69#define GPIO_OUT (1 << 8)
70#define GPIO_IN (0 << 8)
71#define GPIO_PUEN (1 << 9)
72
73#define GPIO_PF (1 << 10)
74#define GPIO_AF (1 << 11)
75
76#define GPIO_OCR_SHIFT 12
77#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
78#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
79#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
80#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
81#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
82
83#define GPIO_AOUT_SHIFT 14
84#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
85#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
86#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
87#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
88#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
89
90#define GPIO_BOUT_SHIFT 16
91#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
92#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
93#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
94#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
95#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
96
97
98#ifdef CONFIG_ARCH_MX1
99#include <mach/iomux-mx1.h>
100#endif
101#ifdef CONFIG_ARCH_MX2
102#include <mach/iomux-mx2x.h>
103#ifdef CONFIG_MACH_MX21
104#include <mach/iomux-mx21.h>
105#endif
106#ifdef CONFIG_MACH_MX27
107#include <mach/iomux-mx27.h>
108#endif
109#endif
110
111
112/* decode irq number to use with IMR(x), ISR(x) and friends */
113#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5)
114
115#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x)
116#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
117#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
118#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
119#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x)
120
121
122extern void mxc_gpio_mode(int gpio_mode);
123extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
124 const char *label);
125extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
126
127#endif
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 0b808399097f..e0783e619580 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -14,7 +14,12 @@
14#if defined CONFIG_ARCH_MX1 14#if defined CONFIG_ARCH_MX1
15#define PHYS_OFFSET UL(0x08000000) 15#define PHYS_OFFSET UL(0x08000000)
16#elif defined CONFIG_ARCH_MX2 16#elif defined CONFIG_ARCH_MX2
17#ifdef CONFIG_MACH_MX21
18#define PHYS_OFFSET UL(0xC0000000)
19#endif
20#ifdef CONFIG_MACH_MX27
17#define PHYS_OFFSET UL(0xA0000000) 21#define PHYS_OFFSET UL(0xA0000000)
22#endif
18#elif defined CONFIG_ARCH_MX3 23#elif defined CONFIG_ARCH_MX3
19#define PHYS_OFFSET UL(0x80000000) 24#define PHYS_OFFSET UL(0x80000000)
20#endif 25#endif
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
new file mode 100644
index 000000000000..e8c4cf56c24e
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -0,0 +1,78 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 * Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de
5 *
6 * This contains i.MX21-specific hardware definitions. For those
7 * hardware pieces that are common between i.MX21 and i.MX27, have a
8 * look at mx2x.h.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
22 * MA 02110-1301, USA.
23 */
24
25#ifndef __ASM_ARCH_MXC_MX21_H__
26#define __ASM_ARCH_MXC_MX21_H__
27
28#ifndef __ASM_ARCH_MXC_HARDWARE_H__
29#error "Do not include directly."
30#endif
31
32
33/* Memory regions and CS */
34#define SDRAM_BASE_ADDR 0xC0000000
35#define CSD1_BASE_ADDR 0xC4000000
36
37#define CS0_BASE_ADDR 0xC8000000
38#define CS1_BASE_ADDR 0xCC000000
39#define CS2_BASE_ADDR 0xD0000000
40#define CS3_BASE_ADDR 0xD1000000
41#define CS4_BASE_ADDR 0xD2000000
42#define CS5_BASE_ADDR 0xDD000000
43#define PCMCIA_MEM_BASE_ADDR 0xD4000000
44
45/* NAND, SDRAM, WEIM etc controllers */
46#define X_MEMC_BASE_ADDR 0xDF000000
47#define X_MEMC_BASE_ADDR_VIRT 0xF4200000
48#define X_MEMC_SIZE SZ_256K
49
50#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000)
51#define EIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
52#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
53#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
54
55#define IRAM_BASE_ADDR 0xFFFFE800 /* internal ram */
56
57/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
58#define ARCH_NR_GPIOS (6*32 + 16)
59
60/* fixed interrupt numbers */
61#define MXC_INT_USBCTRL 58
62#define MXC_INT_USBCTRL 58
63#define MXC_INT_USBMNP 57
64#define MXC_INT_USBFUNC 56
65#define MXC_INT_USBHOST 55
66#define MXC_INT_USBDMA 54
67#define MXC_INT_USBWKUP 53
68#define MXC_INT_EMMADEC 50
69#define MXC_INT_EMMAENC 49
70#define MXC_INT_BMI 30
71#define MXC_INT_FIRI 9
72
73/* fixed DMA request numbers */
74#define DMA_REQ_BMI_RX 29
75#define DMA_REQ_BMI_TX 28
76#define DMA_REQ_FIRI_RX 4
77
78#endif /* __ASM_ARCH_MXC_MX21_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index 0313be720552..6e93f2c0b7bb 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -2,6 +2,10 @@
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 * 4 *
5 * This contains i.MX27-specific hardware definitions. For those
6 * hardware pieces that are common between i.MX21 and i.MX27, have a
7 * look at mx2x.h.
8 *
5 * This program is free software; you can redistribute it and/or 9 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License 10 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2 11 * as published by the Free Software Foundation; either version 2
@@ -27,35 +31,6 @@
27/* IRAM */ 31/* IRAM */
28#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */ 32#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */
29 33
30/* Register offests */
31#define AIPI_BASE_ADDR 0x10000000
32#define AIPI_BASE_ADDR_VIRT 0xF4000000
33#define AIPI_SIZE SZ_1M
34
35#define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000)
36#define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000)
37#define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000)
38#define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000)
39#define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000)
40#define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000)
41#define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000)
42#define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000)
43#define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000)
44#define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000)
45#define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000)
46#define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000)
47#define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000)
48#define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000)
49#define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000)
50#define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000)
51#define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000)
52#define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000)
53#define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000)
54#define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000)
55#define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000)
56#define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000)
57
58#define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000)
59#define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000) 34#define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000)
60#define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000) 35#define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000)
61#define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000) 36#define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000)
@@ -64,55 +39,24 @@
64#define I2C2_BASE_ADDR (AIPI_BASE_ADDR + 0x1D000) 39#define I2C2_BASE_ADDR (AIPI_BASE_ADDR + 0x1D000)
65#define SDHC3_BASE_ADDR (AIPI_BASE_ADDR + 0x1E000) 40#define SDHC3_BASE_ADDR (AIPI_BASE_ADDR + 0x1E000)
66#define GPT6_BASE_ADDR (AIPI_BASE_ADDR + 0x1F000) 41#define GPT6_BASE_ADDR (AIPI_BASE_ADDR + 0x1F000)
67
68#define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000)
69#define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000)
70#define VPU_BASE_ADDR (AIPI_BASE_ADDR + 0x23000) 42#define VPU_BASE_ADDR (AIPI_BASE_ADDR + 0x23000)
71#define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000)
72/* for mx27*/
73#define OTG_BASE_ADDR USBOTG_BASE_ADDR 43#define OTG_BASE_ADDR USBOTG_BASE_ADDR
74#define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000) 44#define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000)
75#define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000)
76#define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400)
77#define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000)
78#define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800)
79#define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000) 45#define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000)
80
81#define RTIC_BASE_ADDR (AIPI_BASE_ADDR + 0x2A000) 46#define RTIC_BASE_ADDR (AIPI_BASE_ADDR + 0x2A000)
82#define FEC_BASE_ADDR (AIPI_BASE_ADDR + 0x2B000) 47#define FEC_BASE_ADDR (AIPI_BASE_ADDR + 0x2B000)
83#define SCC_BASE_ADDR (AIPI_BASE_ADDR + 0x2C000) 48#define SCC_BASE_ADDR (AIPI_BASE_ADDR + 0x2C000)
84#define ETB_BASE_ADDR (AIPI_BASE_ADDR + 0x3B000) 49#define ETB_BASE_ADDR (AIPI_BASE_ADDR + 0x3B000)
85#define ETB_RAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3C000) 50#define ETB_RAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3C000)
86 51
87#define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000) 52/* ROM patch */
88#define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000)
89
90/* ROMP and AVIC */
91#define ROMP_BASE_ADDR 0x10041000 53#define ROMP_BASE_ADDR 0x10041000
92 54
93#define AVIC_BASE_ADDR 0x10040000
94
95#define SAHB1_BASE_ADDR 0x80000000
96#define SAHB1_BASE_ADDR_VIRT 0xF4100000
97#define SAHB1_SIZE SZ_1M
98
99#define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000)
100#define ATA_BASE_ADDR (SAHB1_BASE_ADDR + 0x1000) 55#define ATA_BASE_ADDR (SAHB1_BASE_ADDR + 0x1000)
101 56
102/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
103#define X_MEMC_BASE_ADDR 0xD8000000
104#define X_MEMC_BASE_ADDR_VIRT 0xF4200000
105#define X_MEMC_SIZE SZ_1M
106
107#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR)
108#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
109#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
110#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
111#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
112
113/* Memory regions and CS */ 57/* Memory regions and CS */
114#define SDRAM_BASE_ADDR 0xA0000000 58#define SDRAM_BASE_ADDR 0xA0000000
115#define CSD1_BASE_ADDR 0xB0000000 59#define CSD1_BASE_ADDR 0xB0000000
116 60
117#define CS0_BASE_ADDR 0xC0000000 61#define CS0_BASE_ADDR 0xC0000000
118#define CS1_BASE_ADDR 0xC8000000 62#define CS1_BASE_ADDR 0xC8000000
@@ -122,44 +66,20 @@
122#define CS5_BASE_ADDR 0xD6000000 66#define CS5_BASE_ADDR 0xD6000000
123#define PCMCIA_MEM_BASE_ADDR 0xDC000000 67#define PCMCIA_MEM_BASE_ADDR 0xDC000000
124 68
125/* 69/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
126 * This macro defines the physical to virtual address mapping for all the 70#define X_MEMC_BASE_ADDR 0xD8000000
127 * peripheral modules. It is used by passing in the physical address as x 71#define X_MEMC_BASE_ADDR_VIRT 0xF4200000
128 * and returning the virtual address. If the physical address is not mapped, 72#define X_MEMC_SIZE SZ_1M
129 * it returns 0xDEADBEEF
130 */
131#define IO_ADDRESS(x) \
132 (void __iomem *) \
133 (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
134 AIPI_IO_ADDRESS(x) : \
135 ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
136 SAHB1_IO_ADDRESS(x) : \
137 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
138 X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
139
140/* define the address mapping macros: in physical address order */
141#define AIPI_IO_ADDRESS(x) \
142 (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
143
144#define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x)
145
146#define SAHB1_IO_ADDRESS(x) \
147 (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
148
149#define CS4_IO_ADDRESS(x) \
150 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
151
152#define X_MEMC_IO_ADDRESS(x) \
153 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
154 73
155#define PCMCIA_IO_ADDRESS(x) \ 74#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR)
156 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) 75#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
76#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
77#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
78#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
157 79
158/* fixed interrput numbers */ 80/* fixed interrupt numbers */
159#define MXC_INT_CCM 63 81#define MXC_INT_CCM 63
160#define MXC_INT_IIM 62 82#define MXC_INT_IIM 62
161#define MXC_INT_LCDC 61
162#define MXC_INT_SLCDC 60
163#define MXC_INT_SAHARA 59 83#define MXC_INT_SAHARA 59
164#define MXC_INT_SCC_SCM 58 84#define MXC_INT_SCC_SCM 58
165#define MXC_INT_SCC_SMN 57 85#define MXC_INT_SCC_SMN 57
@@ -167,54 +87,12 @@
167#define MXC_INT_USB2 55 87#define MXC_INT_USB2 55
168#define MXC_INT_USB1 54 88#define MXC_INT_USB1 54
169#define MXC_INT_VPU 53 89#define MXC_INT_VPU 53
170#define MXC_INT_EMMAPP 52
171#define MXC_INT_EMMAPRP 51
172#define MXC_INT_FEC 50 90#define MXC_INT_FEC 50
173#define MXC_INT_UART5 49 91#define MXC_INT_UART5 49
174#define MXC_INT_UART6 48 92#define MXC_INT_UART6 48
175#define MXC_INT_DMACH15 47
176#define MXC_INT_DMACH14 46
177#define MXC_INT_DMACH13 45
178#define MXC_INT_DMACH12 44
179#define MXC_INT_DMACH11 43
180#define MXC_INT_DMACH10 42
181#define MXC_INT_DMACH9 41
182#define MXC_INT_DMACH8 40
183#define MXC_INT_DMACH7 39
184#define MXC_INT_DMACH6 38
185#define MXC_INT_DMACH5 37
186#define MXC_INT_DMACH4 36
187#define MXC_INT_DMACH3 35
188#define MXC_INT_DMACH2 34
189#define MXC_INT_DMACH1 33
190#define MXC_INT_DMACH0 32
191#define MXC_INT_CSI 31
192#define MXC_INT_ATA 30 93#define MXC_INT_ATA 30
193#define MXC_INT_NANDFC 29
194#define MXC_INT_PCMCIA 28
195#define MXC_INT_WDOG 27
196#define MXC_INT_GPT1 26
197#define MXC_INT_GPT2 25
198#define MXC_INT_GPT3 24
199#define MXC_INT_GPT INT_GPT1
200#define MXC_INT_PWM 23
201#define MXC_INT_RTC 22
202#define MXC_INT_KPP 21
203#define MXC_INT_UART1 20
204#define MXC_INT_UART2 19
205#define MXC_INT_UART3 18
206#define MXC_INT_UART4 17
207#define MXC_INT_CSPI1 16
208#define MXC_INT_CSPI2 15
209#define MXC_INT_SSI1 14
210#define MXC_INT_SSI2 13
211#define MXC_INT_I2C 12
212#define MXC_INT_SDHC1 11
213#define MXC_INT_SDHC2 10
214#define MXC_INT_SDHC3 9 94#define MXC_INT_SDHC3 9
215#define MXC_INT_GPIO 8
216#define MXC_INT_SDHC 7 95#define MXC_INT_SDHC 7
217#define MXC_INT_CSPI3 6
218#define MXC_INT_RTIC 5 96#define MXC_INT_RTIC 5
219#define MXC_INT_GPT4 4 97#define MXC_INT_GPT4 4
220#define MXC_INT_GPT5 3 98#define MXC_INT_GPT5 3
@@ -228,36 +106,9 @@
228#define DMA_REQ_UART6_TX 34 106#define DMA_REQ_UART6_TX 34
229#define DMA_REQ_UART5_RX 33 107#define DMA_REQ_UART5_RX 33
230#define DMA_REQ_UART5_TX 32 108#define DMA_REQ_UART5_TX 32
231#define DMA_REQ_CSI_RX 31
232#define DMA_REQ_CSI_STAT 30
233#define DMA_REQ_ATA_RCV 29 109#define DMA_REQ_ATA_RCV 29
234#define DMA_REQ_ATA_TX 28 110#define DMA_REQ_ATA_TX 28
235#define DMA_REQ_UART1_TX 27
236#define DMA_REQ_UART1_RX 26
237#define DMA_REQ_UART2_TX 25
238#define DMA_REQ_UART2_RX 24
239#define DMA_REQ_UART3_TX 23
240#define DMA_REQ_UART3_RX 22
241#define DMA_REQ_UART4_TX 21
242#define DMA_REQ_UART4_RX 20
243#define DMA_REQ_CSPI1_TX 19
244#define DMA_REQ_CSPI1_RX 18
245#define DMA_REQ_CSPI2_TX 17
246#define DMA_REQ_CSPI2_RX 16
247#define DMA_REQ_SSI1_TX1 15
248#define DMA_REQ_SSI1_RX1 14
249#define DMA_REQ_SSI1_TX0 13
250#define DMA_REQ_SSI1_RX0 12
251#define DMA_REQ_SSI2_TX1 11
252#define DMA_REQ_SSI2_RX1 10
253#define DMA_REQ_SSI2_TX0 9
254#define DMA_REQ_SSI2_RX0 8
255#define DMA_REQ_SDHC1 7
256#define DMA_REQ_SDHC2 6
257#define DMA_REQ_MSHC 4 111#define DMA_REQ_MSHC 4
258#define DMA_REQ_EXT 3
259#define DMA_REQ_CSPI3_TX 2
260#define DMA_REQ_CSPI3_RX 1
261 112
262/* silicon revisions specific to i.MX27 */ 113/* silicon revisions specific to i.MX27 */
263#define CHIP_REV_1_0 0x00 114#define CHIP_REV_1_0 0x00
@@ -267,25 +118,8 @@
267extern int mx27_revision(void); 118extern int mx27_revision(void);
268#endif 119#endif
269 120
270/* gpio and gpio based interrupt handling */
271#define GPIO_DR 0x1C
272#define GPIO_GDIR 0x00
273#define GPIO_PSR 0x24
274#define GPIO_ICR1 0x28
275#define GPIO_ICR2 0x2C
276#define GPIO_IMR 0x30
277#define GPIO_ISR 0x34
278#define GPIO_INT_LOW_LEV 0x3
279#define GPIO_INT_HIGH_LEV 0x2
280#define GPIO_INT_RISE_EDGE 0x0
281#define GPIO_INT_FALL_EDGE 0x1
282#define GPIO_INT_NONE 0x4
283
284/* Mandatory defines used globally */ 121/* Mandatory defines used globally */
285 122
286/* this is an i.MX27 CPU */
287#define cpu_is_mx27() (1)
288
289/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */ 123/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
290#define ARCH_NR_GPIOS (192 + 16) 124#define ARCH_NR_GPIOS (192 + 16)
291 125
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
new file mode 100644
index 000000000000..fc40d3ab8c5b
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -0,0 +1,200 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This contains hardware definitions that are common between i.MX21 and
6 * i.MX27.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 */
22
23#ifndef __ASM_ARCH_MXC_MX2x_H__
24#define __ASM_ARCH_MXC_MX2x_H__
25
26#ifndef __ASM_ARCH_MXC_HARDWARE_H__
27#error "Do not include directly."
28#endif
29
30/* The following addresses are common between i.MX21 and i.MX27 */
31
32/* Register offests */
33#define AIPI_BASE_ADDR 0x10000000
34#define AIPI_BASE_ADDR_VIRT 0xF4000000
35#define AIPI_SIZE SZ_1M
36
37#define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000)
38#define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000)
39#define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000)
40#define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000)
41#define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000)
42#define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000)
43#define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000)
44#define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000)
45#define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000)
46#define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000)
47#define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000)
48#define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000)
49#define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000)
50#define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000)
51#define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000)
52#define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000)
53#define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000)
54#define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000)
55#define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000)
56#define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000)
57#define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000)
58#define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000)
59#define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000)
60#define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000)
61#define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000)
62#define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000)
63#define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000)
64#define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400)
65#define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000)
66#define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800)
67#define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000)
68#define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000)
69
70#define AVIC_BASE_ADDR 0x10040000
71
72#define SAHB1_BASE_ADDR 0x80000000
73#define SAHB1_BASE_ADDR_VIRT 0xF4100000
74#define SAHB1_SIZE SZ_1M
75
76#define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000)
77
78/*
79 * This macro defines the physical to virtual address mapping for all the
80 * peripheral modules. It is used by passing in the physical address as x
81 * and returning the virtual address. If the physical address is not mapped,
82 * it returns 0xDEADBEEF
83 */
84#define IO_ADDRESS(x) \
85 (void __force __iomem *) \
86 (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
87 AIPI_IO_ADDRESS(x) : \
88 ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
89 SAHB1_IO_ADDRESS(x) : \
90 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
91 X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
92
93/* define the address mapping macros: in physical address order */
94#define AIPI_IO_ADDRESS(x) \
95 (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
96
97#define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x)
98
99#define SAHB1_IO_ADDRESS(x) \
100 (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
101
102#define CS4_IO_ADDRESS(x) \
103 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
104
105#define X_MEMC_IO_ADDRESS(x) \
106 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
107
108#define PCMCIA_IO_ADDRESS(x) \
109 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
110
111/* fixed interrupt numbers */
112#define MXC_INT_LCDC 61
113#define MXC_INT_SLCDC 60
114#define MXC_INT_EMMAPP 52
115#define MXC_INT_EMMAPRP 51
116#define MXC_INT_DMACH15 47
117#define MXC_INT_DMACH14 46
118#define MXC_INT_DMACH13 45
119#define MXC_INT_DMACH12 44
120#define MXC_INT_DMACH11 43
121#define MXC_INT_DMACH10 42
122#define MXC_INT_DMACH9 41
123#define MXC_INT_DMACH8 40
124#define MXC_INT_DMACH7 39
125#define MXC_INT_DMACH6 38
126#define MXC_INT_DMACH5 37
127#define MXC_INT_DMACH4 36
128#define MXC_INT_DMACH3 35
129#define MXC_INT_DMACH2 34
130#define MXC_INT_DMACH1 33
131#define MXC_INT_DMACH0 32
132#define MXC_INT_CSI 31
133#define MXC_INT_NANDFC 29
134#define MXC_INT_PCMCIA 28
135#define MXC_INT_WDOG 27
136#define MXC_INT_GPT1 26
137#define MXC_INT_GPT2 25
138#define MXC_INT_GPT3 24
139#define MXC_INT_GPT INT_GPT1
140#define MXC_INT_PWM 23
141#define MXC_INT_RTC 22
142#define MXC_INT_KPP 21
143#define MXC_INT_UART1 20
144#define MXC_INT_UART2 19
145#define MXC_INT_UART3 18
146#define MXC_INT_UART4 17
147#define MXC_INT_CSPI1 16
148#define MXC_INT_CSPI2 15
149#define MXC_INT_SSI1 14
150#define MXC_INT_SSI2 13
151#define MXC_INT_I2C 12
152#define MXC_INT_SDHC1 11
153#define MXC_INT_SDHC2 10
154#define MXC_INT_GPIO 8
155#define MXC_INT_CSPI3 6
156
157/* gpio and gpio based interrupt handling */
158#define GPIO_DR 0x1C
159#define GPIO_GDIR 0x00
160#define GPIO_PSR 0x24
161#define GPIO_ICR1 0x28
162#define GPIO_ICR2 0x2C
163#define GPIO_IMR 0x30
164#define GPIO_ISR 0x34
165#define GPIO_INT_LOW_LEV 0x3
166#define GPIO_INT_HIGH_LEV 0x2
167#define GPIO_INT_RISE_EDGE 0x0
168#define GPIO_INT_FALL_EDGE 0x1
169#define GPIO_INT_NONE 0x4
170
171/* fixed DMA request numbers */
172#define DMA_REQ_CSI_RX 31
173#define DMA_REQ_CSI_STAT 30
174#define DMA_REQ_UART1_TX 27
175#define DMA_REQ_UART1_RX 26
176#define DMA_REQ_UART2_TX 25
177#define DMA_REQ_UART2_RX 24
178#define DMA_REQ_UART3_TX 23
179#define DMA_REQ_UART3_RX 22
180#define DMA_REQ_UART4_TX 21
181#define DMA_REQ_UART4_RX 20
182#define DMA_REQ_CSPI1_TX 19
183#define DMA_REQ_CSPI1_RX 18
184#define DMA_REQ_CSPI2_TX 17
185#define DMA_REQ_CSPI2_RX 16
186#define DMA_REQ_SSI1_TX1 15
187#define DMA_REQ_SSI1_RX1 14
188#define DMA_REQ_SSI1_TX0 13
189#define DMA_REQ_SSI1_RX0 12
190#define DMA_REQ_SSI2_TX1 11
191#define DMA_REQ_SSI2_RX1 10
192#define DMA_REQ_SSI2_TX0 9
193#define DMA_REQ_SSI2_RX0 8
194#define DMA_REQ_SDHC1 7
195#define DMA_REQ_SDHC2 6
196#define DMA_REQ_EXT 3
197#define DMA_REQ_CSPI3_TX 2
198#define DMA_REQ_CSPI3_RX 1
199
200#endif /* __ASM_ARCH_MXC_MX2x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index de026654b00e..0b06941b6139 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -1,360 +1,45 @@
1/* 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_MX31_H__
12#define __ASM_ARCH_MXC_MX31_H__
13
14#ifndef __ASM_ARCH_MXC_HARDWARE_H__
15#error "Do not include directly."
16#endif
17
18/*
19 * MX31 memory map:
20 *
21 * Virt Phys Size What
22 * ---------------------------------------------------------------------------
23 * F8000000 1FFC0000 16K IRAM
24 * F9000000 30000000 256M L2CC
25 * FC000000 43F00000 1M AIPS 1
26 * FC100000 50000000 1M SPBA
27 * FC200000 53F00000 1M AIPS 2
28 * FC500000 60000000 128M ROMPATCH
29 * FC400000 68000000 128M AVIC
30 * 70000000 256M IPU (MAX M2)
31 * 80000000 256M CSD0 SDRAM/DDR
32 * 90000000 256M CSD1 SDRAM/DDR
33 * A0000000 128M CS0 Flash
34 * A8000000 128M CS1 Flash
35 * B0000000 32M CS2
36 * B2000000 32M CS3
37 * F4000000 B4000000 32M CS4
38 * B6000000 32M CS5
39 * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers
40 * C0000000 64M PCMCIA/CF
41 */
42
43#define CS0_BASE_ADDR 0xA0000000
44#define CS1_BASE_ADDR 0xA8000000
45#define CS2_BASE_ADDR 0xB0000000
46#define CS3_BASE_ADDR 0xB2000000
47
48#define CS4_BASE_ADDR 0xB4000000
49#define CS4_BASE_ADDR_VIRT 0xF4000000
50#define CS4_SIZE SZ_32M
51
52#define CS5_BASE_ADDR 0xB6000000
53#define PCMCIA_MEM_BASE_ADDR 0xBC000000
54
55/*
56 * IRAM 2 * IRAM
57 */ 3 */
58#define IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */ 4#define MX31_IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */
59#define IRAM_BASE_ADDR_VIRT 0xF8000000 5#define MX31_IRAM_SIZE SZ_16K
60#define IRAM_SIZE SZ_16K
61
62/*
63 * L2CC
64 */
65#define L2CC_BASE_ADDR 0x30000000
66#define L2CC_BASE_ADDR_VIRT 0xF9000000
67#define L2CC_SIZE SZ_1M
68
69/*
70 * AIPS 1
71 */
72#define AIPS1_BASE_ADDR 0x43F00000
73#define AIPS1_BASE_ADDR_VIRT 0xFC000000
74#define AIPS1_SIZE SZ_1M
75 6
76#define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000)
77#define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000)
78#define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000)
79#define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000)
80#define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000)
81#define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000)
82#define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
83#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
84#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) 7#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
85#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) 8#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
86#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
87#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
88#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
89#define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
90#define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
91#define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
92#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
93#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
94#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) 9#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
95#define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) 10#define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
96#define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
97#define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
98
99/*
100 * SPBA global module enabled #0
101 */
102#define SPBA0_BASE_ADDR 0x50000000
103#define SPBA0_BASE_ADDR_VIRT 0xFC100000
104#define SPBA0_SIZE SZ_1M
105 11
106#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) 12#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
107#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) 13#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
108#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
109#define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
110#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
111#define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000) 14#define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000)
112#define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000) 15#define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000)
113#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
114#define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
115#define MSHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
116#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
117 16
118/*
119 * AIPS 2
120 */
121#define AIPS2_BASE_ADDR 0x53F00000
122#define AIPS2_BASE_ADDR_VIRT 0xFC200000
123#define AIPS2_SIZE SZ_1M
124#define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
125#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) 17#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
126#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000) 18#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000)
127#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
128#define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
129#define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
130#define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
131#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
132#define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000) 19#define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000)
133#define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000) 20#define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000)
134#define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
135#define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
136#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
137#define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) 21#define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
138#define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
139#define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
140#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000)
141#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
142#define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
143#define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
144#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
145
146/*
147 * ROMP and AVIC
148 */
149#define ROMP_BASE_ADDR 0x60000000
150#define ROMP_BASE_ADDR_VIRT 0xFC500000
151#define ROMP_SIZE SZ_1M
152
153#define AVIC_BASE_ADDR 0x68000000
154#define AVIC_BASE_ADDR_VIRT 0xFC400000
155#define AVIC_SIZE SZ_1M
156
157/*
158 * NAND, SDRAM, WEIM, M3IF, EMI controllers
159 */
160#define X_MEMC_BASE_ADDR 0xB8000000
161#define X_MEMC_BASE_ADDR_VIRT 0xFC320000
162#define X_MEMC_SIZE SZ_64K
163 22
164#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000) 23#define MX31_NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000)
165#define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
166#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
167#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
168#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
169#define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR
170 24
171/*
172 * Memory regions and CS
173 */
174#define IPU_MEM_BASE_ADDR 0x70000000
175#define CSD0_BASE_ADDR 0x80000000
176#define CSD1_BASE_ADDR 0x90000000
177#define CS0_BASE_ADDR 0xA0000000
178#define CS1_BASE_ADDR 0xA8000000
179#define CS2_BASE_ADDR 0xB0000000
180#define CS3_BASE_ADDR 0xB2000000
181
182#define CS4_BASE_ADDR 0xB4000000
183#define CS4_BASE_ADDR_VIRT 0xF4000000
184#define CS4_SIZE SZ_32M
185
186#define CS5_BASE_ADDR 0xB6000000
187#define PCMCIA_MEM_BASE_ADDR 0xBC000000
188
189/*!
190 * This macro defines the physical to virtual address mapping for all the
191 * peripheral modules. It is used by passing in the physical address as x
192 * and returning the virtual address. If the physical address is not mapped,
193 * it returns 0xDEADBEEF
194 */
195#define IO_ADDRESS(x) \
196 (void __iomem *) \
197 (((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\
198 ((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\
199 ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
200 ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
201 ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
202 ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
203 ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
204 ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
205 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
206 0xDEADBEEF)
207
208/*
209 * define the address mapping macros: in physical address order
210 */
211
212#define IRAM_IO_ADDRESS(x) \
213 (((x) - IRAM_BASE_ADDR) + IRAM_BASE_ADDR_VIRT)
214
215#define L2CC_IO_ADDRESS(x) \
216 (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
217
218#define AIPS1_IO_ADDRESS(x) \
219 (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
220
221#define SPBA0_IO_ADDRESS(x) \
222 (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
223
224#define AIPS2_IO_ADDRESS(x) \
225 (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
226
227#define ROMP_IO_ADDRESS(x) \
228 (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
229
230#define AVIC_IO_ADDRESS(x) \
231 (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
232
233#define CS4_IO_ADDRESS(x) \
234 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
235
236#define X_MEMC_IO_ADDRESS(x) \
237 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
238
239#define PCMCIA_IO_ADDRESS(x) \
240 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
241
242/*
243 * Interrupt numbers
244 */
245#define MXC_INT_PEN_ADS7843 0
246#define MXC_INT_RESV1 1
247#define MXC_INT_CS8900A 2
248#define MXC_INT_I2C3 3
249#define MXC_INT_I2C2 4
250#define MXC_INT_MPEG4_ENCODER 5 25#define MXC_INT_MPEG4_ENCODER 5
251#define MXC_INT_RTIC 6
252#define MXC_INT_FIRI 7 26#define MXC_INT_FIRI 7
253#define MXC_INT_MMC_SDHC2 8 27#define MX31_INT_MMC_SDHC2 8
254#define MXC_INT_MMC_SDHC1 9 28#define MXC_INT_MMC_SDHC1 9
255#define MXC_INT_I2C 10 29#define MX31_INT_SSI2 11
256#define MXC_INT_SSI2 11 30#define MX31_INT_SSI1 12
257#define MXC_INT_SSI1 12
258#define MXC_INT_CSPI2 13
259#define MXC_INT_CSPI1 14
260#define MXC_INT_ATA 15
261#define MXC_INT_MBX 16 31#define MXC_INT_MBX 16
262#define MXC_INT_CSPI3 17 32#define MXC_INT_CSPI3 17
263#define MXC_INT_UART3 18
264#define MXC_INT_IIM 19
265#define MXC_INT_SIM2 20 33#define MXC_INT_SIM2 20
266#define MXC_INT_SIM1 21 34#define MXC_INT_SIM1 21
267#define MXC_INT_RNGA 22 35#define MXC_INT_CCM_DVFS 31
268#define MXC_INT_EVTMON 23
269#define MXC_INT_KPP 24
270#define MXC_INT_RTC 25
271#define MXC_INT_PWM 26
272#define MXC_INT_EPIT2 27
273#define MXC_INT_EPIT1 28
274#define MXC_INT_GPT 29
275#define MXC_INT_RESV30 30
276#define MXC_INT_RESV31 31
277#define MXC_INT_UART2 32
278#define MXC_INT_NANDFC 33
279#define MXC_INT_SDMA 34
280#define MXC_INT_USB1 35 36#define MXC_INT_USB1 35
281#define MXC_INT_USB2 36 37#define MXC_INT_USB2 36
282#define MXC_INT_USB3 37 38#define MXC_INT_USB3 37
283#define MXC_INT_USB4 38 39#define MXC_INT_USB4 38
284#define MXC_INT_MSHC1 39
285#define MXC_INT_MSHC2 40 40#define MXC_INT_MSHC2 40
286#define MXC_INT_IPU_ERR 41
287#define MXC_INT_IPU_SYN 42
288#define MXC_INT_RESV43 43
289#define MXC_INT_RESV44 44
290#define MXC_INT_UART1 45
291#define MXC_INT_UART4 46 41#define MXC_INT_UART4 46
292#define MXC_INT_UART5 47 42#define MXC_INT_UART5 47
293#define MXC_INT_ECT 48
294#define MXC_INT_SCC_SCM 49
295#define MXC_INT_SCC_SMN 50
296#define MXC_INT_GPIO2 51
297#define MXC_INT_GPIO1 52
298#define MXC_INT_CCM 53 43#define MXC_INT_CCM 53
299#define MXC_INT_PCMCIA 54 44#define MXC_INT_PCMCIA 54
300#define MXC_INT_WDOG 55
301#define MXC_INT_GPIO3 56
302#define MXC_INT_RESV57 57
303#define MXC_INT_EXT_POWER 58
304#define MXC_INT_EXT_TEMPER 59
305#define MXC_INT_EXT_SENSOR60 60
306#define MXC_INT_EXT_SENSOR61 61
307#define MXC_INT_EXT_WDOG 62
308#define MXC_INT_EXT_TV 63
309
310#define PROD_SIGNATURE 0x1 /* For MX31 */
311
312/* silicon revisions specific to i.MX31 */
313#define CHIP_REV_1_0 0x10
314#define CHIP_REV_1_1 0x11
315#define CHIP_REV_1_2 0x12
316#define CHIP_REV_1_3 0x13
317#define CHIP_REV_2_0 0x20
318#define CHIP_REV_2_1 0x21
319#define CHIP_REV_2_2 0x22
320#define CHIP_REV_2_3 0x23
321#define CHIP_REV_3_0 0x30
322#define CHIP_REV_3_1 0x31
323#define CHIP_REV_3_2 0x32
324
325#define SYSTEM_REV_MIN CHIP_REV_1_0
326#define SYSTEM_REV_NUM 3
327
328/* gpio and gpio based interrupt handling */
329#define GPIO_DR 0x00
330#define GPIO_GDIR 0x04
331#define GPIO_PSR 0x08
332#define GPIO_ICR1 0x0C
333#define GPIO_ICR2 0x10
334#define GPIO_IMR 0x14
335#define GPIO_ISR 0x18
336#define GPIO_INT_LOW_LEV 0x0
337#define GPIO_INT_HIGH_LEV 0x1
338#define GPIO_INT_RISE_EDGE 0x2
339#define GPIO_INT_FALL_EDGE 0x3
340#define GPIO_INT_NONE 0x4
341
342/* Mandatory defines used globally */
343
344/* this CPU supports up to 96 GPIOs */
345#define ARCH_NR_GPIOS 96
346
347#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
348
349/* this is a i.MX31 CPU */
350#define cpu_is_mx31() (1)
351
352extern unsigned int system_rev;
353
354static inline int mx31_revision(void)
355{
356 return system_rev;
357}
358#endif
359 45
360#endif /* __ASM_ARCH_MXC_MX31_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
new file mode 100644
index 000000000000..6465fefb42e3
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -0,0 +1,29 @@
1/*
2 * IRAM
3 */
4#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */
5#define MX35_IRAM_SIZE SZ_128K
6
7#define MXC_FEC_BASE_ADDR 0x50038000
8#define MX35_NFC_BASE_ADDR 0xBB000000
9
10/*
11 * Interrupt numbers
12 */
13#define MXC_INT_OWIRE 2
14#define MX35_INT_MMC_SDHC1 7
15#define MXC_INT_MMC_SDHC2 8
16#define MXC_INT_MMC_SDHC3 9
17#define MX35_INT_SSI1 11
18#define MX35_INT_SSI2 12
19#define MXC_INT_GPU2D 16
20#define MXC_INT_ASRC 17
21#define MXC_INT_USBHS 35
22#define MXC_INT_USBOTG 37
23#define MXC_INT_ESAI 40
24#define MXC_INT_CAN1 43
25#define MXC_INT_CAN2 44
26#define MXC_INT_MLB 46
27#define MXC_INT_SPDIF 47
28#define MXC_INT_FEC 57
29
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
new file mode 100644
index 000000000000..3878c6085d5c
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -0,0 +1,290 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_MX31_H__
12#define __ASM_ARCH_MXC_MX31_H__
13
14#ifndef __ASM_ARCH_MXC_HARDWARE_H__
15#error "Do not include directly."
16#endif
17
18/*
19 * MX31 memory map:
20 *
21 * Virt Phys Size What
22 * ---------------------------------------------------------------------------
23 * FC000000 43F00000 1M AIPS 1
24 * FC100000 50000000 1M SPBA
25 * FC200000 53F00000 1M AIPS 2
26 * FC500000 60000000 128M ROMPATCH
27 * FC400000 68000000 128M AVIC
28 * 70000000 256M IPU (MAX M2)
29 * 80000000 256M CSD0 SDRAM/DDR
30 * 90000000 256M CSD1 SDRAM/DDR
31 * A0000000 128M CS0 Flash
32 * A8000000 128M CS1 Flash
33 * B0000000 32M CS2
34 * B2000000 32M CS3
35 * F4000000 B4000000 32M CS4
36 * B6000000 32M CS5
37 * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers
38 * C0000000 64M PCMCIA/CF
39 */
40
41#define CS0_BASE_ADDR 0xA0000000
42#define CS1_BASE_ADDR 0xA8000000
43#define CS2_BASE_ADDR 0xB0000000
44#define CS3_BASE_ADDR 0xB2000000
45
46#define CS4_BASE_ADDR 0xB4000000
47#define CS4_BASE_ADDR_VIRT 0xF4000000
48#define CS4_SIZE SZ_32M
49
50#define CS5_BASE_ADDR 0xB6000000
51#define PCMCIA_MEM_BASE_ADDR 0xBC000000
52
53/*
54 * L2CC
55 */
56#define L2CC_BASE_ADDR 0x30000000
57#define L2CC_SIZE SZ_1M
58
59/*
60 * AIPS 1
61 */
62#define AIPS1_BASE_ADDR 0x43F00000
63#define AIPS1_BASE_ADDR_VIRT 0xFC000000
64#define AIPS1_SIZE SZ_1M
65
66#define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000)
67#define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000)
68#define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000)
69#define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000)
70#define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000)
71#define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000)
72#define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
73#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
74#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
75#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
76#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
77#define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
78#define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
79#define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
80#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
81#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
82#define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
83#define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
84
85/*
86 * SPBA global module enabled #0
87 */
88#define SPBA0_BASE_ADDR 0x50000000
89#define SPBA0_BASE_ADDR_VIRT 0xFC100000
90#define SPBA0_SIZE SZ_1M
91
92#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
93#define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
94#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
95#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
96#define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
97#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
98
99/*
100 * AIPS 2
101 */
102#define AIPS2_BASE_ADDR 0x53F00000
103#define AIPS2_BASE_ADDR_VIRT 0xFC200000
104#define AIPS2_SIZE SZ_1M
105#define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
106#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
107#define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
108#define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
109#define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
110#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
111#define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
112#define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
113#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
114#define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
115#define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
116#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000)
117#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
118#define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
119#define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
120#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
121
122/*
123 * ROMP and AVIC
124 */
125#define ROMP_BASE_ADDR 0x60000000
126#define ROMP_BASE_ADDR_VIRT 0xFC500000
127#define ROMP_SIZE SZ_1M
128
129#define AVIC_BASE_ADDR 0x68000000
130#define AVIC_BASE_ADDR_VIRT 0xFC400000
131#define AVIC_SIZE SZ_1M
132
133/*
134 * NAND, SDRAM, WEIM, M3IF, EMI controllers
135 */
136#define X_MEMC_BASE_ADDR 0xB8000000
137#define X_MEMC_BASE_ADDR_VIRT 0xFC320000
138#define X_MEMC_SIZE SZ_64K
139
140#define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
141#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
142#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
143#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
144#define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR
145
146/*
147 * Memory regions and CS
148 */
149#define IPU_MEM_BASE_ADDR 0x70000000
150#define CSD0_BASE_ADDR 0x80000000
151#define CSD1_BASE_ADDR 0x90000000
152
153/*!
154 * This macro defines the physical to virtual address mapping for all the
155 * peripheral modules. It is used by passing in the physical address as x
156 * and returning the virtual address. If the physical address is not mapped,
157 * it returns 0xDEADBEEF
158 */
159#define IO_ADDRESS(x) \
160 (void __force __iomem *) \
161 (((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
162 ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
163 ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
164 ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
165 ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
166 ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
167 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
168 0xDEADBEEF)
169
170/*
171 * define the address mapping macros: in physical address order
172 */
173#define L2CC_IO_ADDRESS(x) \
174 (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
175
176#define AIPS1_IO_ADDRESS(x) \
177 (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
178
179#define SPBA0_IO_ADDRESS(x) \
180 (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
181
182#define AIPS2_IO_ADDRESS(x) \
183 (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
184
185#define ROMP_IO_ADDRESS(x) \
186 (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
187
188#define AVIC_IO_ADDRESS(x) \
189 (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
190
191#define CS4_IO_ADDRESS(x) \
192 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
193
194#define X_MEMC_IO_ADDRESS(x) \
195 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
196
197#define PCMCIA_IO_ADDRESS(x) \
198 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
199
200/*
201 * Interrupt numbers
202 */
203#define MXC_INT_I2C3 3
204#define MXC_INT_I2C2 4
205#define MXC_INT_RTIC 6
206#define MXC_INT_I2C 10
207#define MXC_INT_CSPI2 13
208#define MXC_INT_CSPI1 14
209#define MXC_INT_ATA 15
210#define MXC_INT_UART3 18
211#define MXC_INT_IIM 19
212#define MXC_INT_RNGA 22
213#define MXC_INT_EVTMON 23
214#define MXC_INT_KPP 24
215#define MXC_INT_RTC 25
216#define MXC_INT_PWM 26
217#define MXC_INT_EPIT2 27
218#define MXC_INT_EPIT1 28
219#define MXC_INT_GPT 29
220#define MXC_INT_POWER_FAIL 30
221#define MXC_INT_UART2 32
222#define MXC_INT_NANDFC 33
223#define MXC_INT_SDMA 34
224#define MXC_INT_MSHC1 39
225#define MXC_INT_IPU_ERR 41
226#define MXC_INT_IPU_SYN 42
227#define MXC_INT_UART1 45
228#define MXC_INT_ECT 48
229#define MXC_INT_SCC_SCM 49
230#define MXC_INT_SCC_SMN 50
231#define MXC_INT_GPIO2 51
232#define MXC_INT_GPIO1 52
233#define MXC_INT_WDOG 55
234#define MXC_INT_GPIO3 56
235#define MXC_INT_EXT_POWER 58
236#define MXC_INT_EXT_TEMPER 59
237#define MXC_INT_EXT_SENSOR60 60
238#define MXC_INT_EXT_SENSOR61 61
239#define MXC_INT_EXT_WDOG 62
240#define MXC_INT_EXT_TV 63
241
242#define PROD_SIGNATURE 0x1 /* For MX31 */
243
244/* silicon revisions specific to i.MX31 */
245#define CHIP_REV_1_0 0x10
246#define CHIP_REV_1_1 0x11
247#define CHIP_REV_1_2 0x12
248#define CHIP_REV_1_3 0x13
249#define CHIP_REV_2_0 0x20
250#define CHIP_REV_2_1 0x21
251#define CHIP_REV_2_2 0x22
252#define CHIP_REV_2_3 0x23
253#define CHIP_REV_3_0 0x30
254#define CHIP_REV_3_1 0x31
255#define CHIP_REV_3_2 0x32
256
257#define SYSTEM_REV_MIN CHIP_REV_1_0
258#define SYSTEM_REV_NUM 3
259
260/* gpio and gpio based interrupt handling */
261#define GPIO_DR 0x00
262#define GPIO_GDIR 0x04
263#define GPIO_PSR 0x08
264#define GPIO_ICR1 0x0C
265#define GPIO_ICR2 0x10
266#define GPIO_IMR 0x14
267#define GPIO_ISR 0x18
268#define GPIO_INT_LOW_LEV 0x0
269#define GPIO_INT_HIGH_LEV 0x1
270#define GPIO_INT_RISE_EDGE 0x2
271#define GPIO_INT_FALL_EDGE 0x3
272#define GPIO_INT_NONE 0x4
273
274/* Mandatory defines used globally */
275
276/* this CPU supports up to 96 GPIOs */
277#define ARCH_NR_GPIOS 96
278
279#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
280
281extern unsigned int system_rev;
282
283static inline int mx31_revision(void)
284{
285 return system_rev;
286}
287#endif
288
289#endif /* __ASM_ARCH_MXC_MX31_H__ */
290
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index f6caab062131..5fa2a07f4eaf 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -24,13 +24,74 @@
24#error "Do not include directly." 24#error "Do not include directly."
25#endif 25#endif
26 26
27/* clean up all things that are not used */ 27#define MXC_CPU_MX1 1
28#ifndef CONFIG_ARCH_MX3 28#define MXC_CPU_MX21 21
29# define cpu_is_mx31() (0) 29#define MXC_CPU_MX27 27
30#define MXC_CPU_MX31 31
31#define MXC_CPU_MX35 35
32
33#ifndef __ASSEMBLY__
34extern unsigned int __mxc_cpu_type;
35#endif
36
37#ifdef CONFIG_ARCH_MX1
38# ifdef mxc_cpu_type
39# undef mxc_cpu_type
40# define mxc_cpu_type __mxc_cpu_type
41# else
42# define mxc_cpu_type MXC_CPU_MX1
43# endif
44# define cpu_is_mx1() (mxc_cpu_type == MXC_CPU_MX1)
45#else
46# define cpu_is_mx1() (0)
47#endif
48
49#ifdef CONFIG_MACH_MX21
50# ifdef mxc_cpu_type
51# undef mxc_cpu_type
52# define mxc_cpu_type __mxc_cpu_type
53# else
54# define mxc_cpu_type MXC_CPU_MX21
55# endif
56# define cpu_is_mx21() (mxc_cpu_type == MXC_CPU_MX21)
57#else
58# define cpu_is_mx21() (0)
30#endif 59#endif
31 60
32#ifndef CONFIG_MACH_MX27 61#ifdef CONFIG_MACH_MX27
33# define cpu_is_mx27() (0) 62# ifdef mxc_cpu_type
63# undef mxc_cpu_type
64# define mxc_cpu_type __mxc_cpu_type
65# else
66# define mxc_cpu_type MXC_CPU_MX27
67# endif
68# define cpu_is_mx27() (mxc_cpu_type == MXC_CPU_MX27)
69#else
70# define cpu_is_mx27() (0)
71#endif
72
73#ifdef CONFIG_ARCH_MX31
74# ifdef mxc_cpu_type
75# undef mxc_cpu_type
76# define mxc_cpu_type __mxc_cpu_type
77# else
78# define mxc_cpu_type MXC_CPU_MX31
79# endif
80# define cpu_is_mx31() (mxc_cpu_type == MXC_CPU_MX31)
81#else
82# define cpu_is_mx31() (0)
83#endif
84
85#ifdef CONFIG_ARCH_MX35
86# ifdef mxc_cpu_type
87# undef mxc_cpu_type
88# define mxc_cpu_type __mxc_cpu_type
89# else
90# define mxc_cpu_type MXC_CPU_MX35
91# endif
92# define cpu_is_mx35() (mxc_cpu_type == MXC_CPU_MX35)
93#else
94# define cpu_is_mx35() (0)
34#endif 95#endif
35 96
36#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) 97#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
@@ -39,4 +100,7 @@
39#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8) 100#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8)
40#endif 101#endif
41 102
103#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35())
104#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
105
42#endif /* __ASM_ARCH_MXC_H__ */ 106#endif /* __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/plat-mxc/iomux-mx1-mx2.c b/arch/arm/plat-mxc/iomux-mx1-mx2.c
index df6f18395686..a37163ce280b 100644
--- a/arch/arm/plat-mxc/iomux-mx1-mx2.c
+++ b/arch/arm/plat-mxc/iomux-mx1-mx2.c
@@ -32,7 +32,7 @@
32 32
33#include <mach/hardware.h> 33#include <mach/hardware.h>
34#include <asm/mach/map.h> 34#include <asm/mach/map.h>
35#include <mach/iomux-mx1-mx2.h> 35#include <mach/iomux.h>
36 36
37void mxc_gpio_mode(int gpio_mode) 37void mxc_gpio_mode(int gpio_mode)
38{ 38{
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
new file mode 100644
index 000000000000..9bffbc507cc2
--- /dev/null
+++ b/arch/arm/plat-mxc/pwm.c
@@ -0,0 +1,300 @@
1/*
2 * simple driver for PWM (Pulse Width Modulator) controller
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/platform_device.h>
14#include <linux/err.h>
15#include <linux/clk.h>
16#include <linux/io.h>
17#include <linux/pwm.h>
18
19#if defined CONFIG_ARCH_MX1 || defined CONFIG_ARCH_MX21
20#define PWM_VER_1
21
22#define PWMCR 0x00 /* PWM Control Register */
23#define PWMSR 0x04 /* PWM Sample Register */
24#define PWMPR 0x08 /* PWM Period Register */
25#define PWMCNR 0x0C /* PWM Counter Register */
26
27#define PWMCR_HCTR (1 << 18) /* Halfword FIFO Data Swapping */
28#define PWMCR_BCTR (1 << 17) /* Byte FIFO Data Swapping */
29#define PWMCR_SWR (1 << 16) /* Software Reset */
30#define PWMCR_CLKSRC_PERCLK (0 << 15) /* PERCLK Clock Source */
31#define PWMCR_CLKSRC_CLK32 (1 << 15) /* 32KHz Clock Source */
32#define PWMCR_PRESCALER(x) (((x - 1) & 0x7F) << 8) /* PRESCALER */
33#define PWMCR_IRQ (1 << 7) /* Interrupt Request */
34#define PWMCR_IRQEN (1 << 6) /* Interrupt Request Enable */
35#define PWMCR_FIFOAV (1 << 5) /* FIFO Available */
36#define PWMCR_EN (1 << 4) /* Enables/Disables the PWM */
37#define PWMCR_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */
38#define PWMCR_DIV(x) (((x) & 0x03) << 0) /* Clock divider 2/4/8/16 */
39
40#define MAX_DIV (128 * 16)
41#endif
42
43#if defined CONFIG_MACH_MX27 || defined CONFIG_ARCH_MX31
44#define PWM_VER_2
45
46#define PWMCR 0x00 /* PWM Control Register */
47#define PWMSR 0x04 /* PWM Status Register */
48#define PWMIR 0x08 /* PWM Interrupt Register */
49#define PWMSAR 0x0C /* PWM Sample Register */
50#define PWMPR 0x10 /* PWM Period Register */
51#define PWMCNR 0x14 /* PWM Counter Register */
52
53#define PWMCR_EN (1 << 0) /* Enables/Disables the PWM */
54#define PWMCR_REPEAT(x) (((x) & 0x03) << 1) /* Sample Repeats */
55#define PWMCR_SWR (1 << 3) /* Software Reset */
56#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)/* PRESCALER */
57#define PWMCR_CLKSRC(x) (((x) & 0x3) << 16)
58#define PWMCR_CLKSRC_OFF (0 << 16)
59#define PWMCR_CLKSRC_IPG (1 << 16)
60#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
61#define PWMCR_CLKSRC_CLK32 (3 << 16)
62#define PWMCR_POUTC
63#define PWMCR_HCTR (1 << 20) /* Halfword FIFO Data Swapping */
64#define PWMCR_BCTR (1 << 21) /* Byte FIFO Data Swapping */
65#define PWMCR_DBGEN (1 << 22) /* Debug Mode */
66#define PWMCR_WAITEN (1 << 23) /* Wait Mode */
67#define PWMCR_DOZEN (1 << 24) /* Doze Mode */
68#define PWMCR_STOPEN (1 << 25) /* Stop Mode */
69#define PWMCR_FWM(x) (((x) & 0x3) << 26) /* FIFO Water Mark */
70
71#define MAX_DIV 4096
72#endif
73
74#define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */
75#define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */
76#define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */
77
78struct pwm_device {
79 struct list_head node;
80 struct platform_device *pdev;
81
82 const char *label;
83 struct clk *clk;
84
85 int clk_enabled;
86 void __iomem *mmio_base;
87
88 unsigned int use_count;
89 unsigned int pwm_id;
90};
91
92int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
93{
94 unsigned long long c;
95 unsigned long period_cycles, duty_cycles, prescale;
96
97 if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
98 return -EINVAL;
99
100 c = clk_get_rate(pwm->clk);
101 c = c * period_ns;
102 do_div(c, 1000000000);
103 period_cycles = c;
104
105 prescale = period_cycles / 0x10000 + 1;
106
107 period_cycles /= prescale;
108 c = (unsigned long long)period_cycles * duty_ns;
109 do_div(c, period_ns);
110 duty_cycles = c;
111
112#ifdef PWM_VER_2
113 writel(duty_cycles, pwm->mmio_base + PWMSAR);
114 writel(period_cycles, pwm->mmio_base + PWMPR);
115 writel(PWMCR_PRESCALER(prescale - 1) | PWMCR_CLKSRC_IPG_HIGH | PWMCR_EN,
116 pwm->mmio_base + PWMCR);
117#elif defined PWM_VER_1
118#error PWM not yet working on MX1 / MX21
119#endif
120
121 return 0;
122}
123EXPORT_SYMBOL(pwm_config);
124
125int pwm_enable(struct pwm_device *pwm)
126{
127 int rc = 0;
128
129 if (!pwm->clk_enabled) {
130 rc = clk_enable(pwm->clk);
131 if (!rc)
132 pwm->clk_enabled = 1;
133 }
134 return rc;
135}
136EXPORT_SYMBOL(pwm_enable);
137
138void pwm_disable(struct pwm_device *pwm)
139{
140 if (pwm->clk_enabled) {
141 clk_disable(pwm->clk);
142 pwm->clk_enabled = 0;
143 }
144}
145EXPORT_SYMBOL(pwm_disable);
146
147static DEFINE_MUTEX(pwm_lock);
148static LIST_HEAD(pwm_list);
149
150struct pwm_device *pwm_request(int pwm_id, const char *label)
151{
152 struct pwm_device *pwm;
153 int found = 0;
154
155 mutex_lock(&pwm_lock);
156
157 list_for_each_entry(pwm, &pwm_list, node) {
158 if (pwm->pwm_id == pwm_id) {
159 found = 1;
160 break;
161 }
162 }
163
164 if (found) {
165 if (pwm->use_count == 0) {
166 pwm->use_count++;
167 pwm->label = label;
168 } else
169 pwm = ERR_PTR(-EBUSY);
170 } else
171 pwm = ERR_PTR(-ENOENT);
172
173 mutex_unlock(&pwm_lock);
174 return pwm;
175}
176EXPORT_SYMBOL(pwm_request);
177
178void pwm_free(struct pwm_device *pwm)
179{
180 mutex_lock(&pwm_lock);
181
182 if (pwm->use_count) {
183 pwm->use_count--;
184 pwm->label = NULL;
185 } else
186 pr_warning("PWM device already freed\n");
187
188 mutex_unlock(&pwm_lock);
189}
190EXPORT_SYMBOL(pwm_free);
191
192static int __devinit mxc_pwm_probe(struct platform_device *pdev)
193{
194 struct pwm_device *pwm;
195 struct resource *r;
196 int ret = 0;
197
198 pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
199 if (pwm == NULL) {
200 dev_err(&pdev->dev, "failed to allocate memory\n");
201 return -ENOMEM;
202 }
203
204 pwm->clk = clk_get(&pdev->dev, "pwm");
205
206 if (IS_ERR(pwm->clk)) {
207 ret = PTR_ERR(pwm->clk);
208 goto err_free;
209 }
210
211 pwm->clk_enabled = 0;
212
213 pwm->use_count = 0;
214 pwm->pwm_id = pdev->id;
215 pwm->pdev = pdev;
216
217 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
218 if (r == NULL) {
219 dev_err(&pdev->dev, "no memory resource defined\n");
220 ret = -ENODEV;
221 goto err_free_clk;
222 }
223
224 r = request_mem_region(r->start, r->end - r->start + 1, pdev->name);
225 if (r == NULL) {
226 dev_err(&pdev->dev, "failed to request memory resource\n");
227 ret = -EBUSY;
228 goto err_free_clk;
229 }
230
231 pwm->mmio_base = ioremap(r->start, r->end - r->start + 1);
232 if (pwm->mmio_base == NULL) {
233 dev_err(&pdev->dev, "failed to ioremap() registers\n");
234 ret = -ENODEV;
235 goto err_free_mem;
236 }
237
238 mutex_lock(&pwm_lock);
239 list_add_tail(&pwm->node, &pwm_list);
240 mutex_unlock(&pwm_lock);
241
242 platform_set_drvdata(pdev, pwm);
243 return 0;
244
245err_free_mem:
246 release_mem_region(r->start, r->end - r->start + 1);
247err_free_clk:
248 clk_put(pwm->clk);
249err_free:
250 kfree(pwm);
251 return ret;
252}
253
254static int __devexit mxc_pwm_remove(struct platform_device *pdev)
255{
256 struct pwm_device *pwm;
257 struct resource *r;
258
259 pwm = platform_get_drvdata(pdev);
260 if (pwm == NULL)
261 return -ENODEV;
262
263 mutex_lock(&pwm_lock);
264 list_del(&pwm->node);
265 mutex_unlock(&pwm_lock);
266
267 iounmap(pwm->mmio_base);
268
269 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
270 release_mem_region(r->start, r->end - r->start + 1);
271
272 clk_put(pwm->clk);
273
274 kfree(pwm);
275 return 0;
276}
277
278static struct platform_driver mxc_pwm_driver = {
279 .driver = {
280 .name = "mxc_pwm",
281 },
282 .probe = mxc_pwm_probe,
283 .remove = __devexit_p(mxc_pwm_remove),
284};
285
286static int __init mxc_pwm_init(void)
287{
288 return platform_driver_register(&mxc_pwm_driver);
289}
290arch_initcall(mxc_pwm_init);
291
292static void __exit mxc_pwm_exit(void)
293{
294 platform_driver_unregister(&mxc_pwm_driver);
295}
296module_exit(mxc_pwm_exit);
297
298MODULE_LICENSE("GPL v2");
299MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
300
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 758a1293bcfa..ef1b3cd85bd3 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -34,9 +34,6 @@
34static struct clock_event_device clockevent_mxc; 34static struct clock_event_device clockevent_mxc;
35static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; 35static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
36 36
37/* clock source for the timer */
38static struct clk *timer_clk;
39
40/* clock source */ 37/* clock source */
41 38
42static cycle_t mxc_get_cycles(void) 39static cycle_t mxc_get_cycles(void)
@@ -53,13 +50,11 @@ static struct clocksource clocksource_mxc = {
53 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 50 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
54}; 51};
55 52
56static int __init mxc_clocksource_init(void) 53static int __init mxc_clocksource_init(struct clk *timer_clk)
57{ 54{
58 unsigned int clock; 55 unsigned int c = clk_get_rate(timer_clk);
59
60 clock = clk_get_rate(timer_clk);
61 56
62 clocksource_mxc.mult = clocksource_hz2mult(clock, 57 clocksource_mxc.mult = clocksource_hz2mult(c,
63 clocksource_mxc.shift); 58 clocksource_mxc.shift);
64 clocksource_register(&clocksource_mxc); 59 clocksource_register(&clocksource_mxc);
65 60
@@ -177,13 +172,11 @@ static struct clock_event_device clockevent_mxc = {
177 .rating = 200, 172 .rating = 200,
178}; 173};
179 174
180static int __init mxc_clockevent_init(void) 175static int __init mxc_clockevent_init(struct clk *timer_clk)
181{ 176{
182 unsigned int clock; 177 unsigned int c = clk_get_rate(timer_clk);
183
184 clock = clk_get_rate(timer_clk);
185 178
186 clockevent_mxc.mult = div_sc(clock, NSEC_PER_SEC, 179 clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
187 clockevent_mxc.shift); 180 clockevent_mxc.shift);
188 clockevent_mxc.max_delta_ns = 181 clockevent_mxc.max_delta_ns =
189 clockevent_delta2ns(0xfffffffe, &clockevent_mxc); 182 clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
@@ -197,14 +190,8 @@ static int __init mxc_clockevent_init(void)
197 return 0; 190 return 0;
198} 191}
199 192
200void __init mxc_timer_init(const char *clk_timer) 193void __init mxc_timer_init(struct clk *timer_clk)
201{ 194{
202 timer_clk = clk_get(NULL, clk_timer);
203 if (!timer_clk) {
204 printk(KERN_ERR"Cannot determine timer clock. Giving up.\n");
205 return;
206 }
207
208 clk_enable(timer_clk); 195 clk_enable(timer_clk);
209 196
210 /* 197 /*
@@ -219,10 +206,9 @@ void __init mxc_timer_init(const char *clk_timer)
219 TIMER_BASE + MXC_TCTL); 206 TIMER_BASE + MXC_TCTL);
220 207
221 /* init and register the timer to the framework */ 208 /* init and register the timer to the framework */
222 mxc_clocksource_init(); 209 mxc_clocksource_init(timer_clk);
223 mxc_clockevent_init(); 210 mxc_clockevent_init(timer_clk);
224 211
225 /* Make irqs happen */ 212 /* Make irqs happen */
226 setup_irq(TIMER_INTERRUPT, &mxc_timer_irq); 213 setup_irq(TIMER_INTERRUPT, &mxc_timer_irq);
227} 214}
228
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-01 08:36:02 -0400