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authorLinus Torvalds <torvalds@linux-foundation.org>2009-12-08 11:12:43 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2009-12-08 11:12:43 -0500
commit79c9601c2e0dbbe69895d302de4d19f3a31fbd30 (patch)
tree78d4be2df851b2b4106adcfd736622a90cecf9e9 /arch/arm/plat-mxc
parent41440ffe21f29bdb985cab76b2d0b06d83e63b19 (diff)
parent3d14b5beba35250c548d3851a2b84fce742d8311 (diff)
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (272 commits) Fix soc_common PCMCIA configuration ARM: 5827/1: SA1100: h3100/h3600: emit messages on failed gpio_request ARM: 5826/1: SA1100: h3100/h3600: always build htc-egpio driver ARM: 5825/1: SA1100: h3600: update defconfig ARM: 5824/1: SA1100: reuse h3600 PCMCIA driver on h3100 ARM: 5823/1: SA1100: h3100/h3600: add support for gpio-keys ARM: 5822/1: SA1100: h3100/h3600: clean up #includes ARM: 5821/1: SA1100: h3100/h3600: revise copyright boilerplates ARM: 5820/1: SA1100: h3100/h3600: split h3600.c ARM: 5819/1: SA1100: h3100/h3600: merge h3600.h and h3600_gpio.h into h3xxx.h ARM: 5818/1: SA1100: h3100/h3600: drop old GPIO definitions ARM: 5817/1: SA1100: h3100/h3600: configure all unused gpios as inputs ARM: 5816/1: SA1100: h3600: remove IRQ_GPIO_* definitions ARM: 5815/1: SA1100: h3100/h3600: remove now unused assign_h3600_egpio handlers ARM: 5814/1: SA1100: h3100/h3600: convert all users of assign_h3600_egpio to gpiolib ARM: 5813/1: SA1100: h3100/h3600: add htc-egpio driver ARM: 5812/1: SA1100: h3100/h3600: separate machine-specific LCD helpers ARM: 5811/2: pcmcia: convert sa1100_h3600 driver to gpiolib ARM: 5799/1: SA1100: h3600: stop setting direction for LCD pins ARM: 5798/1: SA1100: h3600: remove unused cruft from h3600.h ...
Diffstat (limited to 'arch/arm/plat-mxc')
-rw-r--r--arch/arm/plat-mxc/Kconfig10
-rw-r--r--arch/arm/plat-mxc/Makefile3
-rw-r--r--arch/arm/plat-mxc/audmux-v1.c58
-rw-r--r--arch/arm/plat-mxc/audmux-v2.c74
-rw-r--r--arch/arm/plat-mxc/dma-mx1-mx2.c3
-rw-r--r--arch/arm/plat-mxc/gpio.c2
-rw-r--r--arch/arm/plat-mxc/include/mach/audmux.h52
-rw-r--r--arch/arm/plat-mxc/include/mach/board-kzmarm11.h39
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31lite.h39
-rw-r--r--arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx3.h34
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v3.h17
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux.h1
-rw-r--r--arch/arm/plat-mxc/include/mach/mx21.h207
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h10
-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h315
-rw-r--r--arch/arm/plat-mxc/include/mach/mx2x.h341
-rw-r--r--arch/arm/plat-mxc/include/mach/mx31.h237
-rw-r--r--arch/arm/plat-mxc/include/mach/mx35.h201
-rw-r--r--arch/arm/plat-mxc/include/mach/mx3x.h418
-rw-r--r--arch/arm/plat-mxc/include/mach/ulpi.h7
-rw-r--r--arch/arm/plat-mxc/include/mach/uncompress.h3
-rw-r--r--arch/arm/plat-mxc/iomux-v3.c36
-rw-r--r--arch/arm/plat-mxc/ulpi.c113
24 files changed, 1755 insertions, 473 deletions
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index ca5c7c226341..8b0a1ee039fa 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -69,10 +69,20 @@ config MXC_PWM
69 help 69 help
70 Enable support for the i.MX PWM controller(s). 70 Enable support for the i.MX PWM controller(s).
71 71
72config MXC_ULPI
73 bool
74
72config ARCH_HAS_RNGA 75config ARCH_HAS_RNGA
73 bool 76 bool
74 depends on ARCH_MXC 77 depends on ARCH_MXC
75 78
76config ARCH_MXC_IOMUX_V3 79config ARCH_MXC_IOMUX_V3
77 bool 80 bool
81
82config ARCH_MXC_AUDMUX_V1
83 bool
84
85config ARCH_MXC_AUDMUX_V2
86 bool
87
78endif 88endif
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index e3212c8ff421..4cbca9da1505 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -9,3 +9,6 @@ obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o
9obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o 9obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o
10obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o 10obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
11obj-$(CONFIG_MXC_PWM) += pwm.o 11obj-$(CONFIG_MXC_PWM) += pwm.o
12obj-$(CONFIG_MXC_ULPI) += ulpi.o
13obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
14obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c
new file mode 100644
index 000000000000..da6387dcdf21
--- /dev/null
+++ b/arch/arm/plat-mxc/audmux-v1.c
@@ -0,0 +1,58 @@
1/*
2 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
3 *
4 * Initial development of this code was funded by
5 * Phytec Messtechnik GmbH, http://www.phytec.de
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/module.h>
23#include <linux/err.h>
24#include <linux/io.h>
25#include <linux/clk.h>
26#include <mach/audmux.h>
27#include <mach/hardware.h>
28
29static void __iomem *audmux_base;
30
31static unsigned char port_mapping[] = {
32 0x0, 0x4, 0x8, 0x10, 0x14, 0x1c,
33};
34
35int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr)
36{
37 if (!audmux_base) {
38 printk("%s: not configured\n", __func__);
39 return -ENOSYS;
40 }
41
42 if (port >= ARRAY_SIZE(port_mapping))
43 return -EINVAL;
44
45 writel(pcr, audmux_base + port_mapping[port]);
46
47 return 0;
48}
49EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port);
50
51static int mxc_audmux_v1_init(void)
52{
53 if (cpu_is_mx27() || cpu_is_mx21())
54 audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR);
55 return 0;
56}
57
58postcore_initcall(mxc_audmux_v1_init);
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
new file mode 100644
index 000000000000..6f21096086fd
--- /dev/null
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -0,0 +1,74 @@
1/*
2 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
3 *
4 * Initial development of this code was funded by
5 * Phytec Messtechnik GmbH, http://www.phytec.de
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/module.h>
23#include <linux/err.h>
24#include <linux/io.h>
25#include <linux/clk.h>
26#include <mach/audmux.h>
27#include <mach/hardware.h>
28
29static struct clk *audmux_clk;
30static void __iomem *audmux_base;
31
32#define MXC_AUDMUX_V2_PTCR(x) ((x) * 8)
33#define MXC_AUDMUX_V2_PDCR(x) ((x) * 8 + 4)
34
35int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
36 unsigned int pdcr)
37{
38 if (!audmux_base)
39 return -ENOSYS;
40
41 if (audmux_clk)
42 clk_enable(audmux_clk);
43
44 writel(ptcr, audmux_base + MXC_AUDMUX_V2_PTCR(port));
45 writel(pdcr, audmux_base + MXC_AUDMUX_V2_PDCR(port));
46
47 if (audmux_clk)
48 clk_disable(audmux_clk);
49
50 return 0;
51}
52EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port);
53
54static int mxc_audmux_v2_init(void)
55{
56 int ret;
57
58 if (cpu_is_mx35()) {
59 audmux_clk = clk_get(NULL, "audmux");
60 if (IS_ERR(audmux_clk)) {
61 ret = PTR_ERR(audmux_clk);
62 printk(KERN_ERR "%s: cannot get clock: %d\n", __func__,
63 ret);
64 return ret;
65 }
66 }
67
68 if (cpu_is_mx31() || cpu_is_mx35())
69 audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR);
70
71 return 0;
72}
73
74postcore_initcall(mxc_audmux_v2_init);
diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c
index 77646436c00e..9c1b3f9c4f4d 100644
--- a/arch/arm/plat-mxc/dma-mx1-mx2.c
+++ b/arch/arm/plat-mxc/dma-mx1-mx2.c
@@ -156,7 +156,8 @@ static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
156 } 156 }
157 157
158 now = min(imxdma->resbytes, sg->length); 158 now = min(imxdma->resbytes, sg->length);
159 imxdma->resbytes -= now; 159 if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
160 imxdma->resbytes -= now;
160 161
161 if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ) 162 if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
162 __raw_writel(sg->dma_address, DMA_BASE + DMA_DAR(channel)); 163 __raw_writel(sg->dma_address, DMA_BASE + DMA_DAR(channel));
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index cfc4a8b43e6a..d65ebe303b9f 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -282,7 +282,7 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
282 for (j = port[i].virtual_irq_start; 282 for (j = port[i].virtual_irq_start;
283 j < port[i].virtual_irq_start + 32; j++) { 283 j < port[i].virtual_irq_start + 32; j++) {
284 set_irq_chip(j, &gpio_irq_chip); 284 set_irq_chip(j, &gpio_irq_chip);
285 set_irq_handler(j, handle_edge_irq); 285 set_irq_handler(j, handle_level_irq);
286 set_irq_flags(j, IRQF_VALID); 286 set_irq_flags(j, IRQF_VALID);
287 } 287 }
288 288
diff --git a/arch/arm/plat-mxc/include/mach/audmux.h b/arch/arm/plat-mxc/include/mach/audmux.h
new file mode 100644
index 000000000000..5cd6466964af
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/audmux.h
@@ -0,0 +1,52 @@
1#ifndef __MACH_AUDMUX_H
2#define __MACH_AUDMUX_H
3
4#define MX27_AUDMUX_HPCR1_SSI0 0
5#define MX27_AUDMUX_HPCR2_SSI1 1
6#define MX27_AUDMUX_HPCR3_SSI_PINS_4 2
7#define MX27_AUDMUX_PPCR1_SSI_PINS_1 3
8#define MX27_AUDMUX_PPCR2_SSI_PINS_2 4
9#define MX27_AUDMUX_PPCR3_SSI_PINS_3 5
10
11#define MX31_AUDMUX_PORT1_SSI0 0
12#define MX31_AUDMUX_PORT2_SSI1 1
13#define MX31_AUDMUX_PORT3_SSI_PINS_3 2
14#define MX31_AUDMUX_PORT4_SSI_PINS_4 3
15#define MX31_AUDMUX_PORT5_SSI_PINS_5 4
16#define MX31_AUDMUX_PORT6_SSI_PINS_6 5
17
18/* Register definitions for the i.MX21/27 Digital Audio Multiplexer */
19#define MXC_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff)
20#define MXC_AUDMUX_V1_PCR_INMEN (1 << 8)
21#define MXC_AUDMUX_V1_PCR_TXRXEN (1 << 10)
22#define MXC_AUDMUX_V1_PCR_SYN (1 << 12)
23#define MXC_AUDMUX_V1_PCR_RXDSEL(x) (((x) & 0x7) << 13)
24#define MXC_AUDMUX_V1_PCR_RFCSEL(x) (((x) & 0xf) << 20)
25#define MXC_AUDMUX_V1_PCR_RCLKDIR (1 << 24)
26#define MXC_AUDMUX_V1_PCR_RFSDIR (1 << 25)
27#define MXC_AUDMUX_V1_PCR_TFCSEL(x) (((x) & 0xf) << 26)
28#define MXC_AUDMUX_V1_PCR_TCLKDIR (1 << 30)
29#define MXC_AUDMUX_V1_PCR_TFSDIR (1 << 31)
30
31/* Register definitions for the i.MX25/31/35 Digital Audio Multiplexer */
32#define MXC_AUDMUX_V2_PTCR_TFSDIR (1 << 31)
33#define MXC_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27)
34#define MXC_AUDMUX_V2_PTCR_TCLKDIR (1 << 26)
35#define MXC_AUDMUX_V2_PTCR_TCSEL(x) (((x) & 0xf) << 22)
36#define MXC_AUDMUX_V2_PTCR_RFSDIR (1 << 21)
37#define MXC_AUDMUX_V2_PTCR_RFSEL(x) (((x) & 0xf) << 17)
38#define MXC_AUDMUX_V2_PTCR_RCLKDIR (1 << 16)
39#define MXC_AUDMUX_V2_PTCR_RCSEL(x) (((x) & 0xf) << 12)
40#define MXC_AUDMUX_V2_PTCR_SYN (1 << 11)
41
42#define MXC_AUDMUX_V2_PDCR_RXDSEL(x) (((x) & 0x7) << 13)
43#define MXC_AUDMUX_V2_PDCR_TXRXEN (1 << 12)
44#define MXC_AUDMUX_V2_PDCR_MODE(x) (((x) & 0x3) << 8)
45#define MXC_AUDMUX_V2_PDCR_INMMASK(x) ((x) & 0xff)
46
47int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr);
48
49int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
50 unsigned int pdcr);
51
52#endif /* __MACH_AUDMUX_H */
diff --git a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
new file mode 100644
index 000000000000..05ff2f31ef1f
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
@@ -0,0 +1,39 @@
1/*
2 * Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18#ifndef __ARM_ARCH_BOARD_KZM_ARM11_H
19#define __ARM_ARCH_BOARD_KZM_ARM11_H
20
21/*
22 * KZM-ARM11-01 Board Control Registers on FPGA
23 */
24#define KZM_ARM11_CTL1 (CS4_BASE_ADDR + 0x1000)
25#define KZM_ARM11_CTL2 (CS4_BASE_ADDR + 0x1001)
26#define KZM_ARM11_RSW1 (CS4_BASE_ADDR + 0x1002)
27#define KZM_ARM11_BACK_LIGHT (CS4_BASE_ADDR + 0x1004)
28#define KZM_ARM11_FPGA_REV (CS4_BASE_ADDR + 0x1008)
29#define KZM_ARM11_7SEG_LED (CS4_BASE_ADDR + 0x1010)
30#define KZM_ARM11_LEDS (CS4_BASE_ADDR + 0x1020)
31#define KZM_ARM11_DIPSW2 (CS4_BASE_ADDR + 0x1003)
32
33/*
34 * External UART for touch panel on FPGA
35 */
36#define KZM_ARM11_16550 (CS4_BASE_ADDR + 0x1050)
37
38#endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */
39
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
index 8e64325d6905..0184b638c268 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
@@ -1,15 +1,42 @@
1/* 1/*
2 * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
4 *
5 * Based on code for mobots boards,
6 * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
3 */ 21 */
4 22
23#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
24#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
25
26#ifndef __ASSEMBLY__
27
28enum mx31lilly_boards {
29 MX31LITE_NOBOARD = 0,
30 MX31LITE_DB = 1,
31};
32
5/* 33/*
6 * This program is free software; you can redistribute it and/or modify 34 * This CPU module needs a baseboard to work. After basic initializing
7 * it under the terms of the GNU General Public License version 2 as 35 * its own devices, it calls baseboard's init function.
8 * published by the Free Software Foundation.
9 */ 36 */
10 37
11#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__ 38extern void mx31lite_db_init(void);
12#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
13 39
14#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */ 40#endif
15 41
42#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
index b3876cc238ca..07be8ad7ec37 100644
--- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
+++ b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
@@ -58,6 +58,14 @@ imx_dma_setup_single(int channel, dma_addr_t dma_address,
58 unsigned int dma_length, unsigned int dev_addr, 58 unsigned int dma_length, unsigned int dev_addr,
59 unsigned int dmamode); 59 unsigned int dmamode);
60 60
61
62/*
63 * Use this flag as the dma_length argument to imx_dma_setup_sg()
64 * to create an endless running dma loop. The end of the scatterlist
65 * must be linked to the beginning for this to work.
66 */
67#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
68
61int 69int
62imx_dma_setup_sg(int channel, struct scatterlist *sg, 70imx_dma_setup_sg(int channel, struct scatterlist *sg,
63 unsigned int sgcount, unsigned int dma_length, 71 unsigned int sgcount, unsigned int dma_length,
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index 446f86763816..eaabd4e96925 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -524,10 +524,18 @@ enum iomux_pins {
524#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC) 524#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
525#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC) 525#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
526#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC) 526#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
527#define MX31_PIN_DCD_DCE1__DCD_DCE1 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC)
528#define MX31_PIN_RI_DCE1__RI_DCE1 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC)
529#define MX31_PIN_DSR_DCE1__DSR_DCE1 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC)
530#define MX31_PIN_DTR_DCE1__DTR_DCE1 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC)
527#define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC) 531#define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC)
528#define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC) 532#define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC)
529#define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC) 533#define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC)
530#define MX31_PIN_RXD2__RXD2 IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC) 534#define MX31_PIN_RXD2__RXD2 IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC)
535#define MX31_PIN_DCD_DTE1__DCD_DTE2 IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT1)
536#define MX31_PIN_RI_DTE1__RI_DTE2 IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT1)
537#define MX31_PIN_DSR_DTE1__DSR_DTE2 IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_ALT1)
538#define MX31_PIN_DTR_DTE1__DTR_DTE2 IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE)
531#define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2) 539#define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2)
532#define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2) 540#define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2)
533#define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2) 541#define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2)
@@ -623,6 +631,8 @@ enum iomux_pins {
623#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO) 631#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO)
624#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) 632#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)
625#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) 633#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
634#define MX31_PIN_CSI_D4__GPIO3_4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO)
635#define MX31_PIN_CSI_D5__GPIO3_5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO)
626#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC) 636#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC)
627#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC) 637#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC)
628#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC) 638#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC)
@@ -642,12 +652,22 @@ enum iomux_pins {
642#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1) 652#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1)
643#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1) 653#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1)
644#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1) 654#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1)
655#define MX31_PIN_SFS6__USBH1_SUSPEND IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC)
656#define MX31_PIN_NFRE_B__GPIO1_11 IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO)
657#define MX31_PIN_NFALE__GPIO1_12 IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO)
645#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC) 658#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)
646#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC) 659#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)
660#define MX31_PIN_STXD3__USBH2_DATA2 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC)
661#define MX31_PIN_SRXD3__USBH2_DATA3 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC)
662#define MX31_PIN_SCK3__USBH2_DATA4 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC)
663#define MX31_PIN_SFS3__USBH2_DATA5 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC)
664#define MX31_PIN_STXD6__USBH2_DATA6 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC)
665#define MX31_PIN_SRXD6__USBH2_DATA7 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC)
647#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC) 666#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)
648#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC) 667#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)
649#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC) 668#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)
650#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC) 669#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)
670#define MX31_PIN_SCK6__GPIO1_25 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO)
651#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO) 671#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO)
652#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) 672#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
653#define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC) 673#define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
@@ -693,7 +713,19 @@ enum iomux_pins {
693#define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO) 713#define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO)
694#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO) 714#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO)
695#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO) 715#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO)
696 716#define MX31_PIN_GPIO1_3__GPIO1_3 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO)
717#define MX31_PIN_CSPI2_SS1__CSPI3_SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1)
718#define MX31_PIN_RTS1__GPIO2_6 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO)
719#define MX31_PIN_CTS1__GPIO2_7 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO)
720#define MX31_PIN_LCS0__GPIO3_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO)
721#define MX31_PIN_STXD4__STXD4 IOMUX_MODE(MX31_PIN_STXD4, IOMUX_CONFIG_FUNC)
722#define MX31_PIN_SRXD4__SRXD4 IOMUX_MODE(MX31_PIN_SRXD4, IOMUX_CONFIG_FUNC)
723#define MX31_PIN_SCK4__SCK4 IOMUX_MODE(MX31_PIN_SCK4, IOMUX_CONFIG_FUNC)
724#define MX31_PIN_SFS4__SFS4 IOMUX_MODE(MX31_PIN_SFS4, IOMUX_CONFIG_FUNC)
725#define MX31_PIN_STXD5__STXD5 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_FUNC)
726#define MX31_PIN_SRXD5__SRXD5 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC)
727#define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC)
728#define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC)
697 729
698/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 730/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0
699 * cspi1_ss1*/ 731 * cspi1_ss1*/
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index a0fa40265468..1deda0184892 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -88,9 +88,7 @@ struct pad_desc {
88#define PAD_CTL_SRE_FAST (1 << 0) 88#define PAD_CTL_SRE_FAST (1 << 0)
89 89
90/* 90/*
91 * setups a single pad: 91 * setups a single pad in the iomuxer
92 * - reserves the pad so that it is not claimed by another driver
93 * - setups the iomux according to the configuration
94 */ 92 */
95int mxc_iomux_v3_setup_pad(struct pad_desc *pad); 93int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
96 94
@@ -101,19 +99,6 @@ int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
101int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count); 99int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count);
102 100
103/* 101/*
104 * releases a single pad:
105 * - make it available for a future use by another driver
106 * - DOES NOT reconfigure the IOMUX in its reset state
107 */
108void mxc_iomux_v3_release_pad(struct pad_desc *pad);
109
110/*
111 * releases multiple pads
112 * convenvient way to call the above function with tables
113 */
114void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count);
115
116/*
117 * Initialise the iomux controller 102 * Initialise the iomux controller
118 */ 103 */
119void mxc_iomux_v3_init(void __iomem *iomux_v3_base); 104void mxc_iomux_v3_init(void __iomem *iomux_v3_base);
diff --git a/arch/arm/plat-mxc/include/mach/iomux.h b/arch/arm/plat-mxc/include/mach/iomux.h
index 6d49f8ae3259..011cfcd8b820 100644
--- a/arch/arm/plat-mxc/include/mach/iomux.h
+++ b/arch/arm/plat-mxc/include/mach/iomux.h
@@ -123,6 +123,7 @@
123#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) 123#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
124#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) 124#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
125#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x) 125#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x)
126#define IRQ_GPIOF(x) (IRQ_GPIOE(32) + x)
126 127
127 128
128extern void mxc_gpio_mode(int gpio_mode); 129extern void mxc_gpio_mode(int gpio_mode);
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index 21112c695ec5..bb297d8765a7 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -25,46 +25,191 @@
25#ifndef __ASM_ARCH_MXC_MX21_H__ 25#ifndef __ASM_ARCH_MXC_MX21_H__
26#define __ASM_ARCH_MXC_MX21_H__ 26#define __ASM_ARCH_MXC_MX21_H__
27 27
28#define MX21_AIPI_BASE_ADDR 0x10000000
29#define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000
30#define MX21_AIPI_SIZE SZ_1M
31#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000)
32#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000)
33#define MX21_GPT1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x03000)
34#define MX21_GPT2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x04000)
35#define MX21_GPT3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x05000)
36#define MX21_PWM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x06000)
37#define MX21_RTC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x07000)
38#define MX21_KPP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x08000)
39#define MX21_OWIRE_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x09000)
40#define MX21_UART1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0a000)
41#define MX21_UART2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0b000)
42#define MX21_UART3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0c000)
43#define MX21_UART4_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0d000)
44#define MX21_CSPI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0e000)
45#define MX21_CSPI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0f000)
46#define MX21_SSI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x10000)
47#define MX21_SSI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x11000)
48#define MX21_I2C_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x12000)
49#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000)
50#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000)
51#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000)
52#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000)
53#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000)
54#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000)
55#define MX21_SLCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x22000)
56#define MX21_USBOTG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x24000)
57#define MX21_EMMA_PP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26000)
58#define MX21_EMMA_PRP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26400)
59#define MX21_CCM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27000)
60#define MX21_SYSCTRL_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27800)
61#define MX21_JAM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3e000)
62#define MX21_MAX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3f000)
63
64#define MX21_AVIC_BASE_ADDR 0x10040000
65
66#define MX21_SAHB1_BASE_ADDR 0x80000000
67#define MX21_SAHB1_BASE_ADDR_VIRT 0xf4100000
68#define MX21_SAHB1_SIZE SZ_1M
69#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
70
28/* Memory regions and CS */ 71/* Memory regions and CS */
29#define SDRAM_BASE_ADDR 0xC0000000 72#define MX21_SDRAM_BASE_ADDR 0xc0000000
30#define CSD1_BASE_ADDR 0xC4000000 73#define MX21_CSD1_BASE_ADDR 0xc4000000
31 74
32#define CS0_BASE_ADDR 0xC8000000 75#define MX21_CS0_BASE_ADDR 0xc8000000
33#define CS1_BASE_ADDR 0xCC000000 76#define MX21_CS1_BASE_ADDR 0xcc000000
34#define CS2_BASE_ADDR 0xD0000000 77#define MX21_CS2_BASE_ADDR 0xd0000000
35#define CS3_BASE_ADDR 0xD1000000 78#define MX21_CS3_BASE_ADDR 0xd1000000
36#define CS4_BASE_ADDR 0xD2000000 79#define MX21_CS4_BASE_ADDR 0xd2000000
37#define CS5_BASE_ADDR 0xDD000000 80#define MX21_PCMCIA_MEM_BASE_ADDR 0xd4000000
38#define PCMCIA_MEM_BASE_ADDR 0xD4000000 81#define MX21_CS5_BASE_ADDR 0xdd000000
39 82
40/* NAND, SDRAM, WEIM etc controllers */ 83/* NAND, SDRAM, WEIM etc controllers */
41#define X_MEMC_BASE_ADDR 0xDF000000 84#define MX21_X_MEMC_BASE_ADDR 0xdf000000
42#define X_MEMC_BASE_ADDR_VIRT 0xF4200000 85#define MX21_X_MEMC_BASE_ADDR_VIRT 0xf4200000
43#define X_MEMC_SIZE SZ_256K 86#define MX21_X_MEMC_SIZE SZ_256K
44 87
45#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000) 88#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000)
46#define EIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) 89#define MX21_EIM_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x1000)
47#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) 90#define MX21_PCMCIA_CTL_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x2000)
48#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) 91#define MX21_NFC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x3000)
49 92
50#define IRAM_BASE_ADDR 0xFFFFE800 /* internal ram */ 93#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
51 94
52/* fixed interrupt numbers */ 95/* fixed interrupt numbers */
53#define MXC_INT_USBCTRL 58 96#define MX21_INT_CSPI3 6
54#define MXC_INT_USBCTRL 58 97#define MX21_INT_GPIO 8
55#define MXC_INT_USBMNP 57 98#define MX21_INT_FIRI 9
56#define MXC_INT_USBFUNC 56 99#define MX21_INT_SDHC2 10
57#define MXC_INT_USBHOST 55 100#define MX21_INT_SDHC1 11
58#define MXC_INT_USBDMA 54 101#define MX21_INT_I2C 12
59#define MXC_INT_USBWKUP 53 102#define MX21_INT_SSI2 13
60#define MXC_INT_EMMADEC 50 103#define MX21_INT_SSI1 14
61#define MXC_INT_EMMAENC 49 104#define MX21_INT_CSPI2 15
62#define MXC_INT_BMI 30 105#define MX21_INT_CSPI1 16
63#define MXC_INT_FIRI 9 106#define MX21_INT_UART4 17
107#define MX21_INT_UART3 18
108#define MX21_INT_UART2 19
109#define MX21_INT_UART1 20
110#define MX21_INT_KPP 21
111#define MX21_INT_RTC 22
112#define MX21_INT_PWM 23
113#define MX21_INT_GPT3 24
114#define MX21_INT_GPT2 25
115#define MX21_INT_GPT1 26
116#define MX21_INT_WDOG 27
117#define MX21_INT_PCMCIA 28
118#define MX21_INT_NANDFC 29
119#define MX21_INT_BMI 30
120#define MX21_INT_CSI 31
121#define MX21_INT_DMACH0 32
122#define MX21_INT_DMACH1 33
123#define MX21_INT_DMACH2 34
124#define MX21_INT_DMACH3 35
125#define MX21_INT_DMACH4 36
126#define MX21_INT_DMACH5 37
127#define MX21_INT_DMACH6 38
128#define MX21_INT_DMACH7 39
129#define MX21_INT_DMACH8 40
130#define MX21_INT_DMACH9 41
131#define MX21_INT_DMACH10 42
132#define MX21_INT_DMACH11 43
133#define MX21_INT_DMACH12 44
134#define MX21_INT_DMACH13 45
135#define MX21_INT_DMACH14 46
136#define MX21_INT_DMACH15 47
137#define MX21_INT_EMMAENC 49
138#define MX21_INT_EMMADEC 50
139#define MX21_INT_EMMAPRP 51
140#define MX21_INT_EMMAPP 52
141#define MX21_INT_USBWKUP 53
142#define MX21_INT_USBDMA 54
143#define MX21_INT_USBHOST 55
144#define MX21_INT_USBFUNC 56
145#define MX21_INT_USBMNP 57
146#define MX21_INT_USBCTRL 58
147#define MX21_INT_SLCDC 60
148#define MX21_INT_LCDC 61
64 149
65/* fixed DMA request numbers */ 150/* fixed DMA request numbers */
66#define DMA_REQ_BMI_RX 29 151#define MX21_DMA_REQ_CSPI3_RX 1
67#define DMA_REQ_BMI_TX 28 152#define MX21_DMA_REQ_CSPI3_TX 2
68#define DMA_REQ_FIRI_RX 4 153#define MX21_DMA_REQ_EXT 3
154#define MX21_DMA_REQ_FIRI_RX 4
155#define MX21_DMA_REQ_SDHC2 6
156#define MX21_DMA_REQ_SDHC1 7
157#define MX21_DMA_REQ_SSI2_RX0 8
158#define MX21_DMA_REQ_SSI2_TX0 9
159#define MX21_DMA_REQ_SSI2_RX1 10
160#define MX21_DMA_REQ_SSI2_TX1 11
161#define MX21_DMA_REQ_SSI1_RX0 12
162#define MX21_DMA_REQ_SSI1_TX0 13
163#define MX21_DMA_REQ_SSI1_RX1 14
164#define MX21_DMA_REQ_SSI1_TX1 15
165#define MX21_DMA_REQ_CSPI2_RX 16
166#define MX21_DMA_REQ_CSPI2_TX 17
167#define MX21_DMA_REQ_CSPI1_RX 18
168#define MX21_DMA_REQ_CSPI1_TX 19
169#define MX21_DMA_REQ_UART4_RX 20
170#define MX21_DMA_REQ_UART4_TX 21
171#define MX21_DMA_REQ_UART3_RX 22
172#define MX21_DMA_REQ_UART3_TX 23
173#define MX21_DMA_REQ_UART2_RX 24
174#define MX21_DMA_REQ_UART2_TX 25
175#define MX21_DMA_REQ_UART1_RX 26
176#define MX21_DMA_REQ_UART1_TX 27
177#define MX21_DMA_REQ_BMI_TX 28
178#define MX21_DMA_REQ_BMI_RX 29
179#define MX21_DMA_REQ_CSI_STAT 30
180#define MX21_DMA_REQ_CSI_RX 31
181
182/* these should go away */
183#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR
184#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR
185#define CS0_BASE_ADDR MX21_CS0_BASE_ADDR
186#define CS1_BASE_ADDR MX21_CS1_BASE_ADDR
187#define CS2_BASE_ADDR MX21_CS2_BASE_ADDR
188#define CS3_BASE_ADDR MX21_CS3_BASE_ADDR
189#define CS4_BASE_ADDR MX21_CS4_BASE_ADDR
190#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR
191#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR
192#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR
193#define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT
194#define X_MEMC_SIZE MX21_X_MEMC_SIZE
195#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR
196#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR
197#define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR
198#define NFC_BASE_ADDR MX21_NFC_BASE_ADDR
199#define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR
200#define MXC_INT_FIRI MX21_INT_FIRI
201#define MXC_INT_BMI MX21_INT_BMI
202#define MXC_INT_EMMAENC MX21_INT_EMMAENC
203#define MXC_INT_EMMADEC MX21_INT_EMMADEC
204#define MXC_INT_USBWKUP MX21_INT_USBWKUP
205#define MXC_INT_USBDMA MX21_INT_USBDMA
206#define MXC_INT_USBHOST MX21_INT_USBHOST
207#define MXC_INT_USBFUNC MX21_INT_USBFUNC
208#define MXC_INT_USBMNP MX21_INT_USBMNP
209#define MXC_INT_USBCTRL MX21_INT_USBCTRL
210#define MXC_INT_USBCTRL MX21_INT_USBCTRL
211#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX
212#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX
213#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX
69 214
70#endif /* __ASM_ARCH_MXC_MX21_H__ */ 215#endif /* __ASM_ARCH_MXC_MX21_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index ec64bd9a8ab1..91e738144804 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -1,14 +1,14 @@
1#ifndef __MACH_MX25_H__ 1#ifndef __MACH_MX25_H__
2#define __MACH_MX25_H__ 2#define __MACH_MX25_H__
3 3
4#define MX25_AIPS1_BASE_ADDR 0x43F00000 4#define MX25_AIPS1_BASE_ADDR 0x43f00000
5#define MX25_AIPS1_BASE_ADDR_VIRT 0xFC000000 5#define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000
6#define MX25_AIPS1_SIZE SZ_1M 6#define MX25_AIPS1_SIZE SZ_1M
7#define MX25_AIPS2_BASE_ADDR 0x53F00000 7#define MX25_AIPS2_BASE_ADDR 0x53f00000
8#define MX25_AIPS2_BASE_ADDR_VIRT 0xFC200000 8#define MX25_AIPS2_BASE_ADDR_VIRT 0xfc200000
9#define MX25_AIPS2_SIZE SZ_1M 9#define MX25_AIPS2_SIZE SZ_1M
10#define MX25_AVIC_BASE_ADDR 0x68000000 10#define MX25_AVIC_BASE_ADDR 0x68000000
11#define MX25_AVIC_BASE_ADDR_VIRT 0xFC400000 11#define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000
12#define MX25_AVIC_SIZE SZ_1M 12#define MX25_AVIC_SIZE SZ_1M
13 13
14#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) 14#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index dc3ad9aa952a..e2ae19f51710 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -24,87 +24,198 @@
24#ifndef __ASM_ARCH_MXC_MX27_H__ 24#ifndef __ASM_ARCH_MXC_MX27_H__
25#define __ASM_ARCH_MXC_MX27_H__ 25#define __ASM_ARCH_MXC_MX27_H__
26 26
27/* IRAM */ 27#define MX27_AIPI_BASE_ADDR 0x10000000
28#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */ 28#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000
29 29#define MX27_AIPI_SIZE SZ_1M
30#define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000) 30#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000)
31#define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000) 31#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000)
32#define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000) 32#define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000)
33#define UART5_BASE_ADDR (AIPI_BASE_ADDR + 0x1B000) 33#define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000)
34#define UART6_BASE_ADDR (AIPI_BASE_ADDR + 0x1C000) 34#define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000)
35#define I2C2_BASE_ADDR (AIPI_BASE_ADDR + 0x1D000) 35#define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000)
36#define SDHC3_BASE_ADDR (AIPI_BASE_ADDR + 0x1E000) 36#define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000)
37#define GPT6_BASE_ADDR (AIPI_BASE_ADDR + 0x1F000) 37#define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000)
38#define VPU_BASE_ADDR (AIPI_BASE_ADDR + 0x23000) 38#define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000)
39#define OTG_BASE_ADDR USBOTG_BASE_ADDR 39#define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000)
40#define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000) 40#define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000)
41#define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000) 41#define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000)
42#define RTIC_BASE_ADDR (AIPI_BASE_ADDR + 0x2A000) 42#define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000)
43#define FEC_BASE_ADDR (AIPI_BASE_ADDR + 0x2B000) 43#define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000)
44#define SCC_BASE_ADDR (AIPI_BASE_ADDR + 0x2C000) 44#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000)
45#define ETB_BASE_ADDR (AIPI_BASE_ADDR + 0x3B000) 45#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000)
46#define ETB_RAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3C000) 46#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000)
47#define MX27_I2C_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000)
48#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000)
49#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000)
50#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000)
51#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000)
52#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000)
53#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000)
54#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000)
55#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000)
56#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000)
57#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000)
58#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000)
59#define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000)
60#define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000)
61#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000)
62#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000)
63#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000)
64#define MX27_USBOTG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000)
65#define MX27_OTG_BASE_ADDR MX27_USBOTG_BASE_ADDR
66#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000)
67#define MX27_EMMA_PP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000)
68#define MX27_EMMA_PRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400)
69#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000)
70#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800)
71#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000)
72#define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000)
73#define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000)
74#define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000)
75#define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000)
76#define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000)
77#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000)
78#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000)
79
80#define MX27_AVIC_BASE_ADDR 0x10040000
47 81
48/* ROM patch */ 82/* ROM patch */
49#define ROMP_BASE_ADDR 0x10041000 83#define MX27_ROMP_BASE_ADDR 0x10041000
50 84
51#define ATA_BASE_ADDR (SAHB1_BASE_ADDR + 0x1000) 85#define MX27_SAHB1_BASE_ADDR 0x80000000
86#define MX27_SAHB1_BASE_ADDR_VIRT 0xf4100000
87#define MX27_SAHB1_SIZE SZ_1M
88#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000)
89#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000)
52 90
53/* Memory regions and CS */ 91/* Memory regions and CS */
54#define SDRAM_BASE_ADDR 0xA0000000 92#define MX27_SDRAM_BASE_ADDR 0xa0000000
55#define CSD1_BASE_ADDR 0xB0000000 93#define MX27_CSD1_BASE_ADDR 0xb0000000
56 94
57#define CS0_BASE_ADDR 0xC0000000 95#define MX27_CS0_BASE_ADDR 0xc0000000
58#define CS1_BASE_ADDR 0xC8000000 96#define MX27_CS1_BASE_ADDR 0xc8000000
59#define CS2_BASE_ADDR 0xD0000000 97#define MX27_CS2_BASE_ADDR 0xd0000000
60#define CS3_BASE_ADDR 0xD2000000 98#define MX27_CS3_BASE_ADDR 0xd2000000
61#define CS4_BASE_ADDR 0xD4000000 99#define MX27_CS4_BASE_ADDR 0xd4000000
62#define CS5_BASE_ADDR 0xD6000000 100#define MX27_CS5_BASE_ADDR 0xd6000000
63#define PCMCIA_MEM_BASE_ADDR 0xDC000000
64 101
65/* NAND, SDRAM, WEIM, M3IF, EMI controllers */ 102/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
66#define X_MEMC_BASE_ADDR 0xD8000000 103#define MX27_X_MEMC_BASE_ADDR 0xd8000000
67#define X_MEMC_BASE_ADDR_VIRT 0xF4200000 104#define MX27_X_MEMC_BASE_ADDR_VIRT 0xf4200000
68#define X_MEMC_SIZE SZ_1M 105#define MX27_X_MEMC_SIZE SZ_1M
106#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
107#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
108#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000)
109#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
110#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
69 111
70#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR) 112#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
71#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) 113
72#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) 114/* IRAM */
73#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) 115#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
74#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
75 116
76/* fixed interrupt numbers */ 117/* fixed interrupt numbers */
77#define MXC_INT_CCM 63 118#define MX27_INT_I2C2 1
78#define MXC_INT_IIM 62 119#define MX27_INT_GPT6 2
79#define MXC_INT_SAHARA 59 120#define MX27_INT_GPT5 3
80#define MXC_INT_SCC_SCM 58 121#define MX27_INT_GPT4 4
81#define MXC_INT_SCC_SMN 57 122#define MX27_INT_RTIC 5
82#define MXC_INT_USB3 56 123#define MX27_INT_CSPI3 6
83#define MXC_INT_USB2 55 124#define MX27_INT_SDHC 7
84#define MXC_INT_USB1 54 125#define MX27_INT_GPIO 8
85#define MXC_INT_VPU 53 126#define MX27_INT_SDHC3 9
86#define MXC_INT_FEC 50 127#define MX27_INT_SDHC2 10
87#define MXC_INT_UART5 49 128#define MX27_INT_SDHC1 11
88#define MXC_INT_UART6 48 129#define MX27_INT_I2C 12
89#define MXC_INT_ATA 30 130#define MX27_INT_SSI2 13
90#define MXC_INT_SDHC3 9 131#define MX27_INT_SSI1 14
91#define MXC_INT_SDHC 7 132#define MX27_INT_CSPI2 15
92#define MXC_INT_RTIC 5 133#define MX27_INT_CSPI1 16
93#define MXC_INT_GPT4 4 134#define MX27_INT_UART4 17
94#define MXC_INT_GPT5 3 135#define MX27_INT_UART3 18
95#define MXC_INT_GPT6 2 136#define MX27_INT_UART2 19
96#define MXC_INT_I2C2 1 137#define MX27_INT_UART1 20
138#define MX27_INT_KPP 21
139#define MX27_INT_RTC 22
140#define MX27_INT_PWM 23
141#define MX27_INT_GPT3 24
142#define MX27_INT_GPT2 25
143#define MX27_INT_GPT1 26
144#define MX27_INT_WDOG 27
145#define MX27_INT_PCMCIA 28
146#define MX27_INT_NANDFC 29
147#define MX27_INT_ATA 30
148#define MX27_INT_CSI 31
149#define MX27_INT_DMACH0 32
150#define MX27_INT_DMACH1 33
151#define MX27_INT_DMACH2 34
152#define MX27_INT_DMACH3 35
153#define MX27_INT_DMACH4 36
154#define MX27_INT_DMACH5 37
155#define MX27_INT_DMACH6 38
156#define MX27_INT_DMACH7 39
157#define MX27_INT_DMACH8 40
158#define MX27_INT_DMACH9 41
159#define MX27_INT_DMACH10 42
160#define MX27_INT_DMACH11 43
161#define MX27_INT_DMACH12 44
162#define MX27_INT_DMACH13 45
163#define MX27_INT_DMACH14 46
164#define MX27_INT_DMACH15 47
165#define MX27_INT_UART6 48
166#define MX27_INT_UART5 49
167#define MX27_INT_FEC 50
168#define MX27_INT_EMMAPRP 51
169#define MX27_INT_EMMAPP 52
170#define MX27_INT_VPU 53
171#define MX27_INT_USB1 54
172#define MX27_INT_USB2 55
173#define MX27_INT_USB3 56
174#define MX27_INT_SCC_SMN 57
175#define MX27_INT_SCC_SCM 58
176#define MX27_INT_SAHARA 59
177#define MX27_INT_SLCDC 60
178#define MX27_INT_LCDC 61
179#define MX27_INT_IIM 62
180#define MX27_INT_CCM 63
97 181
98/* fixed DMA request numbers */ 182/* fixed DMA request numbers */
99#define DMA_REQ_NFC 37 183#define MX27_DMA_REQ_CSPI3_RX 1
100#define DMA_REQ_SDHC3 36 184#define MX27_DMA_REQ_CSPI3_TX 2
101#define DMA_REQ_UART6_RX 35 185#define MX27_DMA_REQ_EXT 3
102#define DMA_REQ_UART6_TX 34 186#define MX27_DMA_REQ_MSHC 4
103#define DMA_REQ_UART5_RX 33 187#define MX27_DMA_REQ_SDHC2 6
104#define DMA_REQ_UART5_TX 32 188#define MX27_DMA_REQ_SDHC1 7
105#define DMA_REQ_ATA_RCV 29 189#define MX27_DMA_REQ_SSI2_RX0 8
106#define DMA_REQ_ATA_TX 28 190#define MX27_DMA_REQ_SSI2_TX0 9
107#define DMA_REQ_MSHC 4 191#define MX27_DMA_REQ_SSI2_RX1 10
192#define MX27_DMA_REQ_SSI2_TX1 11
193#define MX27_DMA_REQ_SSI1_RX0 12
194#define MX27_DMA_REQ_SSI1_TX0 13
195#define MX27_DMA_REQ_SSI1_RX1 14
196#define MX27_DMA_REQ_SSI1_TX1 15
197#define MX27_DMA_REQ_CSPI2_RX 16
198#define MX27_DMA_REQ_CSPI2_TX 17
199#define MX27_DMA_REQ_CSPI1_RX 18
200#define MX27_DMA_REQ_CSPI1_TX 19
201#define MX27_DMA_REQ_UART4_RX 20
202#define MX27_DMA_REQ_UART4_TX 21
203#define MX27_DMA_REQ_UART3_RX 22
204#define MX27_DMA_REQ_UART3_TX 23
205#define MX27_DMA_REQ_UART2_RX 24
206#define MX27_DMA_REQ_UART2_TX 25
207#define MX27_DMA_REQ_UART1_RX 26
208#define MX27_DMA_REQ_UART1_TX 27
209#define MX27_DMA_REQ_ATA_TX 28
210#define MX27_DMA_REQ_ATA_RCV 29
211#define MX27_DMA_REQ_CSI_STAT 30
212#define MX27_DMA_REQ_CSI_RX 31
213#define MX27_DMA_REQ_UART5_TX 32
214#define MX27_DMA_REQ_UART5_RX 33
215#define MX27_DMA_REQ_UART6_TX 34
216#define MX27_DMA_REQ_UART6_RX 35
217#define MX27_DMA_REQ_SDHC3 36
218#define MX27_DMA_REQ_NFC 37
108 219
109/* silicon revisions specific to i.MX27 */ 220/* silicon revisions specific to i.MX27 */
110#define CHIP_REV_1_0 0x00 221#define CHIP_REV_1_0 0x00
@@ -114,6 +225,72 @@
114extern int mx27_revision(void); 225extern int mx27_revision(void);
115#endif 226#endif
116 227
117/* Mandatory defines used globally */ 228/* these should go away */
229#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR
230#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR
231#define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR
232#define UART5_BASE_ADDR MX27_UART5_BASE_ADDR
233#define UART6_BASE_ADDR MX27_UART6_BASE_ADDR
234#define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR
235#define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR
236#define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR
237#define VPU_BASE_ADDR MX27_VPU_BASE_ADDR
238#define OTG_BASE_ADDR MX27_OTG_BASE_ADDR
239#define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR
240#define IIM_BASE_ADDR MX27_IIM_BASE_ADDR
241#define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR
242#define FEC_BASE_ADDR MX27_FEC_BASE_ADDR
243#define SCC_BASE_ADDR MX27_SCC_BASE_ADDR
244#define ETB_BASE_ADDR MX27_ETB_BASE_ADDR
245#define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR
246#define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR
247#define ATA_BASE_ADDR MX27_ATA_BASE_ADDR
248#define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR
249#define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR
250#define CS0_BASE_ADDR MX27_CS0_BASE_ADDR
251#define CS1_BASE_ADDR MX27_CS1_BASE_ADDR
252#define CS2_BASE_ADDR MX27_CS2_BASE_ADDR
253#define CS3_BASE_ADDR MX27_CS3_BASE_ADDR
254#define CS4_BASE_ADDR MX27_CS4_BASE_ADDR
255#define CS5_BASE_ADDR MX27_CS5_BASE_ADDR
256#define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR
257#define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT
258#define X_MEMC_SIZE MX27_X_MEMC_SIZE
259#define NFC_BASE_ADDR MX27_NFC_BASE_ADDR
260#define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR
261#define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR
262#define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR
263#define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR
264#define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR
265#define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR
266#define MXC_INT_I2C2 MX27_INT_I2C2
267#define MXC_INT_GPT6 MX27_INT_GPT6
268#define MXC_INT_GPT5 MX27_INT_GPT5
269#define MXC_INT_GPT4 MX27_INT_GPT4
270#define MXC_INT_RTIC MX27_INT_RTIC
271#define MXC_INT_SDHC MX27_INT_SDHC
272#define MXC_INT_SDHC3 MX27_INT_SDHC3
273#define MXC_INT_ATA MX27_INT_ATA
274#define MXC_INT_UART6 MX27_INT_UART6
275#define MXC_INT_UART5 MX27_INT_UART5
276#define MXC_INT_FEC MX27_INT_FEC
277#define MXC_INT_VPU MX27_INT_VPU
278#define MXC_INT_USB1 MX27_INT_USB1
279#define MXC_INT_USB2 MX27_INT_USB2
280#define MXC_INT_USB3 MX27_INT_USB3
281#define MXC_INT_SCC_SMN MX27_INT_SCC_SMN
282#define MXC_INT_SCC_SCM MX27_INT_SCC_SCM
283#define MXC_INT_SAHARA MX27_INT_SAHARA
284#define MXC_INT_IIM MX27_INT_IIM
285#define MXC_INT_CCM MX27_INT_CCM
286#define DMA_REQ_MSHC MX27_DMA_REQ_MSHC
287#define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX
288#define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV
289#define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX
290#define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX
291#define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX
292#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX
293#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3
294#define DMA_REQ_NFC MX27_DMA_REQ_NFC
118 295
119#endif /* __ASM_ARCH_MXC_MX27_H__ */ 296#endif /* __ASM_ARCH_MXC_MX27_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
index db5d921e0fe6..f2eaf140ed02 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -25,51 +25,49 @@
25 25
26/* The following addresses are common between i.MX21 and i.MX27 */ 26/* The following addresses are common between i.MX21 and i.MX27 */
27 27
28/* Register offests */ 28/* Register offsets */
29#define AIPI_BASE_ADDR 0x10000000 29#define MX2x_AIPI_BASE_ADDR 0x10000000
30#define AIPI_BASE_ADDR_VIRT 0xF4000000 30#define MX2x_AIPI_BASE_ADDR_VIRT 0xf4000000
31#define AIPI_SIZE SZ_1M 31#define MX2x_AIPI_SIZE SZ_1M
32 32#define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
33#define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000) 33#define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
34#define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000) 34#define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
35#define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000) 35#define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
36#define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000) 36#define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
37#define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000) 37#define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
38#define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000) 38#define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
39#define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000) 39#define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
40#define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000) 40#define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
41#define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000) 41#define MX2x_UART1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0a000)
42#define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000) 42#define MX2x_UART2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0b000)
43#define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000) 43#define MX2x_UART3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0c000)
44#define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000) 44#define MX2x_UART4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0d000)
45#define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000) 45#define MX2x_CSPI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0e000)
46#define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000) 46#define MX2x_CSPI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0f000)
47#define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000) 47#define MX2x_SSI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x10000)
48#define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000) 48#define MX2x_SSI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x11000)
49#define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000) 49#define MX2x_I2C_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x12000)
50#define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000) 50#define MX2x_SDHC1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x13000)
51#define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000) 51#define MX2x_SDHC2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x14000)
52#define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000) 52#define MX2x_GPIO_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x15000)
53#define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000) 53#define MX2x_AUDMUX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x16000)
54#define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000) 54#define MX2x_CSPI3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x17000)
55#define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000) 55#define MX2x_LCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x21000)
56#define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000) 56#define MX2x_SLCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x22000)
57#define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000) 57#define MX2x_USBOTG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x24000)
58#define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000) 58#define MX2x_EMMA_PP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26000)
59#define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000) 59#define MX2x_EMMA_PRP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26400)
60#define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400) 60#define MX2x_CCM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27000)
61#define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000) 61#define MX2x_SYSCTRL_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27800)
62#define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800) 62#define MX2x_JAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3e000)
63#define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000) 63#define MX2x_MAX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3f000)
64#define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000) 64
65 65#define MX2x_AVIC_BASE_ADDR 0x10040000
66#define AVIC_BASE_ADDR 0x10040000 66
67 67#define MX2x_SAHB1_BASE_ADDR 0x80000000
68#define SAHB1_BASE_ADDR 0x80000000 68#define MX2x_SAHB1_BASE_ADDR_VIRT 0xf4100000
69#define SAHB1_BASE_ADDR_VIRT 0xF4100000 69#define MX2x_SAHB1_SIZE SZ_1M
70#define SAHB1_SIZE SZ_1M 70#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
71
72#define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000)
73 71
74/* 72/*
75 * This macro defines the physical to virtual address mapping for all the 73 * This macro defines the physical to virtual address mapping for all the
@@ -105,78 +103,189 @@
105 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) 103 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
106 104
107/* fixed interrupt numbers */ 105/* fixed interrupt numbers */
108#define MXC_INT_LCDC 61 106#define MX2x_INT_CSPI3 6
109#define MXC_INT_SLCDC 60 107#define MX2x_INT_GPIO 8
110#define MXC_INT_EMMAPP 52 108#define MX2x_INT_SDHC2 10
111#define MXC_INT_EMMAPRP 51 109#define MX2x_INT_SDHC1 11
112#define MXC_INT_DMACH15 47 110#define MX2x_INT_I2C 12
113#define MXC_INT_DMACH14 46 111#define MX2x_INT_SSI2 13
114#define MXC_INT_DMACH13 45 112#define MX2x_INT_SSI1 14
115#define MXC_INT_DMACH12 44 113#define MX2x_INT_CSPI2 15
116#define MXC_INT_DMACH11 43 114#define MX2x_INT_CSPI1 16
117#define MXC_INT_DMACH10 42 115#define MX2x_INT_UART4 17
118#define MXC_INT_DMACH9 41 116#define MX2x_INT_UART3 18
119#define MXC_INT_DMACH8 40 117#define MX2x_INT_UART2 19
120#define MXC_INT_DMACH7 39 118#define MX2x_INT_UART1 20
121#define MXC_INT_DMACH6 38 119#define MX2x_INT_KPP 21
122#define MXC_INT_DMACH5 37 120#define MX2x_INT_RTC 22
123#define MXC_INT_DMACH4 36 121#define MX2x_INT_PWM 23
124#define MXC_INT_DMACH3 35 122#define MX2x_INT_GPT3 24
125#define MXC_INT_DMACH2 34 123#define MX2x_INT_GPT2 25
126#define MXC_INT_DMACH1 33 124#define MX2x_INT_GPT1 26
127#define MXC_INT_DMACH0 32 125#define MX2x_INT_WDOG 27
128#define MXC_INT_CSI 31 126#define MX2x_INT_PCMCIA 28
129#define MXC_INT_NANDFC 29 127#define MX2x_INT_NANDFC 29
130#define MXC_INT_PCMCIA 28 128#define MX2x_INT_CSI 31
131#define MXC_INT_WDOG 27 129#define MX2x_INT_DMACH0 32
132#define MXC_INT_GPT1 26 130#define MX2x_INT_DMACH1 33
133#define MXC_INT_GPT2 25 131#define MX2x_INT_DMACH2 34
134#define MXC_INT_GPT3 24 132#define MX2x_INT_DMACH3 35
135#define MXC_INT_GPT INT_GPT1 133#define MX2x_INT_DMACH4 36
136#define MXC_INT_PWM 23 134#define MX2x_INT_DMACH5 37
137#define MXC_INT_RTC 22 135#define MX2x_INT_DMACH6 38
138#define MXC_INT_KPP 21 136#define MX2x_INT_DMACH7 39
139#define MXC_INT_UART1 20 137#define MX2x_INT_DMACH8 40
140#define MXC_INT_UART2 19 138#define MX2x_INT_DMACH9 41
141#define MXC_INT_UART3 18 139#define MX2x_INT_DMACH10 42
142#define MXC_INT_UART4 17 140#define MX2x_INT_DMACH11 43
143#define MXC_INT_CSPI1 16 141#define MX2x_INT_DMACH12 44
144#define MXC_INT_CSPI2 15 142#define MX2x_INT_DMACH13 45
145#define MXC_INT_SSI1 14 143#define MX2x_INT_DMACH14 46
146#define MXC_INT_SSI2 13 144#define MX2x_INT_DMACH15 47
147#define MXC_INT_I2C 12 145#define MX2x_INT_EMMAPRP 51
148#define MXC_INT_SDHC1 11 146#define MX2x_INT_EMMAPP 52
149#define MXC_INT_SDHC2 10 147#define MX2x_INT_SLCDC 60
150#define MXC_INT_GPIO 8 148#define MX2x_INT_LCDC 61
151#define MXC_INT_CSPI3 6
152 149
153/* fixed DMA request numbers */ 150/* fixed DMA request numbers */
154#define DMA_REQ_CSI_RX 31 151#define MX2x_DMA_REQ_CSPI3_RX 1
155#define DMA_REQ_CSI_STAT 30 152#define MX2x_DMA_REQ_CSPI3_TX 2
156#define DMA_REQ_UART1_TX 27 153#define MX2x_DMA_REQ_EXT 3
157#define DMA_REQ_UART1_RX 26 154#define MX2x_DMA_REQ_SDHC2 6
158#define DMA_REQ_UART2_TX 25 155#define MX2x_DMA_REQ_SDHC1 7
159#define DMA_REQ_UART2_RX 24 156#define MX2x_DMA_REQ_SSI2_RX0 8
160#define DMA_REQ_UART3_TX 23 157#define MX2x_DMA_REQ_SSI2_TX0 9
161#define DMA_REQ_UART3_RX 22 158#define MX2x_DMA_REQ_SSI2_RX1 10
162#define DMA_REQ_UART4_TX 21 159#define MX2x_DMA_REQ_SSI2_TX1 11
163#define DMA_REQ_UART4_RX 20 160#define MX2x_DMA_REQ_SSI1_RX0 12
164#define DMA_REQ_CSPI1_TX 19 161#define MX2x_DMA_REQ_SSI1_TX0 13
165#define DMA_REQ_CSPI1_RX 18 162#define MX2x_DMA_REQ_SSI1_RX1 14
166#define DMA_REQ_CSPI2_TX 17 163#define MX2x_DMA_REQ_SSI1_TX1 15
167#define DMA_REQ_CSPI2_RX 16 164#define MX2x_DMA_REQ_CSPI2_RX 16
168#define DMA_REQ_SSI1_TX1 15 165#define MX2x_DMA_REQ_CSPI2_TX 17
169#define DMA_REQ_SSI1_RX1 14 166#define MX2x_DMA_REQ_CSPI1_RX 18
170#define DMA_REQ_SSI1_TX0 13 167#define MX2x_DMA_REQ_CSPI1_TX 19
171#define DMA_REQ_SSI1_RX0 12 168#define MX2x_DMA_REQ_UART4_RX 20
172#define DMA_REQ_SSI2_TX1 11 169#define MX2x_DMA_REQ_UART4_TX 21
173#define DMA_REQ_SSI2_RX1 10 170#define MX2x_DMA_REQ_UART3_RX 22
174#define DMA_REQ_SSI2_TX0 9 171#define MX2x_DMA_REQ_UART3_TX 23
175#define DMA_REQ_SSI2_RX0 8 172#define MX2x_DMA_REQ_UART2_RX 24
176#define DMA_REQ_SDHC1 7 173#define MX2x_DMA_REQ_UART2_TX 25
177#define DMA_REQ_SDHC2 6 174#define MX2x_DMA_REQ_UART1_RX 26
178#define DMA_REQ_EXT 3 175#define MX2x_DMA_REQ_UART1_TX 27
179#define DMA_REQ_CSPI3_TX 2 176#define MX2x_DMA_REQ_CSI_STAT 30
180#define DMA_REQ_CSPI3_RX 1 177#define MX2x_DMA_REQ_CSI_RX 31
178
179/* these should go away */
180#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR
181#define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT
182#define AIPI_SIZE MX2x_AIPI_SIZE
183#define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR
184#define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR
185#define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR
186#define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR
187#define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR
188#define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR
189#define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR
190#define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR
191#define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR
192#define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR
193#define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR
194#define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR
195#define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR
196#define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR
197#define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR
198#define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR
199#define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR
200#define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR
201#define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR
202#define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR
203#define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR
204#define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR
205#define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR
206#define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR
207#define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR
208#define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR
209#define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR
210#define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR
211#define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR
212#define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR
213#define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR
214#define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR
215#define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR
216#define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR
217#define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT
218#define SAHB1_SIZE MX2x_SAHB1_SIZE
219#define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR
220#define MXC_INT_CSPI3 MX2x_INT_CSPI3
221#define MXC_INT_GPIO MX2x_INT_GPIO
222#define MXC_INT_SDHC2 MX2x_INT_SDHC2
223#define MXC_INT_SDHC1 MX2x_INT_SDHC1
224#define MXC_INT_I2C MX2x_INT_I2C
225#define MXC_INT_SSI2 MX2x_INT_SSI2
226#define MXC_INT_SSI1 MX2x_INT_SSI1
227#define MXC_INT_CSPI2 MX2x_INT_CSPI2
228#define MXC_INT_CSPI1 MX2x_INT_CSPI1
229#define MXC_INT_UART4 MX2x_INT_UART4
230#define MXC_INT_UART3 MX2x_INT_UART3
231#define MXC_INT_UART2 MX2x_INT_UART2
232#define MXC_INT_UART1 MX2x_INT_UART1
233#define MXC_INT_KPP MX2x_INT_KPP
234#define MXC_INT_RTC MX2x_INT_RTC
235#define MXC_INT_PWM MX2x_INT_PWM
236#define MXC_INT_GPT3 MX2x_INT_GPT3
237#define MXC_INT_GPT2 MX2x_INT_GPT2
238#define MXC_INT_GPT1 MX2x_INT_GPT1
239#define MXC_INT_WDOG MX2x_INT_WDOG
240#define MXC_INT_PCMCIA MX2x_INT_PCMCIA
241#define MXC_INT_NANDFC MX2x_INT_NANDFC
242#define MXC_INT_CSI MX2x_INT_CSI
243#define MXC_INT_DMACH0 MX2x_INT_DMACH0
244#define MXC_INT_DMACH1 MX2x_INT_DMACH1
245#define MXC_INT_DMACH2 MX2x_INT_DMACH2
246#define MXC_INT_DMACH3 MX2x_INT_DMACH3
247#define MXC_INT_DMACH4 MX2x_INT_DMACH4
248#define MXC_INT_DMACH5 MX2x_INT_DMACH5
249#define MXC_INT_DMACH6 MX2x_INT_DMACH6
250#define MXC_INT_DMACH7 MX2x_INT_DMACH7
251#define MXC_INT_DMACH8 MX2x_INT_DMACH8
252#define MXC_INT_DMACH9 MX2x_INT_DMACH9
253#define MXC_INT_DMACH10 MX2x_INT_DMACH10
254#define MXC_INT_DMACH11 MX2x_INT_DMACH11
255#define MXC_INT_DMACH12 MX2x_INT_DMACH12
256#define MXC_INT_DMACH13 MX2x_INT_DMACH13
257#define MXC_INT_DMACH14 MX2x_INT_DMACH14
258#define MXC_INT_DMACH15 MX2x_INT_DMACH15
259#define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP
260#define MXC_INT_EMMAPP MX2x_INT_EMMAPP
261#define MXC_INT_SLCDC MX2x_INT_SLCDC
262#define MXC_INT_LCDC MX2x_INT_LCDC
263#define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX
264#define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX
265#define DMA_REQ_EXT MX2x_DMA_REQ_EXT
266#define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2
267#define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1
268#define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0
269#define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0
270#define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1
271#define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1
272#define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0
273#define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0
274#define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1
275#define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1
276#define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX
277#define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX
278#define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX
279#define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX
280#define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX
281#define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX
282#define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX
283#define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX
284#define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX
285#define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX
286#define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX
287#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX
288#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT
289#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX
181 290
182#endif /* __ASM_ARCH_MXC_MX2x_H__ */ 291#endif /* __ASM_ARCH_MXC_MX2x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index 14ac0dcc82f4..b8b47d139eb5 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -1,45 +1,218 @@
1/* 1/*
2 * IRAM 2 * IRAM
3 */ 3 */
4#define MX31_IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */ 4#define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */
5#define MX31_IRAM_SIZE SZ_16K 5#define MX31_IRAM_SIZE SZ_16K
6 6
7#define MX31_OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) 7#define MX31_L2CC_BASE_ADDR 0x30000000
8#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) 8#define MX31_L2CC_SIZE SZ_1M
9#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
10#define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
11 9
12#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) 10#define MX31_AIPS1_BASE_ADDR 0x43f00000
13#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) 11#define MX31_AIPS1_BASE_ADDR_VIRT 0xfc000000
14#define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000) 12#define MX31_AIPS1_SIZE SZ_1M
15#define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000) 13#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
14#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000)
15#define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000)
16#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000)
17#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000)
18#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
19#define MX31_I2C_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
20#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
21#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
22#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
23#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000)
24#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000)
25#define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000)
26#define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000)
27#define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000)
28#define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000)
29#define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000)
30#define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000)
31#define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000)
32#define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000)
33#define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000)
34#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000)
16 35
17#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) 36#define MX31_SPBA0_BASE_ADDR 0x50000000
18#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000) 37#define MX31_SPBA0_BASE_ADDR_VIRT 0xfc100000
19#define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000) 38#define MX31_SPBA0_SIZE SZ_1M
20#define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000) 39#define MX31_MMC_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
21#define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) 40#define MX31_MMC_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
41#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000)
42#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000)
43#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000)
44#define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000)
45#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000)
46#define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000)
47#define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000)
48#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000)
22 49
23#define MX31_NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000) 50#define MX31_AIPS2_BASE_ADDR 0x53f00000
51#define MX31_AIPS2_BASE_ADDR_VIRT 0xfc200000
52#define MX31_AIPS2_SIZE SZ_1M
53#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000)
54#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000)
55#define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000)
56#define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000)
57#define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000)
58#define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000)
59#define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000)
60#define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000)
61#define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000)
62#define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000)
63#define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000)
64#define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000)
65#define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000)
66#define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000)
67#define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000)
68#define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000)
69#define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000)
70#define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000)
71#define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000)
72#define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000)
73#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000)
24 74
25#define MXC_INT_MPEG4_ENCODER 5 75#define MX31_ROMP_BASE_ADDR 0x60000000
26#define MXC_INT_FIRI 7 76#define MX31_ROMP_BASE_ADDR_VIRT 0xfc500000
77#define MX31_ROMP_SIZE SZ_1M
78
79#define MX31_AVIC_BASE_ADDR 0x68000000
80#define MX31_AVIC_BASE_ADDR_VIRT 0xfc400000
81#define MX31_AVIC_SIZE SZ_1M
82
83#define MX31_IPU_MEM_BASE_ADDR 0x70000000
84#define MX31_CSD0_BASE_ADDR 0x80000000
85#define MX31_CSD1_BASE_ADDR 0x90000000
86
87#define MX31_CS0_BASE_ADDR 0xa0000000
88#define MX31_CS1_BASE_ADDR 0xa8000000
89#define MX31_CS2_BASE_ADDR 0xb0000000
90#define MX31_CS3_BASE_ADDR 0xb2000000
91
92#define MX31_CS4_BASE_ADDR 0xb4000000
93#define MX31_CS4_BASE_ADDR_VIRT 0xf4000000
94#define MX31_CS4_SIZE SZ_32M
95
96#define MX31_CS5_BASE_ADDR 0xb6000000
97#define MX31_CS5_BASE_ADDR_VIRT 0xf6000000
98#define MX31_CS5_SIZE SZ_32M
99
100#define MX31_X_MEMC_BASE_ADDR 0xb8000000
101#define MX31_X_MEMC_BASE_ADDR_VIRT 0xfc320000
102#define MX31_X_MEMC_SIZE SZ_64K
103#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000)
104#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000)
105#define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000)
106#define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000)
107#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000)
108#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR
109
110#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
111
112#define MX31_INT_I2C3 3
113#define MX31_INT_I2C2 4
114#define MX31_INT_MPEG4_ENCODER 5
115#define MX31_INT_RTIC 6
116#define MX31_INT_FIRI 7
27#define MX31_INT_MMC_SDHC2 8 117#define MX31_INT_MMC_SDHC2 8
28#define MXC_INT_MMC_SDHC1 9 118#define MX31_INT_MMC_SDHC1 9
119#define MX31_INT_I2C 10
29#define MX31_INT_SSI2 11 120#define MX31_INT_SSI2 11
30#define MX31_INT_SSI1 12 121#define MX31_INT_SSI1 12
31#define MXC_INT_MBX 16 122#define MX31_INT_CSPI2 13
32#define MXC_INT_CSPI3 17 123#define MX31_INT_CSPI1 14
33#define MXC_INT_SIM2 20 124#define MX31_INT_ATA 15
34#define MXC_INT_SIM1 21 125#define MX31_INT_MBX 16
35#define MXC_INT_CCM_DVFS 31 126#define MX31_INT_CSPI3 17
36#define MXC_INT_USB1 35 127#define MX31_INT_UART3 18
37#define MXC_INT_USB2 36 128#define MX31_INT_IIM 19
38#define MXC_INT_USB3 37 129#define MX31_INT_SIM2 20
39#define MXC_INT_USB4 38 130#define MX31_INT_SIM1 21
40#define MXC_INT_MSHC2 40 131#define MX31_INT_RNGA 22
41#define MXC_INT_UART4 46 132#define MX31_INT_EVTMON 23
42#define MXC_INT_UART5 47 133#define MX31_INT_KPP 24
43#define MXC_INT_CCM 53 134#define MX31_INT_RTC 25
44#define MXC_INT_PCMCIA 54 135#define MX31_INT_PWM 26
136#define MX31_INT_EPIT2 27
137#define MX31_INT_EPIT1 28
138#define MX31_INT_GPT 29
139#define MX31_INT_POWER_FAIL 30
140#define MX31_INT_CCM_DVFS 31
141#define MX31_INT_UART2 32
142#define MX31_INT_NANDFC 33
143#define MX31_INT_SDMA 34
144#define MX31_INT_USB1 35
145#define MX31_INT_USB2 36
146#define MX31_INT_USB3 37
147#define MX31_INT_USB4 38
148#define MX31_INT_MSHC1 39
149#define MX31_INT_MSHC2 40
150#define MX31_INT_IPU_ERR 41
151#define MX31_INT_IPU_SYN 42
152#define MX31_INT_UART1 45
153#define MX31_INT_UART4 46
154#define MX31_INT_UART5 47
155#define MX31_INT_ECT 48
156#define MX31_INT_SCC_SCM 49
157#define MX31_INT_SCC_SMN 50
158#define MX31_INT_GPIO2 51
159#define MX31_INT_GPIO1 52
160#define MX31_INT_CCM 53
161#define MX31_INT_PCMCIA 54
162#define MX31_INT_WDOG 55
163#define MX31_INT_GPIO3 56
164#define MX31_INT_EXT_POWER 58
165#define MX31_INT_EXT_TEMPER 59
166#define MX31_INT_EXT_SENSOR60 60
167#define MX31_INT_EXT_SENSOR61 61
168#define MX31_INT_EXT_WDOG 62
169#define MX31_INT_EXT_TV 63
170
171#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */
172
173/* silicon revisions specific to i.MX31 */
174#define MX31_CHIP_REV_1_0 0x10
175#define MX31_CHIP_REV_1_1 0x11
176#define MX31_CHIP_REV_1_2 0x12
177#define MX31_CHIP_REV_1_3 0x13
178#define MX31_CHIP_REV_2_0 0x20
179#define MX31_CHIP_REV_2_1 0x21
180#define MX31_CHIP_REV_2_2 0x22
181#define MX31_CHIP_REV_2_3 0x23
182#define MX31_CHIP_REV_3_0 0x30
183#define MX31_CHIP_REV_3_1 0x31
184#define MX31_CHIP_REV_3_2 0x32
185
186#define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0
187#define MX31_SYSTEM_REV_NUM 3
45 188
189/* these should go away */
190#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR
191#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR
192#define UART5_BASE_ADDR MX31_UART5_BASE_ADDR
193#define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR
194#define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR
195#define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR
196#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR
197#define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR
198#define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR
199#define SCM_BASE_ADDR MX31_SCM_BASE_ADDR
200#define SMN_BASE_ADDR MX31_SMN_BASE_ADDR
201#define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR
202#define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER
203#define MXC_INT_FIRI MX31_INT_FIRI
204#define MXC_INT_MMC_SDHC1 MX31_INT_MMC_SDHC1
205#define MXC_INT_MBX MX31_INT_MBX
206#define MXC_INT_CSPI3 MX31_INT_CSPI3
207#define MXC_INT_SIM2 MX31_INT_SIM2
208#define MXC_INT_SIM1 MX31_INT_SIM1
209#define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS
210#define MXC_INT_USB1 MX31_INT_USB1
211#define MXC_INT_USB2 MX31_INT_USB2
212#define MXC_INT_USB3 MX31_INT_USB3
213#define MXC_INT_USB4 MX31_INT_USB4
214#define MXC_INT_MSHC2 MX31_INT_MSHC2
215#define MXC_INT_UART4 MX31_INT_UART4
216#define MXC_INT_UART5 MX31_INT_UART5
217#define MXC_INT_CCM MX31_INT_CCM
218#define MXC_INT_PCMCIA MX31_INT_PCMCIA
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index ab4cfec6c8ab..af871bce35b6 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -2,29 +2,196 @@
2 * IRAM 2 * IRAM
3 */ 3 */
4#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */ 4#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */
5#define MX35_IRAM_SIZE SZ_128K 5#define MX35_IRAM_SIZE SZ_128K
6 6
7#define MXC_FEC_BASE_ADDR 0x50038000 7#define MX35_L2CC_BASE_ADDR 0x30000000
8#define MX35_OTG_BASE_ADDR 0x53ff4000 8#define MX35_L2CC_SIZE SZ_1M
9#define MX35_NFC_BASE_ADDR 0xBB000000 9
10#define MX35_AIPS1_BASE_ADDR 0x43f00000
11#define MX35_AIPS1_BASE_ADDR_VIRT 0xfc000000
12#define MX35_AIPS1_SIZE SZ_1M
13#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000)
14#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000)
15#define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000)
16#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000)
17#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000)
18#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000)
19#define MX35_I2C_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000)
20#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000)
21#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000)
22#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000)
23#define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000)
24#define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000)
25#define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000)
26#define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000)
27#define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000)
28#define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000)
29#define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000)
30#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000)
31
32#define MX35_SPBA0_BASE_ADDR 0x50000000
33#define MX35_SPBA0_BASE_ADDR_VIRT 0xfc100000
34#define MX35_SPBA0_SIZE SZ_1M
35#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000)
36#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000)
37#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000)
38#define MX35_ATA_DMA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000)
39#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000)
40#define MX35_FEC_BASE_ADDR 0x50038000
41#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000)
42
43#define MX35_AIPS2_BASE_ADDR 0x53f00000
44#define MX35_AIPS2_BASE_ADDR_VIRT 0xfc200000
45#define MX35_AIPS2_SIZE SZ_1M
46#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000)
47#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000)
48#define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000)
49#define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000)
50#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000)
51#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000)
52#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000)
53#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000)
54#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000)
55#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000)
56#define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000)
57#define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000)
58#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000)
59#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000)
60#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000)
61#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
62#define MX35_OTG_BASE_ADDR 0x53ff4000
63
64#define MX35_ROMP_BASE_ADDR 0x60000000
65#define MX35_ROMP_BASE_ADDR_VIRT 0xfc500000
66#define MX35_ROMP_SIZE SZ_1M
67
68#define MX35_AVIC_BASE_ADDR 0x68000000
69#define MX35_AVIC_BASE_ADDR_VIRT 0xfc400000
70#define MX35_AVIC_SIZE SZ_1M
71
72/*
73 * Memory regions and CS
74 */
75#define MX35_IPU_MEM_BASE_ADDR 0x70000000
76#define MX35_CSD0_BASE_ADDR 0x80000000
77#define MX35_CSD1_BASE_ADDR 0x90000000
78
79#define MX35_CS0_BASE_ADDR 0xa0000000
80#define MX35_CS1_BASE_ADDR 0xa8000000
81#define MX35_CS2_BASE_ADDR 0xb0000000
82#define MX35_CS3_BASE_ADDR 0xb2000000
83
84#define MX35_CS4_BASE_ADDR 0xb4000000
85#define MX35_CS4_BASE_ADDR_VIRT 0xf4000000
86#define MX35_CS4_SIZE SZ_32M
87
88#define MX35_CS5_BASE_ADDR 0xb6000000
89#define MX35_CS5_BASE_ADDR_VIRT 0xf6000000
90#define MX35_CS5_SIZE SZ_32M
91
92/*
93 * NAND, SDRAM, WEIM, M3IF, EMI controllers
94 */
95#define MX35_X_MEMC_BASE_ADDR 0xb8000000
96#define MX35_X_MEMC_BASE_ADDR_VIRT 0xfc320000
97#define MX35_X_MEMC_SIZE SZ_64K
98#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000)
99#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000)
100#define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000)
101#define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000)
102#define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR
103
104#define MX35_NFC_BASE_ADDR 0xbb000000
105#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
10 106
11/* 107/*
12 * Interrupt numbers 108 * Interrupt numbers
13 */ 109 */
14#define MXC_INT_OWIRE 2 110#define MX35_INT_OWIRE 2
111#define MX35_INT_I2C3 3
112#define MX35_INT_I2C2 4
113#define MX35_INT_RTIC 6
15#define MX35_INT_MMC_SDHC1 7 114#define MX35_INT_MMC_SDHC1 7
16#define MXC_INT_MMC_SDHC2 8 115#define MX35_INT_MMC_SDHC2 8
17#define MXC_INT_MMC_SDHC3 9 116#define MX35_INT_MMC_SDHC3 9
117#define MX35_INT_I2C 10
18#define MX35_INT_SSI1 11 118#define MX35_INT_SSI1 11
19#define MX35_INT_SSI2 12 119#define MX35_INT_SSI2 12
20#define MXC_INT_GPU2D 16 120#define MX35_INT_CSPI2 13
21#define MXC_INT_ASRC 17 121#define MX35_INT_CSPI1 14
22#define MXC_INT_USBHS 35 122#define MX35_INT_ATA 15
23#define MXC_INT_USBOTG 37 123#define MX35_INT_GPU2D 16
24#define MXC_INT_ESAI 40 124#define MX35_INT_ASRC 17
25#define MXC_INT_CAN1 43 125#define MX35_INT_UART3 18
26#define MXC_INT_CAN2 44 126#define MX35_INT_IIM 19
27#define MXC_INT_MLB 46 127#define MX35_INT_RNGA 22
28#define MXC_INT_SPDIF 47 128#define MX35_INT_EVTMON 23
29#define MXC_INT_FEC 57 129#define MX35_INT_KPP 24
130#define MX35_INT_RTC 25
131#define MX35_INT_PWM 26
132#define MX35_INT_EPIT2 27
133#define MX35_INT_EPIT1 28
134#define MX35_INT_GPT 29
135#define MX35_INT_POWER_FAIL 30
136#define MX35_INT_UART2 32
137#define MX35_INT_NANDFC 33
138#define MX35_INT_SDMA 34
139#define MX35_INT_USBHS 35
140#define MX35_INT_USBOTG 37
141#define MX35_INT_MSHC1 39
142#define MX35_INT_ESAI 40
143#define MX35_INT_IPU_ERR 41
144#define MX35_INT_IPU_SYN 42
145#define MX35_INT_CAN1 43
146#define MX35_INT_CAN2 44
147#define MX35_INT_UART1 45
148#define MX35_INT_MLB 46
149#define MX35_INT_SPDIF 47
150#define MX35_INT_ECT 48
151#define MX35_INT_SCC_SCM 49
152#define MX35_INT_SCC_SMN 50
153#define MX35_INT_GPIO2 51
154#define MX35_INT_GPIO1 52
155#define MX35_INT_WDOG 55
156#define MX35_INT_GPIO3 56
157#define MX35_INT_FEC 57
158#define MX35_INT_EXT_POWER 58
159#define MX35_INT_EXT_TEMPER 59
160#define MX35_INT_EXT_SENSOR60 60
161#define MX35_INT_EXT_SENSOR61 61
162#define MX35_INT_EXT_WDOG 62
163#define MX35_INT_EXT_TV 63
164
165#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */
166
167/* silicon revisions specific to i.MX31 */
168#define MX35_CHIP_REV_1_0 0x10
169#define MX35_CHIP_REV_1_1 0x11
170#define MX35_CHIP_REV_1_2 0x12
171#define MX35_CHIP_REV_1_3 0x13
172#define MX35_CHIP_REV_2_0 0x20
173#define MX35_CHIP_REV_2_1 0x21
174#define MX35_CHIP_REV_2_2 0x22
175#define MX35_CHIP_REV_2_3 0x23
176#define MX35_CHIP_REV_3_0 0x30
177#define MX35_CHIP_REV_3_1 0x31
178#define MX35_CHIP_REV_3_2 0x32
179
180#define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0
181#define MX35_SYSTEM_REV_NUM 3
30 182
183/* these should go away */
184#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
185#define MXC_INT_OWIRE MX35_INT_OWIRE
186#define MXC_INT_MMC_SDHC2 MX35_INT_MMC_SDHC2
187#define MXC_INT_MMC_SDHC3 MX35_INT_MMC_SDHC3
188#define MXC_INT_GPU2D MX35_INT_GPU2D
189#define MXC_INT_ASRC MX35_INT_ASRC
190#define MXC_INT_USBHS MX35_INT_USBHS
191#define MXC_INT_USBOTG MX35_INT_USBOTG
192#define MXC_INT_ESAI MX35_INT_ESAI
193#define MXC_INT_CAN1 MX35_INT_CAN1
194#define MXC_INT_CAN2 MX35_INT_CAN2
195#define MXC_INT_MLB MX35_INT_MLB
196#define MXC_INT_SPDIF MX35_INT_SPDIF
197#define MXC_INT_FEC MX35_INT_FEC
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index 009f4440276b..be69272407ad 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -34,120 +34,117 @@
34 * C0000000 64M PCMCIA/CF 34 * C0000000 64M PCMCIA/CF
35 */ 35 */
36 36
37#define CS0_BASE_ADDR 0xA0000000
38#define CS1_BASE_ADDR 0xA8000000
39#define CS2_BASE_ADDR 0xB0000000
40#define CS3_BASE_ADDR 0xB2000000
41
42#define CS4_BASE_ADDR 0xB4000000
43#define CS4_BASE_ADDR_VIRT 0xF4000000
44#define CS4_SIZE SZ_32M
45
46#define CS5_BASE_ADDR 0xB6000000
47#define CS5_BASE_ADDR_VIRT 0xF6000000
48#define CS5_SIZE SZ_32M
49
50#define PCMCIA_MEM_BASE_ADDR 0xBC000000
51
52/* 37/*
53 * L2CC 38 * L2CC
54 */ 39 */
55#define L2CC_BASE_ADDR 0x30000000 40#define MX3x_L2CC_BASE_ADDR 0x30000000
56#define L2CC_SIZE SZ_1M 41#define MX3x_L2CC_SIZE SZ_1M
57 42
58/* 43/*
59 * AIPS 1 44 * AIPS 1
60 */ 45 */
61#define AIPS1_BASE_ADDR 0x43F00000 46#define MX3x_AIPS1_BASE_ADDR 0x43f00000
62#define AIPS1_BASE_ADDR_VIRT 0xFC000000 47#define MX3x_AIPS1_BASE_ADDR_VIRT 0xfc000000
63#define AIPS1_SIZE SZ_1M 48#define MX3x_AIPS1_SIZE SZ_1M
64 49#define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
65#define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000) 50#define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
66#define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000) 51#define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
67#define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000) 52#define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
68#define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000) 53#define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
69#define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000) 54#define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
70#define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000) 55#define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
71#define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) 56#define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
72#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) 57#define MX3x_UART1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x90000)
73#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) 58#define MX3x_UART2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x94000)
74#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) 59#define MX3x_I2C2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x98000)
75#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) 60#define MX3x_OWIRE_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x9c000)
76#define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) 61#define MX3x_SSI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa0000)
77#define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) 62#define MX3x_CSPI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa4000)
78#define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) 63#define MX3x_KPP_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa8000)
79#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) 64#define MX3x_IOMUXC_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xac000)
80#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) 65#define MX3x_ECT_IP1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb8000)
81#define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) 66#define MX3x_ECT_IP2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xbc000)
82#define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
83 67
84/* 68/*
85 * SPBA global module enabled #0 69 * SPBA global module enabled #0
86 */ 70 */
87#define SPBA0_BASE_ADDR 0x50000000 71#define MX3x_SPBA0_BASE_ADDR 0x50000000
88#define SPBA0_BASE_ADDR_VIRT 0xFC100000 72#define MX3x_SPBA0_BASE_ADDR_VIRT 0xfc100000
89#define SPBA0_SIZE SZ_1M 73#define MX3x_SPBA0_SIZE SZ_1M
90 74#define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000)
91#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) 75#define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000)
92#define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) 76#define MX3x_SSI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x14000)
93#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) 77#define MX3x_ATA_DMA_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x20000)
94#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) 78#define MX3x_MSHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x24000)
95#define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) 79#define MX3x_SPBA_CTRL_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x3c000)
96#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
97 80
98/* 81/*
99 * AIPS 2 82 * AIPS 2
100 */ 83 */
101#define AIPS2_BASE_ADDR 0x53F00000 84#define MX3x_AIPS2_BASE_ADDR 0x53f00000
102#define AIPS2_BASE_ADDR_VIRT 0xFC200000 85#define MX3x_AIPS2_BASE_ADDR_VIRT 0xfc200000
103#define AIPS2_SIZE SZ_1M 86#define MX3x_AIPS2_SIZE SZ_1M
104#define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) 87#define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000)
105#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) 88#define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000)
106#define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) 89#define MX3x_EPIT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x94000)
107#define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) 90#define MX3x_EPIT2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x98000)
108#define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) 91#define MX3x_GPIO3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xa4000)
109#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) 92#define MX3x_SCC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xac000)
110#define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) 93#define MX3x_RNGA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xb0000)
111#define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) 94#define MX3x_IPU_CTRL_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc0000)
112#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) 95#define MX3x_AUDMUX_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc4000)
113#define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) 96#define MX3x_GPIO1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xcc000)
114#define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) 97#define MX3x_GPIO2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd0000)
115#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000) 98#define MX3x_SDMA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd4000)
116#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) 99#define MX3x_RTC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd8000)
117#define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) 100#define MX3x_WDOG_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xdc000)
118#define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) 101#define MX3x_PWM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xe0000)
119#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) 102#define MX3x_RTIC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xec000)
120 103
121/* 104/*
122 * ROMP and AVIC 105 * ROMP and AVIC
123 */ 106 */
124#define ROMP_BASE_ADDR 0x60000000 107#define MX3x_ROMP_BASE_ADDR 0x60000000
125#define ROMP_BASE_ADDR_VIRT 0xFC500000 108#define MX3x_ROMP_BASE_ADDR_VIRT 0xfc500000
126#define ROMP_SIZE SZ_1M 109#define MX3x_ROMP_SIZE SZ_1M
127 110
128#define AVIC_BASE_ADDR 0x68000000 111#define MX3x_AVIC_BASE_ADDR 0x68000000
129#define AVIC_BASE_ADDR_VIRT 0xFC400000 112#define MX3x_AVIC_BASE_ADDR_VIRT 0xfc400000
130#define AVIC_SIZE SZ_1M 113#define MX3x_AVIC_SIZE SZ_1M
131 114
132/* 115/*
133 * NAND, SDRAM, WEIM, M3IF, EMI controllers 116 * Memory regions and CS
134 */ 117 */
135#define X_MEMC_BASE_ADDR 0xB8000000 118#define MX3x_IPU_MEM_BASE_ADDR 0x70000000
136#define X_MEMC_BASE_ADDR_VIRT 0xFC320000 119#define MX3x_CSD0_BASE_ADDR 0x80000000
137#define X_MEMC_SIZE SZ_64K 120#define MX3x_CSD1_BASE_ADDR 0x90000000
138 121
139#define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) 122#define MX3x_CS0_BASE_ADDR 0xa0000000
140#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) 123#define MX3x_CS1_BASE_ADDR 0xa8000000
141#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) 124#define MX3x_CS2_BASE_ADDR 0xb0000000
142#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) 125#define MX3x_CS3_BASE_ADDR 0xb2000000
143#define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR 126
127#define MX3x_CS4_BASE_ADDR 0xb4000000
128#define MX3x_CS4_BASE_ADDR_VIRT 0xf4000000
129#define MX3x_CS4_SIZE SZ_32M
130
131#define MX3x_CS5_BASE_ADDR 0xb6000000
132#define MX3x_CS5_BASE_ADDR_VIRT 0xf6000000
133#define MX3x_CS5_SIZE SZ_32M
144 134
145/* 135/*
146 * Memory regions and CS 136 * NAND, SDRAM, WEIM, M3IF, EMI controllers
147 */ 137 */
148#define IPU_MEM_BASE_ADDR 0x70000000 138#define MX3x_X_MEMC_BASE_ADDR 0xb8000000
149#define CSD0_BASE_ADDR 0x80000000 139#define MX3x_X_MEMC_BASE_ADDR_VIRT 0xfc320000
150#define CSD1_BASE_ADDR 0x90000000 140#define MX3x_X_MEMC_SIZE SZ_64K
141#define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000)
142#define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000)
143#define MX3x_M3IF_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x3000)
144#define MX3x_EMI_CTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x4000)
145#define MX3x_PCMCIA_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
146
147#define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000
151 148
152/*! 149/*!
153 * This macro defines the physical to virtual address mapping for all the 150 * This macro defines the physical to virtual address mapping for all the
@@ -202,74 +199,207 @@
202/* 199/*
203 * Interrupt numbers 200 * Interrupt numbers
204 */ 201 */
205#define MXC_INT_I2C3 3 202#define MX3x_INT_I2C3 3
206#define MXC_INT_I2C2 4 203#define MX3x_INT_I2C2 4
207#define MXC_INT_RTIC 6 204#define MX3x_INT_RTIC 6
208#define MXC_INT_I2C 10 205#define MX3x_INT_I2C 10
209#define MXC_INT_CSPI2 13 206#define MX3x_INT_CSPI2 13
210#define MXC_INT_CSPI1 14 207#define MX3x_INT_CSPI1 14
211#define MXC_INT_ATA 15 208#define MX3x_INT_ATA 15
212#define MXC_INT_UART3 18 209#define MX3x_INT_UART3 18
213#define MXC_INT_IIM 19 210#define MX3x_INT_IIM 19
214#define MXC_INT_RNGA 22 211#define MX3x_INT_RNGA 22
215#define MXC_INT_EVTMON 23 212#define MX3x_INT_EVTMON 23
216#define MXC_INT_KPP 24 213#define MX3x_INT_KPP 24
217#define MXC_INT_RTC 25 214#define MX3x_INT_RTC 25
218#define MXC_INT_PWM 26 215#define MX3x_INT_PWM 26
219#define MXC_INT_EPIT2 27 216#define MX3x_INT_EPIT2 27
220#define MXC_INT_EPIT1 28 217#define MX3x_INT_EPIT1 28
221#define MXC_INT_GPT 29 218#define MX3x_INT_GPT 29
222#define MXC_INT_POWER_FAIL 30 219#define MX3x_INT_POWER_FAIL 30
223#define MXC_INT_UART2 32 220#define MX3x_INT_UART2 32
224#define MXC_INT_NANDFC 33 221#define MX3x_INT_NANDFC 33
225#define MXC_INT_SDMA 34 222#define MX3x_INT_SDMA 34
226#define MXC_INT_MSHC1 39 223#define MX3x_INT_MSHC1 39
227#define MXC_INT_IPU_ERR 41 224#define MX3x_INT_IPU_ERR 41
228#define MXC_INT_IPU_SYN 42 225#define MX3x_INT_IPU_SYN 42
229#define MXC_INT_UART1 45 226#define MX3x_INT_UART1 45
230#define MXC_INT_ECT 48 227#define MX3x_INT_ECT 48
231#define MXC_INT_SCC_SCM 49 228#define MX3x_INT_SCC_SCM 49
232#define MXC_INT_SCC_SMN 50 229#define MX3x_INT_SCC_SMN 50
233#define MXC_INT_GPIO2 51 230#define MX3x_INT_GPIO2 51
234#define MXC_INT_GPIO1 52 231#define MX3x_INT_GPIO1 52
235#define MXC_INT_WDOG 55 232#define MX3x_INT_WDOG 55
236#define MXC_INT_GPIO3 56 233#define MX3x_INT_GPIO3 56
237#define MXC_INT_EXT_POWER 58 234#define MX3x_INT_EXT_POWER 58
238#define MXC_INT_EXT_TEMPER 59 235#define MX3x_INT_EXT_TEMPER 59
239#define MXC_INT_EXT_SENSOR60 60 236#define MX3x_INT_EXT_SENSOR60 60
240#define MXC_INT_EXT_SENSOR61 61 237#define MX3x_INT_EXT_SENSOR61 61
241#define MXC_INT_EXT_WDOG 62 238#define MX3x_INT_EXT_WDOG 62
242#define MXC_INT_EXT_TV 63 239#define MX3x_INT_EXT_TV 63
243 240
244#define PROD_SIGNATURE 0x1 /* For MX31 */ 241#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */
245 242
246/* silicon revisions specific to i.MX31 */ 243/* silicon revisions specific to i.MX31 */
247#define CHIP_REV_1_0 0x10 244#define MX3x_CHIP_REV_1_0 0x10
248#define CHIP_REV_1_1 0x11 245#define MX3x_CHIP_REV_1_1 0x11
249#define CHIP_REV_1_2 0x12 246#define MX3x_CHIP_REV_1_2 0x12
250#define CHIP_REV_1_3 0x13 247#define MX3x_CHIP_REV_1_3 0x13
251#define CHIP_REV_2_0 0x20 248#define MX3x_CHIP_REV_2_0 0x20
252#define CHIP_REV_2_1 0x21 249#define MX3x_CHIP_REV_2_1 0x21
253#define CHIP_REV_2_2 0x22 250#define MX3x_CHIP_REV_2_2 0x22
254#define CHIP_REV_2_3 0x23 251#define MX3x_CHIP_REV_2_3 0x23
255#define CHIP_REV_3_0 0x30 252#define MX3x_CHIP_REV_3_0 0x30
256#define CHIP_REV_3_1 0x31 253#define MX3x_CHIP_REV_3_1 0x31
257#define CHIP_REV_3_2 0x32 254#define MX3x_CHIP_REV_3_2 0x32
258 255
259#define SYSTEM_REV_MIN CHIP_REV_1_0 256#define MX3x_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0
260#define SYSTEM_REV_NUM 3 257#define MX3x_SYSTEM_REV_NUM 3
261 258
262/* Mandatory defines used globally */ 259/* Mandatory defines used globally */
263 260
264#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) 261#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
265 262
266extern unsigned int system_rev; 263extern unsigned int mx31_cpu_rev;
264extern void mx31_read_cpu_rev(void);
267 265
268static inline int mx31_revision(void) 266static inline int mx31_revision(void)
269{ 267{
270 return system_rev; 268 return mx31_cpu_rev;
271} 269}
272#endif 270#endif
273 271
274#endif /* __ASM_ARCH_MXC_MX31_H__ */ 272/* these should go away */
273#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR
274#define L2CC_SIZE MX3x_L2CC_SIZE
275#define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR
276#define AIPS1_BASE_ADDR_VIRT MX3x_AIPS1_BASE_ADDR_VIRT
277#define AIPS1_SIZE MX3x_AIPS1_SIZE
278#define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR
279#define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR
280#define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR
281#define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR
282#define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR
283#define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR
284#define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR
285#define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR
286#define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR
287#define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR
288#define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR
289#define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR
290#define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR
291#define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR
292#define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR
293#define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR
294#define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR
295#define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR
296#define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR
297#define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT
298#define SPBA0_SIZE MX3x_SPBA0_SIZE
299#define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR
300#define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR
301#define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR
302#define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR
303#define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR
304#define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR
305#define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR
306#define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT
307#define AIPS2_SIZE MX3x_AIPS2_SIZE
308#define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR
309#define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR
310#define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR
311#define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR
312#define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR
313#define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR
314#define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR
315#define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR
316#define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR
317#define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR
318#define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR
319#define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR
320#define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR
321#define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR
322#define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR
323#define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR
324#define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR
325#define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT
326#define ROMP_SIZE MX3x_ROMP_SIZE
327#define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR
328#define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT
329#define AVIC_SIZE MX3x_AVIC_SIZE
330#define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR
331#define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR
332#define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR
333#define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR
334#define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR
335#define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR
336#define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR
337#define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR
338#define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT
339#define CS4_SIZE MX3x_CS4_SIZE
340#define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR
341#define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT
342#define CS5_SIZE MX3x_CS5_SIZE
343#define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR
344#define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT
345#define X_MEMC_SIZE MX3x_X_MEMC_SIZE
346#define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR
347#define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR
348#define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR
349#define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
350#define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR
351#define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR
352#define MXC_INT_I2C3 MX3x_INT_I2C3
353#define MXC_INT_I2C2 MX3x_INT_I2C2
354#define MXC_INT_RTIC MX3x_INT_RTIC
355#define MXC_INT_I2C MX3x_INT_I2C
356#define MXC_INT_CSPI2 MX3x_INT_CSPI2
357#define MXC_INT_CSPI1 MX3x_INT_CSPI1
358#define MXC_INT_ATA MX3x_INT_ATA
359#define MXC_INT_UART3 MX3x_INT_UART3
360#define MXC_INT_IIM MX3x_INT_IIM
361#define MXC_INT_RNGA MX3x_INT_RNGA
362#define MXC_INT_EVTMON MX3x_INT_EVTMON
363#define MXC_INT_KPP MX3x_INT_KPP
364#define MXC_INT_RTC MX3x_INT_RTC
365#define MXC_INT_PWM MX3x_INT_PWM
366#define MXC_INT_EPIT2 MX3x_INT_EPIT2
367#define MXC_INT_EPIT1 MX3x_INT_EPIT1
368#define MXC_INT_GPT MX3x_INT_GPT
369#define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL
370#define MXC_INT_UART2 MX3x_INT_UART2
371#define MXC_INT_NANDFC MX3x_INT_NANDFC
372#define MXC_INT_SDMA MX3x_INT_SDMA
373#define MXC_INT_MSHC1 MX3x_INT_MSHC1
374#define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR
375#define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN
376#define MXC_INT_UART1 MX3x_INT_UART1
377#define MXC_INT_ECT MX3x_INT_ECT
378#define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM
379#define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN
380#define MXC_INT_GPIO2 MX3x_INT_GPIO2
381#define MXC_INT_GPIO1 MX3x_INT_GPIO1
382#define MXC_INT_WDOG MX3x_INT_WDOG
383#define MXC_INT_GPIO3 MX3x_INT_GPIO3
384#define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER
385#define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER
386#define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60
387#define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61
388#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG
389#define MXC_INT_EXT_TV MX3x_INT_EXT_TV
390#define PROD_SIGNATURE MX3x_PROD_SIGNATURE
391#define CHIP_REV_1_0 MX3x_CHIP_REV_1_0
392#define CHIP_REV_1_1 MX3x_CHIP_REV_1_1
393#define CHIP_REV_1_2 MX3x_CHIP_REV_1_2
394#define CHIP_REV_1_3 MX3x_CHIP_REV_1_3
395#define CHIP_REV_2_0 MX3x_CHIP_REV_2_0
396#define CHIP_REV_2_1 MX3x_CHIP_REV_2_1
397#define CHIP_REV_2_2 MX3x_CHIP_REV_2_2
398#define CHIP_REV_2_3 MX3x_CHIP_REV_2_3
399#define CHIP_REV_3_0 MX3x_CHIP_REV_3_0
400#define CHIP_REV_3_1 MX3x_CHIP_REV_3_1
401#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2
402#define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN
403#define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM
275 404
405#endif /* __ASM_ARCH_MXC_MX31_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/ulpi.h b/arch/arm/plat-mxc/include/mach/ulpi.h
new file mode 100644
index 000000000000..96b6ab4c40c3
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/ulpi.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_ULPI_H
2#define __MACH_ULPI_H
3
4extern struct otg_io_access_ops mxc_ulpi_access_ops;
5
6#endif /* __MACH_ULPI_H */
7
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index 082a3908256b..4d5d395ad63b 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -83,6 +83,8 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
83 case MACH_TYPE_MX27ADS: 83 case MACH_TYPE_MX27ADS:
84 case MACH_TYPE_PCM038: 84 case MACH_TYPE_PCM038:
85 case MACH_TYPE_MX21ADS: 85 case MACH_TYPE_MX21ADS:
86 case MACH_TYPE_PCA100:
87 case MACH_TYPE_MXT_TD60:
86 uart_base = MX2X_UART1_BASE_ADDR; 88 uart_base = MX2X_UART1_BASE_ADDR;
87 break; 89 break;
88 case MACH_TYPE_MX31LITE: 90 case MACH_TYPE_MX31LITE:
@@ -94,6 +96,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
94 case MACH_TYPE_MX31ADS: 96 case MACH_TYPE_MX31ADS:
95 case MACH_TYPE_MX35_3DS: 97 case MACH_TYPE_MX35_3DS:
96 case MACH_TYPE_PCM043: 98 case MACH_TYPE_PCM043:
99 case MACH_TYPE_LILLY1131:
97 uart_base = MX3X_UART1_BASE_ADDR; 100 uart_base = MX3X_UART1_BASE_ADDR;
98 break; 101 break;
99 case MACH_TYPE_MAGX_ZN5: 102 case MACH_TYPE_MAGX_ZN5:
diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c
index 851ca99bf1b1..b318c6a222d5 100644
--- a/arch/arm/plat-mxc/iomux-v3.c
+++ b/arch/arm/plat-mxc/iomux-v3.c
@@ -31,19 +31,11 @@
31 31
32static void __iomem *base; 32static void __iomem *base;
33 33
34static unsigned long iomux_v3_pad_alloc_map[0x200 / BITS_PER_LONG];
35
36/* 34/*
37 * setups a single pin: 35 * setups a single pad in the iomuxer
38 * - reserves the pin so that it is not claimed by another driver
39 * - setups the iomux according to the configuration
40 */ 36 */
41int mxc_iomux_v3_setup_pad(struct pad_desc *pad) 37int mxc_iomux_v3_setup_pad(struct pad_desc *pad)
42{ 38{
43 unsigned int pad_ofs = pad->pad_ctrl_ofs;
44
45 if (test_and_set_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map))
46 return -EBUSY;
47 if (pad->mux_ctrl_ofs) 39 if (pad->mux_ctrl_ofs)
48 __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs); 40 __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs);
49 41
@@ -66,37 +58,13 @@ int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count)
66 for (i = 0; i < count; i++) { 58 for (i = 0; i < count; i++) {
67 ret = mxc_iomux_v3_setup_pad(p); 59 ret = mxc_iomux_v3_setup_pad(p);
68 if (ret) 60 if (ret)
69 goto setup_error; 61 return ret;
70 p++; 62 p++;
71 } 63 }
72 return 0; 64 return 0;
73
74setup_error:
75 mxc_iomux_v3_release_multiple_pads(pad_list, i);
76 return ret;
77} 65}
78EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads); 66EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
79 67
80void mxc_iomux_v3_release_pad(struct pad_desc *pad)
81{
82 unsigned int pad_ofs = pad->pad_ctrl_ofs;
83
84 clear_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map);
85}
86EXPORT_SYMBOL(mxc_iomux_v3_release_pad);
87
88void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count)
89{
90 struct pad_desc *p = pad_list;
91 int i;
92
93 for (i = 0; i < count; i++) {
94 mxc_iomux_v3_release_pad(p);
95 p++;
96 }
97}
98EXPORT_SYMBOL(mxc_iomux_v3_release_multiple_pads);
99
100void mxc_iomux_v3_init(void __iomem *iomux_v3_base) 68void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
101{ 69{
102 base = iomux_v3_base; 70 base = iomux_v3_base;
diff --git a/arch/arm/plat-mxc/ulpi.c b/arch/arm/plat-mxc/ulpi.c
new file mode 100644
index 000000000000..582c6dfaba4a
--- /dev/null
+++ b/arch/arm/plat-mxc/ulpi.c
@@ -0,0 +1,113 @@
1/*
2 * Copyright 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 * Copyright 2009 Daniel Mack <daniel@caiaq.de>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/io.h>
23#include <linux/delay.h>
24#include <linux/usb/otg.h>
25
26#include <mach/ulpi.h>
27
28/* ULPIVIEW register bits */
29#define ULPIVW_WU (1 << 31) /* Wakeup */
30#define ULPIVW_RUN (1 << 30) /* read/write run */
31#define ULPIVW_WRITE (1 << 29) /* 0 = read 1 = write */
32#define ULPIVW_SS (1 << 27) /* SyncState */
33#define ULPIVW_PORT_MASK 0x07 /* Port field */
34#define ULPIVW_PORT_SHIFT 24
35#define ULPIVW_ADDR_MASK 0xff /* data address field */
36#define ULPIVW_ADDR_SHIFT 16
37#define ULPIVW_RDATA_MASK 0xff /* read data field */
38#define ULPIVW_RDATA_SHIFT 8
39#define ULPIVW_WDATA_MASK 0xff /* write data field */
40#define ULPIVW_WDATA_SHIFT 0
41
42static int ulpi_poll(void __iomem *view, u32 bit)
43{
44 int timeout = 10000;
45
46 while (timeout--) {
47 u32 data = __raw_readl(view);
48
49 if (!(data & bit))
50 return 0;
51
52 cpu_relax();
53 };
54
55 printk(KERN_WARNING "timeout polling for ULPI device\n");
56
57 return -ETIMEDOUT;
58}
59
60static int ulpi_read(struct otg_transceiver *otg, u32 reg)
61{
62 int ret;
63 void __iomem *view = otg->io_priv;
64
65 /* make sure interface is running */
66 if (!(__raw_readl(view) & ULPIVW_SS)) {
67 __raw_writel(ULPIVW_WU, view);
68
69 /* wait for wakeup */
70 ret = ulpi_poll(view, ULPIVW_WU);
71 if (ret)
72 return ret;
73 }
74
75 /* read the register */
76 __raw_writel((ULPIVW_RUN | (reg << ULPIVW_ADDR_SHIFT)), view);
77
78 /* wait for completion */
79 ret = ulpi_poll(view, ULPIVW_RUN);
80 if (ret)
81 return ret;
82
83 return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK;
84}
85
86static int ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
87{
88 int ret;
89 void __iomem *view = otg->io_priv;
90
91 /* make sure the interface is running */
92 if (!(__raw_readl(view) & ULPIVW_SS)) {
93 __raw_writel(ULPIVW_WU, view);
94 /* wait for wakeup */
95 ret = ulpi_poll(view, ULPIVW_WU);
96 if (ret)
97 return ret;
98 }
99
100 __raw_writel((ULPIVW_RUN | ULPIVW_WRITE |
101 (reg << ULPIVW_ADDR_SHIFT) |
102 ((val & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), view);
103
104 /* wait for completion */
105 return ulpi_poll(view, ULPIVW_RUN);
106}
107
108struct otg_io_access_ops mxc_ulpi_access_ops = {
109 .read = ulpi_read,
110 .write = ulpi_write,
111};
112EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops);
113
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-25 17:19:35 -0400