diff options
author | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2010-11-12 10:40:06 -0500 |
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committer | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2010-11-19 15:54:35 -0500 |
commit | 9e1dde33876ba83ad586c336647fff133d0f5472 (patch) | |
tree | 52aa4efe87f2f52234f2f55e3a2b29e61de683c9 /arch/arm/plat-mxc/include/mach/mx31.h | |
parent | fed3d35b06bf3f6a3383c2637d054823c563200b (diff) |
ARM: mx3: dynamically allocate fsl-usb2-udc devices
While adapting the #defines for this I noticed that the offset
used for USB HS on i.MX35 differs from the documented offset.
I kept the working offset and commented that the documentation
differs.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mx31.h')
-rw-r--r-- | arch/arm/plat-mxc/include/mach/mx31.h | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index d024c9c5dd3f..092323144e2b 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h | |||
@@ -24,7 +24,10 @@ | |||
24 | #define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) | 24 | #define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) |
25 | #define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) | 25 | #define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) |
26 | #define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) | 26 | #define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) |
27 | #define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) | 27 | #define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) |
28 | #define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000) | ||
29 | #define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200) | ||
30 | #define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400) | ||
28 | #define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) | 31 | #define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) |
29 | #define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000) | 32 | #define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000) |
30 | #define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000) | 33 | #define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000) |
@@ -161,10 +164,9 @@ static inline void mx31_setup_weimcs(size_t cs, | |||
161 | #define MX31_INT_UART2 32 | 164 | #define MX31_INT_UART2 32 |
162 | #define MX31_INT_NFC 33 | 165 | #define MX31_INT_NFC 33 |
163 | #define MX31_INT_SDMA 34 | 166 | #define MX31_INT_SDMA 34 |
164 | #define MX31_INT_USB1 35 | 167 | #define MX31_INT_USB_HS1 35 |
165 | #define MX31_INT_USB2 36 | 168 | #define MX31_INT_USB_HS2 36 |
166 | #define MX31_INT_USB3 37 | 169 | #define MX31_INT_USB_OTG 37 |
167 | #define MX31_INT_USB4 38 | ||
168 | #define MX31_INT_MSHC1 39 | 170 | #define MX31_INT_MSHC1 39 |
169 | #define MX31_INT_MSHC2 40 | 171 | #define MX31_INT_MSHC2 40 |
170 | #define MX31_INT_IPU_ERR 41 | 172 | #define MX31_INT_IPU_ERR 41 |