diff options
| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-07-31 09:20:16 -0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-07-31 09:20:16 -0400 |
| commit | 7b70c4275f28702b76b273c8534c38f8313812e9 (patch) | |
| tree | 1df2229ca02466bd1adda814ac5c37aa0a597db1 /arch/arm/plat-mxc/include/mach/mx27.h | |
| parent | ceb0885d3b01bb2e2f18765770e212914f2864be (diff) | |
| parent | a20df564d15bd28e3df24e1c65b885bd74d23f17 (diff) | |
Merge branch 'devel-stable' into devel
Conflicts:
arch/arm/kernel/entry-armv.S
arch/arm/kernel/setup.c
arch/arm/mm/init.c
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mx27.h')
| -rw-r--r-- | arch/arm/plat-mxc/include/mach/mx27.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index bae9cd75beee..a8ab2e02a8ca 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h | |||
| @@ -48,7 +48,7 @@ | |||
| 48 | #define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000) | 48 | #define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000) |
| 49 | #define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000) | 49 | #define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000) |
| 50 | #define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000) | 50 | #define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000) |
| 51 | #define MX27_I2C_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) | 51 | #define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) |
| 52 | #define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) | 52 | #define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) |
| 53 | #define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) | 53 | #define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) |
| 54 | #define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) | 54 | #define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) |
| @@ -150,7 +150,7 @@ static inline void mx27_setup_weimcs(size_t cs, | |||
| 150 | #define MX27_INT_SDHC3 9 | 150 | #define MX27_INT_SDHC3 9 |
| 151 | #define MX27_INT_SDHC2 10 | 151 | #define MX27_INT_SDHC2 10 |
| 152 | #define MX27_INT_SDHC1 11 | 152 | #define MX27_INT_SDHC1 11 |
| 153 | #define MX27_INT_I2C 12 | 153 | #define MX27_INT_I2C1 12 |
| 154 | #define MX27_INT_SSI2 13 | 154 | #define MX27_INT_SSI2 13 |
| 155 | #define MX27_INT_SSI1 14 | 155 | #define MX27_INT_SSI1 14 |
| 156 | #define MX27_INT_CSPI2 15 | 156 | #define MX27_INT_CSPI2 15 |