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author | Herbert Xu <herbert@gondor.apana.org.au> | 2010-05-02 23:28:58 -0400 |
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committer | Herbert Xu <herbert@gondor.apana.org.au> | 2010-05-02 23:28:58 -0400 |
commit | df2071bd081408318d659cd14a9cf6ff23d874c9 (patch) | |
tree | b31291b5fd4b9f84c629833afbfaa8d431857475 /arch/arm/plat-mxc/include/mach/irqs.h | |
parent | 97e3d94aac1c3e95bd04d1b186479a4df3663ab8 (diff) | |
parent | be1066bbcd443a65df312fdecea7e4959adedb45 (diff) |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/irqs.h')
-rw-r--r-- | arch/arm/plat-mxc/include/mach/irqs.h | 20 |
1 files changed, 14 insertions, 6 deletions
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 0cb347645db4..86781f7b0c0c 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h | |||
@@ -12,22 +12,29 @@ | |||
12 | #define __ASM_ARCH_MXC_IRQS_H__ | 12 | #define __ASM_ARCH_MXC_IRQS_H__ |
13 | 13 | ||
14 | /* | 14 | /* |
15 | * So far all i.MX SoCs have 64 internal interrupts | 15 | * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64 |
16 | */ | 16 | */ |
17 | #ifdef CONFIG_MXC_TZIC | ||
18 | #define MXC_INTERNAL_IRQS 128 | ||
19 | #else | ||
17 | #define MXC_INTERNAL_IRQS 64 | 20 | #define MXC_INTERNAL_IRQS 64 |
21 | #endif | ||
18 | 22 | ||
19 | #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS | 23 | #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS |
20 | 24 | ||
21 | #if defined CONFIG_ARCH_MX1 | 25 | /* these are ordered by size to support multi-SoC kernels */ |
22 | #define MXC_GPIO_IRQS (32 * 4) | 26 | #if defined CONFIG_ARCH_MX2 |
23 | #elif defined CONFIG_ARCH_MX2 | ||
24 | #define MXC_GPIO_IRQS (32 * 6) | 27 | #define MXC_GPIO_IRQS (32 * 6) |
25 | #elif defined CONFIG_ARCH_MX3 | 28 | #elif defined CONFIG_ARCH_MX1 |
26 | #define MXC_GPIO_IRQS (32 * 3) | 29 | #define MXC_GPIO_IRQS (32 * 4) |
27 | #elif defined CONFIG_ARCH_MX25 | 30 | #elif defined CONFIG_ARCH_MX25 |
28 | #define MXC_GPIO_IRQS (32 * 4) | 31 | #define MXC_GPIO_IRQS (32 * 4) |
32 | #elif defined CONFIG_ARCH_MX5 | ||
33 | #define MXC_GPIO_IRQS (32 * 4) | ||
29 | #elif defined CONFIG_ARCH_MXC91231 | 34 | #elif defined CONFIG_ARCH_MXC91231 |
30 | #define MXC_GPIO_IRQS (32 * 4) | 35 | #define MXC_GPIO_IRQS (32 * 4) |
36 | #elif defined CONFIG_ARCH_MX3 | ||
37 | #define MXC_GPIO_IRQS (32 * 3) | ||
31 | #endif | 38 | #endif |
32 | 39 | ||
33 | /* | 40 | /* |
@@ -51,6 +58,7 @@ | |||
51 | #else | 58 | #else |
52 | #define MX3_IPU_IRQS 0 | 59 | #define MX3_IPU_IRQS 0 |
53 | #endif | 60 | #endif |
61 | /* REVISIT: Add IPU irqs on IMX51 */ | ||
54 | 62 | ||
55 | #define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS) | 63 | #define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS) |
56 | 64 | ||