ARM: 6112/1: Use the Inner Shareable I-cache and BTB ops on ARMv7 SMP

The standard I-cache Invalidate All (ICIALLU) and Branch Predication
Invalidate All (BPIALL) operations are not automatically broadcast to
the other CPUs in an ARMv7 MP system. The patch adds the Inner Shareable
variants, ICIALLUIS and BPIALLIS, if ARMv7 and SMP.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

2 files changed, 12 insertions, 0 deletions

diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index bcd64f265870..06a90dcfc60a 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -167,7 +167,11 @@ ENTRY(v7_coherent_user_range)
         cmp     r0, r1
         blo     1b
         mov     r0, #0
+#ifdef CONFIG_SMP
+        mcr     p15, 0, r0, c7, c1, 6           @ invalidate BTB Inner Shareable
+#else
         mcr     p15, 0, r0, c7, c5, 6           @ invalidate BTB
+#endif
         dsb
         isb
         mov     pc, lr
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index 0cb1848bd876..f3f288a9546d 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -50,7 +50,11 @@ ENTRY(v7wbi_flush_user_tlb_range)
         cmp     r0, r1
         blo     1b
         mov     ip, #0
+#ifdef CONFIG_SMP
+        mcr     p15, 0, ip, c7, c1, 6           @ flush BTAC/BTB Inner Shareable
+#else
         mcr     p15, 0, ip, c7, c5, 6           @ flush BTAC/BTB
+#endif
         dsb
         mov     pc, lr
 ENDPROC(v7wbi_flush_user_tlb_range)
@@ -79,7 +83,11 @@ ENTRY(v7wbi_flush_kern_tlb_range)
         cmp     r0, r1
         blo     1b
         mov     r2, #0
+#ifdef CONFIG_SMP
+        mcr     p15, 0, r2, c7, c1, 6           @ flush BTAC/BTB Inner Shareable
+#else
         mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
+#endif
         dsb
         isb
         mov     pc, lr