diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-10-06 12:12:25 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-10-13 12:11:28 -0400 |
commit | b1b3f49ce4606452279b58b17f2bbe2ba00304b7 (patch) | |
tree | c9cfdc72dd580a9c3ace71846af45b4f65268f46 /arch/arm/mm | |
parent | 4f1cd91497774488ed16119ec3f54b3daf1561de (diff) |
ARM: config: sort select statements alphanumerically
As suggested by Andrew Morton:
This is a pet peeve of mine. Any time there's a long list of items
(header file inclusions, kconfig entries, array initalisers, etc) and
someone wants to add a new item, they *always* go and stick it at the
end of the list.
Guys, don't do this. Either put the new item into a randomly-chosen
position or, probably better, alphanumerically sort the list.
lets sort all our select statements alphanumerically. This commit was
created by the following perl:
while (<>) {
while (/\\\s*$/) {
$_ .= <>;
}
undef %selects if /^\s*config\s+/;
if (/^\s+select\s+(\w+).*/) {
if (defined($selects{$1})) {
if ($selects{$1} eq $_) {
print STDERR "Warning: removing duplicated $1 entry\n";
} else {
print STDERR "Error: $1 differently selected\n".
"\tOld: $selects{$1}\n".
"\tNew: $_\n";
exit 1;
}
}
$selects{$1} = $_;
next;
}
if (%selects and (/^\s*$/ or /^\s+help/ or /^\s+---help---/ or
/^endif/ or /^endchoice/)) {
foreach $k (sort (keys %selects)) {
print "$selects{$k}";
}
undef %selects;
}
print;
}
if (%selects) {
foreach $k (sort (keys %selects)) {
print "$selects{$k}";
}
}
It found two duplicates:
Warning: removing duplicated S5P_SETUP_MIPIPHY entry
Warning: removing duplicated HARDIRQS_SW_RESEND entry
and they are identical duplicates, hence the shrinkage in the diffstat
of two lines.
We have four testers reporting success of this change (Tony, Stephen,
Linus and Sekhar.)
Acked-by: Jason Cooper <jason@lakedaemon.net>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r-- | arch/arm/mm/Kconfig | 106 |
1 files changed, 53 insertions, 53 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index c9a4963b5c3d..94186b6c685f 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig | |||
@@ -10,8 +10,8 @@ config CPU_ARM7TDMI | |||
10 | depends on !MMU | 10 | depends on !MMU |
11 | select CPU_32v4T | 11 | select CPU_32v4T |
12 | select CPU_ABRT_LV4T | 12 | select CPU_ABRT_LV4T |
13 | select CPU_PABRT_LEGACY | ||
14 | select CPU_CACHE_V4 | 13 | select CPU_CACHE_V4 |
14 | select CPU_PABRT_LEGACY | ||
15 | help | 15 | help |
16 | A 32-bit RISC microprocessor based on the ARM7 processor core | 16 | A 32-bit RISC microprocessor based on the ARM7 processor core |
17 | which has no memory control unit and cache. | 17 | which has no memory control unit and cache. |
@@ -24,11 +24,11 @@ config CPU_ARM720T | |||
24 | bool "Support ARM720T processor" if ARCH_INTEGRATOR | 24 | bool "Support ARM720T processor" if ARCH_INTEGRATOR |
25 | select CPU_32v4T | 25 | select CPU_32v4T |
26 | select CPU_ABRT_LV4T | 26 | select CPU_ABRT_LV4T |
27 | select CPU_PABRT_LEGACY | ||
28 | select CPU_CACHE_V4 | 27 | select CPU_CACHE_V4 |
29 | select CPU_CACHE_VIVT | 28 | select CPU_CACHE_VIVT |
30 | select CPU_CP15_MMU | ||
31 | select CPU_COPY_V4WT if MMU | 29 | select CPU_COPY_V4WT if MMU |
30 | select CPU_CP15_MMU | ||
31 | select CPU_PABRT_LEGACY | ||
32 | select CPU_TLB_V4WT if MMU | 32 | select CPU_TLB_V4WT if MMU |
33 | help | 33 | help |
34 | A 32-bit RISC processor with 8kByte Cache, Write Buffer and | 34 | A 32-bit RISC processor with 8kByte Cache, Write Buffer and |
@@ -43,9 +43,9 @@ config CPU_ARM740T | |||
43 | depends on !MMU | 43 | depends on !MMU |
44 | select CPU_32v4T | 44 | select CPU_32v4T |
45 | select CPU_ABRT_LV4T | 45 | select CPU_ABRT_LV4T |
46 | select CPU_PABRT_LEGACY | ||
47 | select CPU_CACHE_V3 # although the core is v4t | 46 | select CPU_CACHE_V3 # although the core is v4t |
48 | select CPU_CP15_MPU | 47 | select CPU_CP15_MPU |
48 | select CPU_PABRT_LEGACY | ||
49 | help | 49 | help |
50 | A 32-bit RISC processor with 8KB cache or 4KB variants, | 50 | A 32-bit RISC processor with 8KB cache or 4KB variants, |
51 | write buffer and MPU(Protection Unit) built around | 51 | write buffer and MPU(Protection Unit) built around |
@@ -60,8 +60,8 @@ config CPU_ARM9TDMI | |||
60 | depends on !MMU | 60 | depends on !MMU |
61 | select CPU_32v4T | 61 | select CPU_32v4T |
62 | select CPU_ABRT_NOMMU | 62 | select CPU_ABRT_NOMMU |
63 | select CPU_PABRT_LEGACY | ||
64 | select CPU_CACHE_V4 | 63 | select CPU_CACHE_V4 |
64 | select CPU_PABRT_LEGACY | ||
65 | help | 65 | help |
66 | A 32-bit RISC microprocessor based on the ARM9 processor core | 66 | A 32-bit RISC microprocessor based on the ARM9 processor core |
67 | which has no memory control unit and cache. | 67 | which has no memory control unit and cache. |
@@ -74,11 +74,11 @@ config CPU_ARM920T | |||
74 | bool "Support ARM920T processor" if ARCH_INTEGRATOR | 74 | bool "Support ARM920T processor" if ARCH_INTEGRATOR |
75 | select CPU_32v4T | 75 | select CPU_32v4T |
76 | select CPU_ABRT_EV4T | 76 | select CPU_ABRT_EV4T |
77 | select CPU_PABRT_LEGACY | ||
78 | select CPU_CACHE_V4WT | 77 | select CPU_CACHE_V4WT |
79 | select CPU_CACHE_VIVT | 78 | select CPU_CACHE_VIVT |
80 | select CPU_CP15_MMU | ||
81 | select CPU_COPY_V4WB if MMU | 79 | select CPU_COPY_V4WB if MMU |
80 | select CPU_CP15_MMU | ||
81 | select CPU_PABRT_LEGACY | ||
82 | select CPU_TLB_V4WBI if MMU | 82 | select CPU_TLB_V4WBI if MMU |
83 | help | 83 | help |
84 | The ARM920T is licensed to be produced by numerous vendors, | 84 | The ARM920T is licensed to be produced by numerous vendors, |
@@ -92,11 +92,11 @@ config CPU_ARM922T | |||
92 | bool "Support ARM922T processor" if ARCH_INTEGRATOR | 92 | bool "Support ARM922T processor" if ARCH_INTEGRATOR |
93 | select CPU_32v4T | 93 | select CPU_32v4T |
94 | select CPU_ABRT_EV4T | 94 | select CPU_ABRT_EV4T |
95 | select CPU_PABRT_LEGACY | ||
96 | select CPU_CACHE_V4WT | 95 | select CPU_CACHE_V4WT |
97 | select CPU_CACHE_VIVT | 96 | select CPU_CACHE_VIVT |
98 | select CPU_CP15_MMU | ||
99 | select CPU_COPY_V4WB if MMU | 97 | select CPU_COPY_V4WB if MMU |
98 | select CPU_CP15_MMU | ||
99 | select CPU_PABRT_LEGACY | ||
100 | select CPU_TLB_V4WBI if MMU | 100 | select CPU_TLB_V4WBI if MMU |
101 | help | 101 | help |
102 | The ARM922T is a version of the ARM920T, but with smaller | 102 | The ARM922T is a version of the ARM920T, but with smaller |
@@ -111,11 +111,11 @@ config CPU_ARM925T | |||
111 | bool "Support ARM925T processor" if ARCH_OMAP1 | 111 | bool "Support ARM925T processor" if ARCH_OMAP1 |
112 | select CPU_32v4T | 112 | select CPU_32v4T |
113 | select CPU_ABRT_EV4T | 113 | select CPU_ABRT_EV4T |
114 | select CPU_PABRT_LEGACY | ||
115 | select CPU_CACHE_V4WT | 114 | select CPU_CACHE_V4WT |
116 | select CPU_CACHE_VIVT | 115 | select CPU_CACHE_VIVT |
117 | select CPU_CP15_MMU | ||
118 | select CPU_COPY_V4WB if MMU | 116 | select CPU_COPY_V4WB if MMU |
117 | select CPU_CP15_MMU | ||
118 | select CPU_PABRT_LEGACY | ||
119 | select CPU_TLB_V4WBI if MMU | 119 | select CPU_TLB_V4WBI if MMU |
120 | help | 120 | help |
121 | The ARM925T is a mix between the ARM920T and ARM926T, but with | 121 | The ARM925T is a mix between the ARM920T and ARM926T, but with |
@@ -130,10 +130,10 @@ config CPU_ARM926T | |||
130 | bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB | 130 | bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB |
131 | select CPU_32v5 | 131 | select CPU_32v5 |
132 | select CPU_ABRT_EV5TJ | 132 | select CPU_ABRT_EV5TJ |
133 | select CPU_PABRT_LEGACY | ||
134 | select CPU_CACHE_VIVT | 133 | select CPU_CACHE_VIVT |
135 | select CPU_CP15_MMU | ||
136 | select CPU_COPY_V4WB if MMU | 134 | select CPU_COPY_V4WB if MMU |
135 | select CPU_CP15_MMU | ||
136 | select CPU_PABRT_LEGACY | ||
137 | select CPU_TLB_V4WBI if MMU | 137 | select CPU_TLB_V4WBI if MMU |
138 | help | 138 | help |
139 | This is a variant of the ARM920. It has slightly different | 139 | This is a variant of the ARM920. It has slightly different |
@@ -148,11 +148,11 @@ config CPU_FA526 | |||
148 | bool | 148 | bool |
149 | select CPU_32v4 | 149 | select CPU_32v4 |
150 | select CPU_ABRT_EV4 | 150 | select CPU_ABRT_EV4 |
151 | select CPU_PABRT_LEGACY | ||
152 | select CPU_CACHE_VIVT | ||
153 | select CPU_CP15_MMU | ||
154 | select CPU_CACHE_FA | 151 | select CPU_CACHE_FA |
152 | select CPU_CACHE_VIVT | ||
155 | select CPU_COPY_FA if MMU | 153 | select CPU_COPY_FA if MMU |
154 | select CPU_CP15_MMU | ||
155 | select CPU_PABRT_LEGACY | ||
156 | select CPU_TLB_FA if MMU | 156 | select CPU_TLB_FA if MMU |
157 | help | 157 | help |
158 | The FA526 is a version of the ARMv4 compatible processor with | 158 | The FA526 is a version of the ARMv4 compatible processor with |
@@ -167,9 +167,9 @@ config CPU_ARM940T | |||
167 | depends on !MMU | 167 | depends on !MMU |
168 | select CPU_32v4T | 168 | select CPU_32v4T |
169 | select CPU_ABRT_NOMMU | 169 | select CPU_ABRT_NOMMU |
170 | select CPU_PABRT_LEGACY | ||
171 | select CPU_CACHE_VIVT | 170 | select CPU_CACHE_VIVT |
172 | select CPU_CP15_MPU | 171 | select CPU_CP15_MPU |
172 | select CPU_PABRT_LEGACY | ||
173 | help | 173 | help |
174 | ARM940T is a member of the ARM9TDMI family of general- | 174 | ARM940T is a member of the ARM9TDMI family of general- |
175 | purpose microprocessors with MPU and separate 4KB | 175 | purpose microprocessors with MPU and separate 4KB |
@@ -185,9 +185,9 @@ config CPU_ARM946E | |||
185 | depends on !MMU | 185 | depends on !MMU |
186 | select CPU_32v5 | 186 | select CPU_32v5 |
187 | select CPU_ABRT_NOMMU | 187 | select CPU_ABRT_NOMMU |
188 | select CPU_PABRT_LEGACY | ||
189 | select CPU_CACHE_VIVT | 188 | select CPU_CACHE_VIVT |
190 | select CPU_CP15_MPU | 189 | select CPU_CP15_MPU |
190 | select CPU_PABRT_LEGACY | ||
191 | help | 191 | help |
192 | ARM946E-S is a member of the ARM9E-S family of high- | 192 | ARM946E-S is a member of the ARM9E-S family of high- |
193 | performance, 32-bit system-on-chip processor solutions. | 193 | performance, 32-bit system-on-chip processor solutions. |
@@ -201,11 +201,11 @@ config CPU_ARM1020 | |||
201 | bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR | 201 | bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR |
202 | select CPU_32v5 | 202 | select CPU_32v5 |
203 | select CPU_ABRT_EV4T | 203 | select CPU_ABRT_EV4T |
204 | select CPU_PABRT_LEGACY | ||
205 | select CPU_CACHE_V4WT | 204 | select CPU_CACHE_V4WT |
206 | select CPU_CACHE_VIVT | 205 | select CPU_CACHE_VIVT |
207 | select CPU_CP15_MMU | ||
208 | select CPU_COPY_V4WB if MMU | 206 | select CPU_COPY_V4WB if MMU |
207 | select CPU_CP15_MMU | ||
208 | select CPU_PABRT_LEGACY | ||
209 | select CPU_TLB_V4WBI if MMU | 209 | select CPU_TLB_V4WBI if MMU |
210 | help | 210 | help |
211 | The ARM1020 is the 32K cached version of the ARM10 processor, | 211 | The ARM1020 is the 32K cached version of the ARM10 processor, |
@@ -217,25 +217,25 @@ config CPU_ARM1020 | |||
217 | # ARM1020E - needs validating | 217 | # ARM1020E - needs validating |
218 | config CPU_ARM1020E | 218 | config CPU_ARM1020E |
219 | bool "Support ARM1020E processor" if ARCH_INTEGRATOR | 219 | bool "Support ARM1020E processor" if ARCH_INTEGRATOR |
220 | depends on n | ||
220 | select CPU_32v5 | 221 | select CPU_32v5 |
221 | select CPU_ABRT_EV4T | 222 | select CPU_ABRT_EV4T |
222 | select CPU_PABRT_LEGACY | ||
223 | select CPU_CACHE_V4WT | 223 | select CPU_CACHE_V4WT |
224 | select CPU_CACHE_VIVT | 224 | select CPU_CACHE_VIVT |
225 | select CPU_CP15_MMU | ||
226 | select CPU_COPY_V4WB if MMU | 225 | select CPU_COPY_V4WB if MMU |
226 | select CPU_CP15_MMU | ||
227 | select CPU_PABRT_LEGACY | ||
227 | select CPU_TLB_V4WBI if MMU | 228 | select CPU_TLB_V4WBI if MMU |
228 | depends on n | ||
229 | 229 | ||
230 | # ARM1022E | 230 | # ARM1022E |
231 | config CPU_ARM1022 | 231 | config CPU_ARM1022 |
232 | bool "Support ARM1022E processor" if ARCH_INTEGRATOR | 232 | bool "Support ARM1022E processor" if ARCH_INTEGRATOR |
233 | select CPU_32v5 | 233 | select CPU_32v5 |
234 | select CPU_ABRT_EV4T | 234 | select CPU_ABRT_EV4T |
235 | select CPU_PABRT_LEGACY | ||
236 | select CPU_CACHE_VIVT | 235 | select CPU_CACHE_VIVT |
237 | select CPU_CP15_MMU | ||
238 | select CPU_COPY_V4WB if MMU # can probably do better | 236 | select CPU_COPY_V4WB if MMU # can probably do better |
237 | select CPU_CP15_MMU | ||
238 | select CPU_PABRT_LEGACY | ||
239 | select CPU_TLB_V4WBI if MMU | 239 | select CPU_TLB_V4WBI if MMU |
240 | help | 240 | help |
241 | The ARM1022E is an implementation of the ARMv5TE architecture | 241 | The ARM1022E is an implementation of the ARMv5TE architecture |
@@ -250,10 +250,10 @@ config CPU_ARM1026 | |||
250 | bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR | 250 | bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR |
251 | select CPU_32v5 | 251 | select CPU_32v5 |
252 | select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 | 252 | select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 |
253 | select CPU_PABRT_LEGACY | ||
254 | select CPU_CACHE_VIVT | 253 | select CPU_CACHE_VIVT |
255 | select CPU_CP15_MMU | ||
256 | select CPU_COPY_V4WB if MMU # can probably do better | 254 | select CPU_COPY_V4WB if MMU # can probably do better |
255 | select CPU_CP15_MMU | ||
256 | select CPU_PABRT_LEGACY | ||
257 | select CPU_TLB_V4WBI if MMU | 257 | select CPU_TLB_V4WBI if MMU |
258 | help | 258 | help |
259 | The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture | 259 | The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture |
@@ -268,11 +268,11 @@ config CPU_SA110 | |||
268 | select CPU_32v3 if ARCH_RPC | 268 | select CPU_32v3 if ARCH_RPC |
269 | select CPU_32v4 if !ARCH_RPC | 269 | select CPU_32v4 if !ARCH_RPC |
270 | select CPU_ABRT_EV4 | 270 | select CPU_ABRT_EV4 |
271 | select CPU_PABRT_LEGACY | ||
272 | select CPU_CACHE_V4WB | 271 | select CPU_CACHE_V4WB |
273 | select CPU_CACHE_VIVT | 272 | select CPU_CACHE_VIVT |
274 | select CPU_CP15_MMU | ||
275 | select CPU_COPY_V4WB if MMU | 273 | select CPU_COPY_V4WB if MMU |
274 | select CPU_CP15_MMU | ||
275 | select CPU_PABRT_LEGACY | ||
276 | select CPU_TLB_V4WB if MMU | 276 | select CPU_TLB_V4WB if MMU |
277 | help | 277 | help |
278 | The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and | 278 | The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and |
@@ -288,10 +288,10 @@ config CPU_SA1100 | |||
288 | bool | 288 | bool |
289 | select CPU_32v4 | 289 | select CPU_32v4 |
290 | select CPU_ABRT_EV4 | 290 | select CPU_ABRT_EV4 |
291 | select CPU_PABRT_LEGACY | ||
292 | select CPU_CACHE_V4WB | 291 | select CPU_CACHE_V4WB |
293 | select CPU_CACHE_VIVT | 292 | select CPU_CACHE_VIVT |
294 | select CPU_CP15_MMU | 293 | select CPU_CP15_MMU |
294 | select CPU_PABRT_LEGACY | ||
295 | select CPU_TLB_V4WB if MMU | 295 | select CPU_TLB_V4WB if MMU |
296 | 296 | ||
297 | # XScale | 297 | # XScale |
@@ -299,9 +299,9 @@ config CPU_XSCALE | |||
299 | bool | 299 | bool |
300 | select CPU_32v5 | 300 | select CPU_32v5 |
301 | select CPU_ABRT_EV5T | 301 | select CPU_ABRT_EV5T |
302 | select CPU_PABRT_LEGACY | ||
303 | select CPU_CACHE_VIVT | 302 | select CPU_CACHE_VIVT |
304 | select CPU_CP15_MMU | 303 | select CPU_CP15_MMU |
304 | select CPU_PABRT_LEGACY | ||
305 | select CPU_TLB_V4WBI if MMU | 305 | select CPU_TLB_V4WBI if MMU |
306 | 306 | ||
307 | # XScale Core Version 3 | 307 | # XScale Core Version 3 |
@@ -309,9 +309,9 @@ config CPU_XSC3 | |||
309 | bool | 309 | bool |
310 | select CPU_32v5 | 310 | select CPU_32v5 |
311 | select CPU_ABRT_EV5T | 311 | select CPU_ABRT_EV5T |
312 | select CPU_PABRT_LEGACY | ||
313 | select CPU_CACHE_VIVT | 312 | select CPU_CACHE_VIVT |
314 | select CPU_CP15_MMU | 313 | select CPU_CP15_MMU |
314 | select CPU_PABRT_LEGACY | ||
315 | select CPU_TLB_V4WBI if MMU | 315 | select CPU_TLB_V4WBI if MMU |
316 | select IO_36 | 316 | select IO_36 |
317 | 317 | ||
@@ -320,21 +320,21 @@ config CPU_MOHAWK | |||
320 | bool | 320 | bool |
321 | select CPU_32v5 | 321 | select CPU_32v5 |
322 | select CPU_ABRT_EV5T | 322 | select CPU_ABRT_EV5T |
323 | select CPU_PABRT_LEGACY | ||
324 | select CPU_CACHE_VIVT | 323 | select CPU_CACHE_VIVT |
324 | select CPU_COPY_V4WB if MMU | ||
325 | select CPU_CP15_MMU | 325 | select CPU_CP15_MMU |
326 | select CPU_PABRT_LEGACY | ||
326 | select CPU_TLB_V4WBI if MMU | 327 | select CPU_TLB_V4WBI if MMU |
327 | select CPU_COPY_V4WB if MMU | ||
328 | 328 | ||
329 | # Feroceon | 329 | # Feroceon |
330 | config CPU_FEROCEON | 330 | config CPU_FEROCEON |
331 | bool | 331 | bool |
332 | select CPU_32v5 | 332 | select CPU_32v5 |
333 | select CPU_ABRT_EV5T | 333 | select CPU_ABRT_EV5T |
334 | select CPU_PABRT_LEGACY | ||
335 | select CPU_CACHE_VIVT | 334 | select CPU_CACHE_VIVT |
336 | select CPU_CP15_MMU | ||
337 | select CPU_COPY_FEROCEON if MMU | 335 | select CPU_COPY_FEROCEON if MMU |
336 | select CPU_CP15_MMU | ||
337 | select CPU_PABRT_LEGACY | ||
338 | select CPU_TLB_FEROCEON if MMU | 338 | select CPU_TLB_FEROCEON if MMU |
339 | 339 | ||
340 | config CPU_FEROCEON_OLD_ID | 340 | config CPU_FEROCEON_OLD_ID |
@@ -349,20 +349,20 @@ config CPU_FEROCEON_OLD_ID | |||
349 | # Marvell PJ4 | 349 | # Marvell PJ4 |
350 | config CPU_PJ4 | 350 | config CPU_PJ4 |
351 | bool | 351 | bool |
352 | select CPU_V7 | ||
353 | select ARM_THUMBEE | 352 | select ARM_THUMBEE |
353 | select CPU_V7 | ||
354 | 354 | ||
355 | # ARMv6 | 355 | # ARMv6 |
356 | config CPU_V6 | 356 | config CPU_V6 |
357 | bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX | 357 | bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX |
358 | select CPU_32v6 | 358 | select CPU_32v6 |
359 | select CPU_ABRT_EV6 | 359 | select CPU_ABRT_EV6 |
360 | select CPU_PABRT_V6 | ||
361 | select CPU_CACHE_V6 | 360 | select CPU_CACHE_V6 |
362 | select CPU_CACHE_VIPT | 361 | select CPU_CACHE_VIPT |
362 | select CPU_COPY_V6 if MMU | ||
363 | select CPU_CP15_MMU | 363 | select CPU_CP15_MMU |
364 | select CPU_HAS_ASID if MMU | 364 | select CPU_HAS_ASID if MMU |
365 | select CPU_COPY_V6 if MMU | 365 | select CPU_PABRT_V6 |
366 | select CPU_TLB_V6 if MMU | 366 | select CPU_TLB_V6 if MMU |
367 | 367 | ||
368 | # ARMv6k | 368 | # ARMv6k |
@@ -371,12 +371,12 @@ config CPU_V6K | |||
371 | select CPU_32v6 | 371 | select CPU_32v6 |
372 | select CPU_32v6K | 372 | select CPU_32v6K |
373 | select CPU_ABRT_EV6 | 373 | select CPU_ABRT_EV6 |
374 | select CPU_PABRT_V6 | ||
375 | select CPU_CACHE_V6 | 374 | select CPU_CACHE_V6 |
376 | select CPU_CACHE_VIPT | 375 | select CPU_CACHE_VIPT |
376 | select CPU_COPY_V6 if MMU | ||
377 | select CPU_CP15_MMU | 377 | select CPU_CP15_MMU |
378 | select CPU_HAS_ASID if MMU | 378 | select CPU_HAS_ASID if MMU |
379 | select CPU_COPY_V6 if MMU | 379 | select CPU_PABRT_V6 |
380 | select CPU_TLB_V6 if MMU | 380 | select CPU_TLB_V6 if MMU |
381 | 381 | ||
382 | # ARMv7 | 382 | # ARMv7 |
@@ -385,44 +385,44 @@ config CPU_V7 | |||
385 | select CPU_32v6K | 385 | select CPU_32v6K |
386 | select CPU_32v7 | 386 | select CPU_32v7 |
387 | select CPU_ABRT_EV7 | 387 | select CPU_ABRT_EV7 |
388 | select CPU_PABRT_V7 | ||
389 | select CPU_CACHE_V7 | 388 | select CPU_CACHE_V7 |
390 | select CPU_CACHE_VIPT | 389 | select CPU_CACHE_VIPT |
390 | select CPU_COPY_V6 if MMU | ||
391 | select CPU_CP15_MMU | 391 | select CPU_CP15_MMU |
392 | select CPU_HAS_ASID if MMU | 392 | select CPU_HAS_ASID if MMU |
393 | select CPU_COPY_V6 if MMU | 393 | select CPU_PABRT_V7 |
394 | select CPU_TLB_V7 if MMU | 394 | select CPU_TLB_V7 if MMU |
395 | 395 | ||
396 | # Figure out what processor architecture version we should be using. | 396 | # Figure out what processor architecture version we should be using. |
397 | # This defines the compiler instruction set which depends on the machine type. | 397 | # This defines the compiler instruction set which depends on the machine type. |
398 | config CPU_32v3 | 398 | config CPU_32v3 |
399 | bool | 399 | bool |
400 | select TLS_REG_EMUL if SMP || !MMU | ||
401 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP | ||
402 | select CPU_USE_DOMAINS if MMU | 400 | select CPU_USE_DOMAINS if MMU |
401 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP | ||
402 | select TLS_REG_EMUL if SMP || !MMU | ||
403 | 403 | ||
404 | config CPU_32v4 | 404 | config CPU_32v4 |
405 | bool | 405 | bool |
406 | select TLS_REG_EMUL if SMP || !MMU | ||
407 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP | ||
408 | select CPU_USE_DOMAINS if MMU | 406 | select CPU_USE_DOMAINS if MMU |
407 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP | ||
408 | select TLS_REG_EMUL if SMP || !MMU | ||
409 | 409 | ||
410 | config CPU_32v4T | 410 | config CPU_32v4T |
411 | bool | 411 | bool |
412 | select TLS_REG_EMUL if SMP || !MMU | ||
413 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP | ||
414 | select CPU_USE_DOMAINS if MMU | 412 | select CPU_USE_DOMAINS if MMU |
413 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP | ||
414 | select TLS_REG_EMUL if SMP || !MMU | ||
415 | 415 | ||
416 | config CPU_32v5 | 416 | config CPU_32v5 |
417 | bool | 417 | bool |
418 | select TLS_REG_EMUL if SMP || !MMU | ||
419 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP | ||
420 | select CPU_USE_DOMAINS if MMU | 418 | select CPU_USE_DOMAINS if MMU |
419 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP | ||
420 | select TLS_REG_EMUL if SMP || !MMU | ||
421 | 421 | ||
422 | config CPU_32v6 | 422 | config CPU_32v6 |
423 | bool | 423 | bool |
424 | select TLS_REG_EMUL if !CPU_32v6K && !MMU | ||
425 | select CPU_USE_DOMAINS if CPU_V6 && MMU | 424 | select CPU_USE_DOMAINS if CPU_V6 && MMU |
425 | select TLS_REG_EMUL if !CPU_32v6K && !MMU | ||
426 | 426 | ||
427 | config CPU_32v6K | 427 | config CPU_32v6K |
428 | bool | 428 | bool |
@@ -644,8 +644,8 @@ config ARM_VIRT_EXT | |||
644 | config SWP_EMULATE | 644 | config SWP_EMULATE |
645 | bool "Emulate SWP/SWPB instructions" | 645 | bool "Emulate SWP/SWPB instructions" |
646 | depends on !CPU_USE_DOMAINS && CPU_V7 | 646 | depends on !CPU_USE_DOMAINS && CPU_V7 |
647 | select HAVE_PROC_CPU if PROC_FS | ||
648 | default y if SMP | 647 | default y if SMP |
648 | select HAVE_PROC_CPU if PROC_FS | ||
649 | help | 649 | help |
650 | ARMv6 architecture deprecates use of the SWP/SWPB instructions. | 650 | ARMv6 architecture deprecates use of the SWP/SWPB instructions. |
651 | ARMv7 multiprocessing extensions introduce the ability to disable | 651 | ARMv7 multiprocessing extensions introduce the ability to disable |