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authorStanislav Samsonov <samsonov@marvell.com>2008-06-03 04:24:40 -0400
committerLennert Buytenhek <buytenh@marvell.com>2008-06-22 16:45:03 -0400
commit836a8051d54525e0782f156dcfa3c13d30f22840 (patch)
treea72c16e6bbfb4b4768562bc9757bdd04b17e4c7f /arch/arm/mm
parent7ea217a85e38c5ed6edbc789670badb619da9f28 (diff)
[ARM] Feroceon: L1 cache range operation support
This patch adds support for the L1 D cache range operations that are supported by the Marvell Discovery Duo and Marvell Kirkwood ARM SoCs. Signed-off-by: Stanislav Samsonov <samsonov@marvell.com> Acked-by: Saeed Bishara <saeed@marvell.com> Reviewed-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/proc-feroceon.S69
1 files changed, 68 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index 61a5025bf032..c279652a98fd 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -237,6 +237,20 @@ ENTRY(feroceon_flush_kern_dcache_page)
237 mcr p15, 0, r0, c7, c10, 4 @ drain WB 237 mcr p15, 0, r0, c7, c10, 4 @ drain WB
238 mov pc, lr 238 mov pc, lr
239 239
240 .align 5
241ENTRY(feroceon_range_flush_kern_dcache_page)
242 mrs r2, cpsr
243 add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive
244 orr r3, r2, #PSR_I_BIT
245 msr cpsr_c, r3 @ disable interrupts
246 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
247 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
248 msr cpsr_c, r2 @ restore interrupts
249 mov r0, #0
250 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
251 mcr p15, 0, r0, c7, c10, 4 @ drain WB
252 mov pc, lr
253
240/* 254/*
241 * dma_inv_range(start, end) 255 * dma_inv_range(start, end)
242 * 256 *
@@ -253,10 +267,10 @@ ENTRY(feroceon_flush_kern_dcache_page)
253 .align 5 267 .align 5
254ENTRY(feroceon_dma_inv_range) 268ENTRY(feroceon_dma_inv_range)
255 tst r0, #CACHE_DLINESIZE - 1 269 tst r0, #CACHE_DLINESIZE - 1
270 bic r0, r0, #CACHE_DLINESIZE - 1
256 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 271 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
257 tst r1, #CACHE_DLINESIZE - 1 272 tst r1, #CACHE_DLINESIZE - 1
258 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 273 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
259 bic r0, r0, #CACHE_DLINESIZE - 1
2601: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 2741: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
261 add r0, r0, #CACHE_DLINESIZE 275 add r0, r0, #CACHE_DLINESIZE
262 cmp r0, r1 276 cmp r0, r1
@@ -264,6 +278,22 @@ ENTRY(feroceon_dma_inv_range)
264 mcr p15, 0, r0, c7, c10, 4 @ drain WB 278 mcr p15, 0, r0, c7, c10, 4 @ drain WB
265 mov pc, lr 279 mov pc, lr
266 280
281 .align 5
282ENTRY(feroceon_range_dma_inv_range)
283 mrs r2, cpsr
284 tst r0, #CACHE_DLINESIZE - 1
285 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
286 tst r1, #CACHE_DLINESIZE - 1
287 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
288 cmp r1, r0
289 subne r1, r1, #1 @ top address is inclusive
290 orr r3, r2, #PSR_I_BIT
291 msr cpsr_c, r3 @ disable interrupts
292 mcr p15, 5, r0, c15, c14, 0 @ D inv range start
293 mcr p15, 5, r1, c15, c14, 1 @ D inv range top
294 msr cpsr_c, r2 @ restore interrupts
295 mov pc, lr
296
267/* 297/*
268 * dma_clean_range(start, end) 298 * dma_clean_range(start, end)
269 * 299 *
@@ -284,6 +314,19 @@ ENTRY(feroceon_dma_clean_range)
284 mcr p15, 0, r0, c7, c10, 4 @ drain WB 314 mcr p15, 0, r0, c7, c10, 4 @ drain WB
285 mov pc, lr 315 mov pc, lr
286 316
317 .align 5
318ENTRY(feroceon_range_dma_clean_range)
319 mrs r2, cpsr
320 cmp r1, r0
321 subne r1, r1, #1 @ top address is inclusive
322 orr r3, r2, #PSR_I_BIT
323 msr cpsr_c, r3 @ disable interrupts
324 mcr p15, 5, r0, c15, c13, 0 @ D clean range start
325 mcr p15, 5, r1, c15, c13, 1 @ D clean range top
326 msr cpsr_c, r2 @ restore interrupts
327 mcr p15, 0, r0, c7, c10, 4 @ drain WB
328 mov pc, lr
329
287/* 330/*
288 * dma_flush_range(start, end) 331 * dma_flush_range(start, end)
289 * 332 *
@@ -302,6 +345,19 @@ ENTRY(feroceon_dma_flush_range)
302 mcr p15, 0, r0, c7, c10, 4 @ drain WB 345 mcr p15, 0, r0, c7, c10, 4 @ drain WB
303 mov pc, lr 346 mov pc, lr
304 347
348 .align 5
349ENTRY(feroceon_range_dma_flush_range)
350 mrs r2, cpsr
351 cmp r1, r0
352 subne r1, r1, #1 @ top address is inclusive
353 orr r3, r2, #PSR_I_BIT
354 msr cpsr_c, r3 @ disable interrupts
355 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
356 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
357 msr cpsr_c, r2 @ restore interrupts
358 mcr p15, 0, r0, c7, c10, 4 @ drain WB
359 mov pc, lr
360
305ENTRY(feroceon_cache_fns) 361ENTRY(feroceon_cache_fns)
306 .long feroceon_flush_kern_cache_all 362 .long feroceon_flush_kern_cache_all
307 .long feroceon_flush_user_cache_all 363 .long feroceon_flush_user_cache_all
@@ -313,6 +369,17 @@ ENTRY(feroceon_cache_fns)
313 .long feroceon_dma_clean_range 369 .long feroceon_dma_clean_range
314 .long feroceon_dma_flush_range 370 .long feroceon_dma_flush_range
315 371
372ENTRY(feroceon_range_cache_fns)
373 .long feroceon_flush_kern_cache_all
374 .long feroceon_flush_user_cache_all
375 .long feroceon_flush_user_cache_range
376 .long feroceon_coherent_kern_range
377 .long feroceon_coherent_user_range
378 .long feroceon_range_flush_kern_dcache_page
379 .long feroceon_range_dma_inv_range
380 .long feroceon_range_dma_clean_range
381 .long feroceon_range_dma_flush_range
382
316 .align 5 383 .align 5
317ENTRY(cpu_feroceon_dcache_clean_area) 384ENTRY(cpu_feroceon_dcache_clean_area)
3181: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3851: mcr p15, 0, r0, c7, c10, 1 @ clean D entry