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authorRussell King <rmk+kernel@arm.linux.org.uk>2009-11-26 11:24:19 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-02-15 10:22:23 -0500
commit702b94bff3c50542a6e4ab9a4f4cef093262fe65 (patch)
tree2ae468b08de2aeb0e65ab3830c40c7a84dbbdb5e /arch/arm/mm
parenta9c9147eb9b1dba0ce567a41897c7773b4d1b0bc (diff)
ARM: dma-mapping: remove dmac_clean_range and dmac_inv_range
These are now unused, and so can be removed. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-By: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/cache-fa.S6
-rw-r--r--arch/arm/mm/cache-v3.S29
-rw-r--r--arch/arm/mm/cache-v4.S29
-rw-r--r--arch/arm/mm/cache-v4wb.S6
-rw-r--r--arch/arm/mm/cache-v4wt.S15
-rw-r--r--arch/arm/mm/cache-v6.S6
-rw-r--r--arch/arm/mm/cache-v7.S6
-rw-r--r--arch/arm/mm/proc-arm1020.S6
-rw-r--r--arch/arm/mm/proc-arm1020e.S6
-rw-r--r--arch/arm/mm/proc-arm1022.S6
-rw-r--r--arch/arm/mm/proc-arm1026.S6
-rw-r--r--arch/arm/mm/proc-arm920.S6
-rw-r--r--arch/arm/mm/proc-arm922.S6
-rw-r--r--arch/arm/mm/proc-arm925.S6
-rw-r--r--arch/arm/mm/proc-arm926.S6
-rw-r--r--arch/arm/mm/proc-arm940.S6
-rw-r--r--arch/arm/mm/proc-arm946.S6
-rw-r--r--arch/arm/mm/proc-feroceon.S12
-rw-r--r--arch/arm/mm/proc-mohawk.S6
-rw-r--r--arch/arm/mm/proc-xsc3.S6
-rw-r--r--arch/arm/mm/proc-xscale.S8
21 files changed, 41 insertions, 148 deletions
diff --git a/arch/arm/mm/cache-fa.S b/arch/arm/mm/cache-fa.S
index 8ebffdd6fcff..7148e53e6078 100644
--- a/arch/arm/mm/cache-fa.S
+++ b/arch/arm/mm/cache-fa.S
@@ -157,7 +157,7 @@ ENTRY(fa_flush_kern_dcache_area)
157 * - start - virtual start address 157 * - start - virtual start address
158 * - end - virtual end address 158 * - end - virtual end address
159 */ 159 */
160ENTRY(fa_dma_inv_range) 160fa_dma_inv_range:
161 tst r0, #CACHE_DLINESIZE - 1 161 tst r0, #CACHE_DLINESIZE - 1
162 bic r0, r0, #CACHE_DLINESIZE - 1 162 bic r0, r0, #CACHE_DLINESIZE - 1
163 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry 163 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
@@ -180,7 +180,7 @@ ENTRY(fa_dma_inv_range)
180 * - start - virtual start address 180 * - start - virtual start address
181 * - end - virtual end address 181 * - end - virtual end address
182 */ 182 */
183ENTRY(fa_dma_clean_range) 183fa_dma_clean_range:
184 bic r0, r0, #CACHE_DLINESIZE - 1 184 bic r0, r0, #CACHE_DLINESIZE - 1
1851: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 1851: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
186 add r0, r0, #CACHE_DLINESIZE 186 add r0, r0, #CACHE_DLINESIZE
@@ -241,7 +241,5 @@ ENTRY(fa_cache_fns)
241 .long fa_flush_kern_dcache_area 241 .long fa_flush_kern_dcache_area
242 .long fa_dma_map_area 242 .long fa_dma_map_area
243 .long fa_dma_unmap_area 243 .long fa_dma_unmap_area
244 .long fa_dma_inv_range
245 .long fa_dma_clean_range
246 .long fa_dma_flush_range 244 .long fa_dma_flush_range
247 .size fa_cache_fns, . - fa_cache_fns 245 .size fa_cache_fns, . - fa_cache_fns
diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S
index 6df52dc014be..c2ff3c599fee 100644
--- a/arch/arm/mm/cache-v3.S
+++ b/arch/arm/mm/cache-v3.S
@@ -84,20 +84,6 @@ ENTRY(v3_flush_kern_dcache_area)
84 /* FALLTHROUGH */ 84 /* FALLTHROUGH */
85 85
86/* 86/*
87 * dma_inv_range(start, end)
88 *
89 * Invalidate (discard) the specified virtual address range.
90 * May not write back any entries. If 'start' or 'end'
91 * are not cache line aligned, those lines must be written
92 * back.
93 *
94 * - start - virtual start address
95 * - end - virtual end address
96 */
97ENTRY(v3_dma_inv_range)
98 /* FALLTHROUGH */
99
100/*
101 * dma_flush_range(start, end) 87 * dma_flush_range(start, end)
102 * 88 *
103 * Clean and invalidate the specified virtual address range. 89 * Clean and invalidate the specified virtual address range.
@@ -108,17 +94,6 @@ ENTRY(v3_dma_inv_range)
108ENTRY(v3_dma_flush_range) 94ENTRY(v3_dma_flush_range)
109 mov r0, #0 95 mov r0, #0
110 mcr p15, 0, r0, c7, c0, 0 @ flush ID cache 96 mcr p15, 0, r0, c7, c0, 0 @ flush ID cache
111 /* FALLTHROUGH */
112
113/*
114 * dma_clean_range(start, end)
115 *
116 * Clean (write back) the specified virtual address range.
117 *
118 * - start - virtual start address
119 * - end - virtual end address
120 */
121ENTRY(v3_dma_clean_range)
122 mov pc, lr 97 mov pc, lr
123 98
124/* 99/*
@@ -129,7 +104,7 @@ ENTRY(v3_dma_clean_range)
129 */ 104 */
130ENTRY(v3_dma_unmap_area) 105ENTRY(v3_dma_unmap_area)
131 teq r2, #DMA_TO_DEVICE 106 teq r2, #DMA_TO_DEVICE
132 bne v3_dma_inv_range 107 bne v3_dma_flush_range
133 /* FALLTHROUGH */ 108 /* FALLTHROUGH */
134 109
135/* 110/*
@@ -155,7 +130,5 @@ ENTRY(v3_cache_fns)
155 .long v3_flush_kern_dcache_area 130 .long v3_flush_kern_dcache_area
156 .long v3_dma_map_area 131 .long v3_dma_map_area
157 .long v3_dma_unmap_area 132 .long v3_dma_unmap_area
158 .long v3_dma_inv_range
159 .long v3_dma_clean_range
160 .long v3_dma_flush_range 133 .long v3_dma_flush_range
161 .size v3_cache_fns, . - v3_cache_fns 134 .size v3_cache_fns, . - v3_cache_fns
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index df3b423713b9..4810f7e3e813 100644
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -94,20 +94,6 @@ ENTRY(v4_flush_kern_dcache_area)
94 /* FALLTHROUGH */ 94 /* FALLTHROUGH */
95 95
96/* 96/*
97 * dma_inv_range(start, end)
98 *
99 * Invalidate (discard) the specified virtual address range.
100 * May not write back any entries. If 'start' or 'end'
101 * are not cache line aligned, those lines must be written
102 * back.
103 *
104 * - start - virtual start address
105 * - end - virtual end address
106 */
107ENTRY(v4_dma_inv_range)
108 /* FALLTHROUGH */
109
110/*
111 * dma_flush_range(start, end) 97 * dma_flush_range(start, end)
112 * 98 *
113 * Clean and invalidate the specified virtual address range. 99 * Clean and invalidate the specified virtual address range.
@@ -120,17 +106,6 @@ ENTRY(v4_dma_flush_range)
120 mov r0, #0 106 mov r0, #0
121 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache 107 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
122#endif 108#endif
123 /* FALLTHROUGH */
124
125/*
126 * dma_clean_range(start, end)
127 *
128 * Clean (write back) the specified virtual address range.
129 *
130 * - start - virtual start address
131 * - end - virtual end address
132 */
133ENTRY(v4_dma_clean_range)
134 mov pc, lr 109 mov pc, lr
135 110
136/* 111/*
@@ -141,7 +116,7 @@ ENTRY(v4_dma_clean_range)
141 */ 116 */
142ENTRY(v4_dma_unmap_area) 117ENTRY(v4_dma_unmap_area)
143 teq r2, #DMA_TO_DEVICE 118 teq r2, #DMA_TO_DEVICE
144 bne v4_dma_inv_range 119 bne v4_dma_flush_range
145 /* FALLTHROUGH */ 120 /* FALLTHROUGH */
146 121
147/* 122/*
@@ -167,7 +142,5 @@ ENTRY(v4_cache_fns)
167 .long v4_flush_kern_dcache_area 142 .long v4_flush_kern_dcache_area
168 .long v4_dma_map_area 143 .long v4_dma_map_area
169 .long v4_dma_unmap_area 144 .long v4_dma_unmap_area
170 .long v4_dma_inv_range
171 .long v4_dma_clean_range
172 .long v4_dma_flush_range 145 .long v4_dma_flush_range
173 .size v4_cache_fns, . - v4_cache_fns 146 .size v4_cache_fns, . - v4_cache_fns
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index 32e7a7448496..df8368afa102 100644
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -173,7 +173,7 @@ ENTRY(v4wb_coherent_user_range)
173 * - start - virtual start address 173 * - start - virtual start address
174 * - end - virtual end address 174 * - end - virtual end address
175 */ 175 */
176ENTRY(v4wb_dma_inv_range) 176v4wb_dma_inv_range:
177 tst r0, #CACHE_DLINESIZE - 1 177 tst r0, #CACHE_DLINESIZE - 1
178 bic r0, r0, #CACHE_DLINESIZE - 1 178 bic r0, r0, #CACHE_DLINESIZE - 1
179 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 179 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -194,7 +194,7 @@ ENTRY(v4wb_dma_inv_range)
194 * - start - virtual start address 194 * - start - virtual start address
195 * - end - virtual end address 195 * - end - virtual end address
196 */ 196 */
197ENTRY(v4wb_dma_clean_range) 197v4wb_dma_clean_range:
198 bic r0, r0, #CACHE_DLINESIZE - 1 198 bic r0, r0, #CACHE_DLINESIZE - 1
1991: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 1991: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
200 add r0, r0, #CACHE_DLINESIZE 200 add r0, r0, #CACHE_DLINESIZE
@@ -252,7 +252,5 @@ ENTRY(v4wb_cache_fns)
252 .long v4wb_flush_kern_dcache_area 252 .long v4wb_flush_kern_dcache_area
253 .long v4wb_dma_map_area 253 .long v4wb_dma_map_area
254 .long v4wb_dma_unmap_area 254 .long v4wb_dma_unmap_area
255 .long v4wb_dma_inv_range
256 .long v4wb_dma_clean_range
257 .long v4wb_dma_flush_range 255 .long v4wb_dma_flush_range
258 .size v4wb_cache_fns, . - v4wb_cache_fns 256 .size v4wb_cache_fns, . - v4wb_cache_fns
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index 3d8dad5b2650..45c70312f43b 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -142,23 +142,12 @@ ENTRY(v4wt_flush_kern_dcache_area)
142 * - start - virtual start address 142 * - start - virtual start address
143 * - end - virtual end address 143 * - end - virtual end address
144 */ 144 */
145ENTRY(v4wt_dma_inv_range) 145v4wt_dma_inv_range:
146 bic r0, r0, #CACHE_DLINESIZE - 1 146 bic r0, r0, #CACHE_DLINESIZE - 1
1471: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 1471: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
148 add r0, r0, #CACHE_DLINESIZE 148 add r0, r0, #CACHE_DLINESIZE
149 cmp r0, r1 149 cmp r0, r1
150 blo 1b 150 blo 1b
151 /* FALLTHROUGH */
152
153/*
154 * dma_clean_range(start, end)
155 *
156 * Clean the specified virtual address range.
157 *
158 * - start - virtual start address
159 * - end - virtual end address
160 */
161ENTRY(v4wt_dma_clean_range)
162 mov pc, lr 151 mov pc, lr
163 152
164/* 153/*
@@ -207,7 +196,5 @@ ENTRY(v4wt_cache_fns)
207 .long v4wt_flush_kern_dcache_area 196 .long v4wt_flush_kern_dcache_area
208 .long v4wt_dma_map_area 197 .long v4wt_dma_map_area
209 .long v4wt_dma_unmap_area 198 .long v4wt_dma_unmap_area
210 .long v4wt_dma_inv_range
211 .long v4wt_dma_clean_range
212 .long v4wt_dma_flush_range 199 .long v4wt_dma_flush_range
213 .size v4wt_cache_fns, . - v4wt_cache_fns 200 .size v4wt_cache_fns, . - v4wt_cache_fns
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 6f926dd0e0f7..a11934e53fbd 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -195,7 +195,7 @@ ENTRY(v6_flush_kern_dcache_area)
195 * - start - virtual start address of region 195 * - start - virtual start address of region
196 * - end - virtual end address of region 196 * - end - virtual end address of region
197 */ 197 */
198ENTRY(v6_dma_inv_range) 198v6_dma_inv_range:
199 tst r0, #D_CACHE_LINE_SIZE - 1 199 tst r0, #D_CACHE_LINE_SIZE - 1
200 bic r0, r0, #D_CACHE_LINE_SIZE - 1 200 bic r0, r0, #D_CACHE_LINE_SIZE - 1
201#ifdef HARVARD_CACHE 201#ifdef HARVARD_CACHE
@@ -228,7 +228,7 @@ ENTRY(v6_dma_inv_range)
228 * - start - virtual start address of region 228 * - start - virtual start address of region
229 * - end - virtual end address of region 229 * - end - virtual end address of region
230 */ 230 */
231ENTRY(v6_dma_clean_range) 231v6_dma_clean_range:
232 bic r0, r0, #D_CACHE_LINE_SIZE - 1 232 bic r0, r0, #D_CACHE_LINE_SIZE - 1
2331: 2331:
234#ifdef HARVARD_CACHE 234#ifdef HARVARD_CACHE
@@ -299,7 +299,5 @@ ENTRY(v6_cache_fns)
299 .long v6_flush_kern_dcache_area 299 .long v6_flush_kern_dcache_area
300 .long v6_dma_map_area 300 .long v6_dma_map_area
301 .long v6_dma_unmap_area 301 .long v6_dma_unmap_area
302 .long v6_dma_inv_range
303 .long v6_dma_clean_range
304 .long v6_dma_flush_range 302 .long v6_dma_flush_range
305 .size v6_cache_fns, . - v6_cache_fns 303 .size v6_cache_fns, . - v6_cache_fns
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index e30d8bc67182..b1cd0fd91207 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -216,7 +216,7 @@ ENDPROC(v7_flush_kern_dcache_area)
216 * - start - virtual start address of region 216 * - start - virtual start address of region
217 * - end - virtual end address of region 217 * - end - virtual end address of region
218 */ 218 */
219ENTRY(v7_dma_inv_range) 219v7_dma_inv_range:
220 dcache_line_size r2, r3 220 dcache_line_size r2, r3
221 sub r3, r2, #1 221 sub r3, r2, #1
222 tst r0, r3 222 tst r0, r3
@@ -240,7 +240,7 @@ ENDPROC(v7_dma_inv_range)
240 * - start - virtual start address of region 240 * - start - virtual start address of region
241 * - end - virtual end address of region 241 * - end - virtual end address of region
242 */ 242 */
243ENTRY(v7_dma_clean_range) 243v7_dma_clean_range:
244 dcache_line_size r2, r3 244 dcache_line_size r2, r3
245 sub r3, r2, #1 245 sub r3, r2, #1
246 bic r0, r0, r3 246 bic r0, r0, r3
@@ -307,7 +307,5 @@ ENTRY(v7_cache_fns)
307 .long v7_flush_kern_dcache_area 307 .long v7_flush_kern_dcache_area
308 .long v7_dma_map_area 308 .long v7_dma_map_area
309 .long v7_dma_unmap_area 309 .long v7_dma_unmap_area
310 .long v7_dma_inv_range
311 .long v7_dma_clean_range
312 .long v7_dma_flush_range 310 .long v7_dma_flush_range
313 .size v7_cache_fns, . - v7_cache_fns 311 .size v7_cache_fns, . - v7_cache_fns
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index c85f5eb42634..72507c630ceb 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -265,7 +265,7 @@ ENTRY(arm1020_flush_kern_dcache_area)
265 * 265 *
266 * (same as v4wb) 266 * (same as v4wb)
267 */ 267 */
268ENTRY(arm1020_dma_inv_range) 268arm1020_dma_inv_range:
269 mov ip, #0 269 mov ip, #0
270#ifndef CONFIG_CPU_DCACHE_DISABLE 270#ifndef CONFIG_CPU_DCACHE_DISABLE
271 tst r0, #CACHE_DLINESIZE - 1 271 tst r0, #CACHE_DLINESIZE - 1
@@ -295,7 +295,7 @@ ENTRY(arm1020_dma_inv_range)
295 * 295 *
296 * (same as v4wb) 296 * (same as v4wb)
297 */ 297 */
298ENTRY(arm1020_dma_clean_range) 298arm1020_dma_clean_range:
299 mov ip, #0 299 mov ip, #0
300#ifndef CONFIG_CPU_DCACHE_DISABLE 300#ifndef CONFIG_CPU_DCACHE_DISABLE
301 bic r0, r0, #CACHE_DLINESIZE - 1 301 bic r0, r0, #CACHE_DLINESIZE - 1
@@ -363,8 +363,6 @@ ENTRY(arm1020_cache_fns)
363 .long arm1020_flush_kern_dcache_area 363 .long arm1020_flush_kern_dcache_area
364 .long arm1020_dma_map_area 364 .long arm1020_dma_map_area
365 .long arm1020_dma_unmap_area 365 .long arm1020_dma_unmap_area
366 .long arm1020_dma_inv_range
367 .long arm1020_dma_clean_range
368 .long arm1020_dma_flush_range 366 .long arm1020_dma_flush_range
369 367
370 .align 5 368 .align 5
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 5a3cf7620a2c..d27829805609 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -258,7 +258,7 @@ ENTRY(arm1020e_flush_kern_dcache_area)
258 * 258 *
259 * (same as v4wb) 259 * (same as v4wb)
260 */ 260 */
261ENTRY(arm1020e_dma_inv_range) 261arm1020e_dma_inv_range:
262 mov ip, #0 262 mov ip, #0
263#ifndef CONFIG_CPU_DCACHE_DISABLE 263#ifndef CONFIG_CPU_DCACHE_DISABLE
264 tst r0, #CACHE_DLINESIZE - 1 264 tst r0, #CACHE_DLINESIZE - 1
@@ -284,7 +284,7 @@ ENTRY(arm1020e_dma_inv_range)
284 * 284 *
285 * (same as v4wb) 285 * (same as v4wb)
286 */ 286 */
287ENTRY(arm1020e_dma_clean_range) 287arm1020e_dma_clean_range:
288 mov ip, #0 288 mov ip, #0
289#ifndef CONFIG_CPU_DCACHE_DISABLE 289#ifndef CONFIG_CPU_DCACHE_DISABLE
290 bic r0, r0, #CACHE_DLINESIZE - 1 290 bic r0, r0, #CACHE_DLINESIZE - 1
@@ -349,8 +349,6 @@ ENTRY(arm1020e_cache_fns)
349 .long arm1020e_flush_kern_dcache_area 349 .long arm1020e_flush_kern_dcache_area
350 .long arm1020e_dma_map_area 350 .long arm1020e_dma_map_area
351 .long arm1020e_dma_unmap_area 351 .long arm1020e_dma_unmap_area
352 .long arm1020e_dma_inv_range
353 .long arm1020e_dma_clean_range
354 .long arm1020e_dma_flush_range 352 .long arm1020e_dma_flush_range
355 353
356 .align 5 354 .align 5
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index fec8f5878438..ce13e4a827de 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -247,7 +247,7 @@ ENTRY(arm1022_flush_kern_dcache_area)
247 * 247 *
248 * (same as v4wb) 248 * (same as v4wb)
249 */ 249 */
250ENTRY(arm1022_dma_inv_range) 250arm1022_dma_inv_range:
251 mov ip, #0 251 mov ip, #0
252#ifndef CONFIG_CPU_DCACHE_DISABLE 252#ifndef CONFIG_CPU_DCACHE_DISABLE
253 tst r0, #CACHE_DLINESIZE - 1 253 tst r0, #CACHE_DLINESIZE - 1
@@ -273,7 +273,7 @@ ENTRY(arm1022_dma_inv_range)
273 * 273 *
274 * (same as v4wb) 274 * (same as v4wb)
275 */ 275 */
276ENTRY(arm1022_dma_clean_range) 276arm1022_dma_clean_range:
277 mov ip, #0 277 mov ip, #0
278#ifndef CONFIG_CPU_DCACHE_DISABLE 278#ifndef CONFIG_CPU_DCACHE_DISABLE
279 bic r0, r0, #CACHE_DLINESIZE - 1 279 bic r0, r0, #CACHE_DLINESIZE - 1
@@ -338,8 +338,6 @@ ENTRY(arm1022_cache_fns)
338 .long arm1022_flush_kern_dcache_area 338 .long arm1022_flush_kern_dcache_area
339 .long arm1022_dma_map_area 339 .long arm1022_dma_map_area
340 .long arm1022_dma_unmap_area 340 .long arm1022_dma_unmap_area
341 .long arm1022_dma_inv_range
342 .long arm1022_dma_clean_range
343 .long arm1022_dma_flush_range 341 .long arm1022_dma_flush_range
344 342
345 .align 5 343 .align 5
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 9ece6f666497..636672a29c6d 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -241,7 +241,7 @@ ENTRY(arm1026_flush_kern_dcache_area)
241 * 241 *
242 * (same as v4wb) 242 * (same as v4wb)
243 */ 243 */
244ENTRY(arm1026_dma_inv_range) 244arm1026_dma_inv_range:
245 mov ip, #0 245 mov ip, #0
246#ifndef CONFIG_CPU_DCACHE_DISABLE 246#ifndef CONFIG_CPU_DCACHE_DISABLE
247 tst r0, #CACHE_DLINESIZE - 1 247 tst r0, #CACHE_DLINESIZE - 1
@@ -267,7 +267,7 @@ ENTRY(arm1026_dma_inv_range)
267 * 267 *
268 * (same as v4wb) 268 * (same as v4wb)
269 */ 269 */
270ENTRY(arm1026_dma_clean_range) 270arm1026_dma_clean_range:
271 mov ip, #0 271 mov ip, #0
272#ifndef CONFIG_CPU_DCACHE_DISABLE 272#ifndef CONFIG_CPU_DCACHE_DISABLE
273 bic r0, r0, #CACHE_DLINESIZE - 1 273 bic r0, r0, #CACHE_DLINESIZE - 1
@@ -332,8 +332,6 @@ ENTRY(arm1026_cache_fns)
332 .long arm1026_flush_kern_dcache_area 332 .long arm1026_flush_kern_dcache_area
333 .long arm1026_dma_map_area 333 .long arm1026_dma_map_area
334 .long arm1026_dma_unmap_area 334 .long arm1026_dma_unmap_area
335 .long arm1026_dma_inv_range
336 .long arm1026_dma_clean_range
337 .long arm1026_dma_flush_range 335 .long arm1026_dma_flush_range
338 336
339 .align 5 337 .align 5
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 6f6ab2747da6..8be81992645d 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -239,7 +239,7 @@ ENTRY(arm920_flush_kern_dcache_area)
239 * 239 *
240 * (same as v4wb) 240 * (same as v4wb)
241 */ 241 */
242ENTRY(arm920_dma_inv_range) 242arm920_dma_inv_range:
243 tst r0, #CACHE_DLINESIZE - 1 243 tst r0, #CACHE_DLINESIZE - 1
244 bic r0, r0, #CACHE_DLINESIZE - 1 244 bic r0, r0, #CACHE_DLINESIZE - 1
245 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 245 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -262,7 +262,7 @@ ENTRY(arm920_dma_inv_range)
262 * 262 *
263 * (same as v4wb) 263 * (same as v4wb)
264 */ 264 */
265ENTRY(arm920_dma_clean_range) 265arm920_dma_clean_range:
266 bic r0, r0, #CACHE_DLINESIZE - 1 266 bic r0, r0, #CACHE_DLINESIZE - 1
2671: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2671: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
268 add r0, r0, #CACHE_DLINESIZE 268 add r0, r0, #CACHE_DLINESIZE
@@ -321,8 +321,6 @@ ENTRY(arm920_cache_fns)
321 .long arm920_flush_kern_dcache_area 321 .long arm920_flush_kern_dcache_area
322 .long arm920_dma_map_area 322 .long arm920_dma_map_area
323 .long arm920_dma_unmap_area 323 .long arm920_dma_unmap_area
324 .long arm920_dma_inv_range
325 .long arm920_dma_clean_range
326 .long arm920_dma_flush_range 324 .long arm920_dma_flush_range
327 325
328#endif 326#endif
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 4e4396b121ca..c0ff8e4b1074 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -241,7 +241,7 @@ ENTRY(arm922_flush_kern_dcache_area)
241 * 241 *
242 * (same as v4wb) 242 * (same as v4wb)
243 */ 243 */
244ENTRY(arm922_dma_inv_range) 244arm922_dma_inv_range:
245 tst r0, #CACHE_DLINESIZE - 1 245 tst r0, #CACHE_DLINESIZE - 1
246 bic r0, r0, #CACHE_DLINESIZE - 1 246 bic r0, r0, #CACHE_DLINESIZE - 1
247 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 247 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -264,7 +264,7 @@ ENTRY(arm922_dma_inv_range)
264 * 264 *
265 * (same as v4wb) 265 * (same as v4wb)
266 */ 266 */
267ENTRY(arm922_dma_clean_range) 267arm922_dma_clean_range:
268 bic r0, r0, #CACHE_DLINESIZE - 1 268 bic r0, r0, #CACHE_DLINESIZE - 1
2691: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2691: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
270 add r0, r0, #CACHE_DLINESIZE 270 add r0, r0, #CACHE_DLINESIZE
@@ -323,8 +323,6 @@ ENTRY(arm922_cache_fns)
323 .long arm922_flush_kern_dcache_area 323 .long arm922_flush_kern_dcache_area
324 .long arm922_dma_map_area 324 .long arm922_dma_map_area
325 .long arm922_dma_unmap_area 325 .long arm922_dma_unmap_area
326 .long arm922_dma_inv_range
327 .long arm922_dma_clean_range
328 .long arm922_dma_flush_range 326 .long arm922_dma_flush_range
329 327
330#endif 328#endif
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 7c01c5d1108c..3c6cffe400f6 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -283,7 +283,7 @@ ENTRY(arm925_flush_kern_dcache_area)
283 * 283 *
284 * (same as v4wb) 284 * (same as v4wb)
285 */ 285 */
286ENTRY(arm925_dma_inv_range) 286arm925_dma_inv_range:
287#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 287#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
288 tst r0, #CACHE_DLINESIZE - 1 288 tst r0, #CACHE_DLINESIZE - 1
289 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 289 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -308,7 +308,7 @@ ENTRY(arm925_dma_inv_range)
308 * 308 *
309 * (same as v4wb) 309 * (same as v4wb)
310 */ 310 */
311ENTRY(arm925_dma_clean_range) 311arm925_dma_clean_range:
312#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 312#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
313 bic r0, r0, #CACHE_DLINESIZE - 1 313 bic r0, r0, #CACHE_DLINESIZE - 1
3141: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3141: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -374,8 +374,6 @@ ENTRY(arm925_cache_fns)
374 .long arm925_flush_kern_dcache_area 374 .long arm925_flush_kern_dcache_area
375 .long arm925_dma_map_area 375 .long arm925_dma_map_area
376 .long arm925_dma_unmap_area 376 .long arm925_dma_unmap_area
377 .long arm925_dma_inv_range
378 .long arm925_dma_clean_range
379 .long arm925_dma_flush_range 377 .long arm925_dma_flush_range
380 378
381ENTRY(cpu_arm925_dcache_clean_area) 379ENTRY(cpu_arm925_dcache_clean_area)
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 72a01a4b80ab..75b707c9cce1 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -246,7 +246,7 @@ ENTRY(arm926_flush_kern_dcache_area)
246 * 246 *
247 * (same as v4wb) 247 * (same as v4wb)
248 */ 248 */
249ENTRY(arm926_dma_inv_range) 249arm926_dma_inv_range:
250#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 250#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
251 tst r0, #CACHE_DLINESIZE - 1 251 tst r0, #CACHE_DLINESIZE - 1
252 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 252 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -271,7 +271,7 @@ ENTRY(arm926_dma_inv_range)
271 * 271 *
272 * (same as v4wb) 272 * (same as v4wb)
273 */ 273 */
274ENTRY(arm926_dma_clean_range) 274arm926_dma_clean_range:
275#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 275#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
276 bic r0, r0, #CACHE_DLINESIZE - 1 276 bic r0, r0, #CACHE_DLINESIZE - 1
2771: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2771: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -337,8 +337,6 @@ ENTRY(arm926_cache_fns)
337 .long arm926_flush_kern_dcache_area 337 .long arm926_flush_kern_dcache_area
338 .long arm926_dma_map_area 338 .long arm926_dma_map_area
339 .long arm926_dma_unmap_area 339 .long arm926_dma_unmap_area
340 .long arm926_dma_inv_range
341 .long arm926_dma_clean_range
342 .long arm926_dma_flush_range 340 .long arm926_dma_flush_range
343 341
344ENTRY(cpu_arm926_dcache_clean_area) 342ENTRY(cpu_arm926_dcache_clean_area)
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 6bb58fca7270..1af1657819eb 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -171,7 +171,7 @@ ENTRY(arm940_flush_kern_dcache_area)
171 * - start - virtual start address 171 * - start - virtual start address
172 * - end - virtual end address 172 * - end - virtual end address
173 */ 173 */
174ENTRY(arm940_dma_inv_range) 174arm940_dma_inv_range:
175 mov ip, #0 175 mov ip, #0
176 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments 176 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
1771: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 1771: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
@@ -192,7 +192,7 @@ ENTRY(arm940_dma_inv_range)
192 * - start - virtual start address 192 * - start - virtual start address
193 * - end - virtual end address 193 * - end - virtual end address
194 */ 194 */
195ENTRY(arm940_dma_clean_range) 195arm940_dma_clean_range:
196ENTRY(cpu_arm940_dcache_clean_area) 196ENTRY(cpu_arm940_dcache_clean_area)
197 mov ip, #0 197 mov ip, #0
198#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 198#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
@@ -266,8 +266,6 @@ ENTRY(arm940_cache_fns)
266 .long arm940_flush_kern_dcache_area 266 .long arm940_flush_kern_dcache_area
267 .long arm940_dma_map_area 267 .long arm940_dma_map_area
268 .long arm940_dma_unmap_area 268 .long arm940_dma_unmap_area
269 .long arm940_dma_inv_range
270 .long arm940_dma_clean_range
271 .long arm940_dma_flush_range 269 .long arm940_dma_flush_range
272 270
273 __INIT 271 __INIT
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index ac0f9ba719d7..1664b6aaff79 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -215,7 +215,7 @@ ENTRY(arm946_flush_kern_dcache_area)
215 * - end - virtual end address 215 * - end - virtual end address
216 * (same as arm926) 216 * (same as arm926)
217 */ 217 */
218ENTRY(arm946_dma_inv_range) 218arm946_dma_inv_range:
219#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 219#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
220 tst r0, #CACHE_DLINESIZE - 1 220 tst r0, #CACHE_DLINESIZE - 1
221 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 221 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -240,7 +240,7 @@ ENTRY(arm946_dma_inv_range)
240 * 240 *
241 * (same as arm926) 241 * (same as arm926)
242 */ 242 */
243ENTRY(arm946_dma_clean_range) 243arm946_dma_clean_range:
244#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 244#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
245 bic r0, r0, #CACHE_DLINESIZE - 1 245 bic r0, r0, #CACHE_DLINESIZE - 1
2461: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2461: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -308,8 +308,6 @@ ENTRY(arm946_cache_fns)
308 .long arm946_flush_kern_dcache_area 308 .long arm946_flush_kern_dcache_area
309 .long arm946_dma_map_area 309 .long arm946_dma_map_area
310 .long arm946_dma_unmap_area 310 .long arm946_dma_unmap_area
311 .long arm946_dma_inv_range
312 .long arm946_dma_clean_range
313 .long arm946_dma_flush_range 311 .long arm946_dma_flush_range
314 312
315 313
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index 97e1d784f152..53e632343849 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -274,7 +274,7 @@ ENTRY(feroceon_range_flush_kern_dcache_area)
274 * (same as v4wb) 274 * (same as v4wb)
275 */ 275 */
276 .align 5 276 .align 5
277ENTRY(feroceon_dma_inv_range) 277feroceon_dma_inv_range:
278 tst r0, #CACHE_DLINESIZE - 1 278 tst r0, #CACHE_DLINESIZE - 1
279 bic r0, r0, #CACHE_DLINESIZE - 1 279 bic r0, r0, #CACHE_DLINESIZE - 1
280 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 280 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -288,7 +288,7 @@ ENTRY(feroceon_dma_inv_range)
288 mov pc, lr 288 mov pc, lr
289 289
290 .align 5 290 .align 5
291ENTRY(feroceon_range_dma_inv_range) 291feroceon_range_dma_inv_range:
292 mrs r2, cpsr 292 mrs r2, cpsr
293 tst r0, #CACHE_DLINESIZE - 1 293 tst r0, #CACHE_DLINESIZE - 1
294 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 294 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -314,7 +314,7 @@ ENTRY(feroceon_range_dma_inv_range)
314 * (same as v4wb) 314 * (same as v4wb)
315 */ 315 */
316 .align 5 316 .align 5
317ENTRY(feroceon_dma_clean_range) 317feroceon_dma_clean_range:
318 bic r0, r0, #CACHE_DLINESIZE - 1 318 bic r0, r0, #CACHE_DLINESIZE - 1
3191: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3191: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
320 add r0, r0, #CACHE_DLINESIZE 320 add r0, r0, #CACHE_DLINESIZE
@@ -324,7 +324,7 @@ ENTRY(feroceon_dma_clean_range)
324 mov pc, lr 324 mov pc, lr
325 325
326 .align 5 326 .align 5
327ENTRY(feroceon_range_dma_clean_range) 327feroceon_range_dma_clean_range:
328 mrs r2, cpsr 328 mrs r2, cpsr
329 cmp r1, r0 329 cmp r1, r0
330 subne r1, r1, #1 @ top address is inclusive 330 subne r1, r1, #1 @ top address is inclusive
@@ -414,8 +414,6 @@ ENTRY(feroceon_cache_fns)
414 .long feroceon_flush_kern_dcache_area 414 .long feroceon_flush_kern_dcache_area
415 .long feroceon_dma_map_area 415 .long feroceon_dma_map_area
416 .long feroceon_dma_unmap_area 416 .long feroceon_dma_unmap_area
417 .long feroceon_dma_inv_range
418 .long feroceon_dma_clean_range
419 .long feroceon_dma_flush_range 417 .long feroceon_dma_flush_range
420 418
421ENTRY(feroceon_range_cache_fns) 419ENTRY(feroceon_range_cache_fns)
@@ -427,8 +425,6 @@ ENTRY(feroceon_range_cache_fns)
427 .long feroceon_range_flush_kern_dcache_area 425 .long feroceon_range_flush_kern_dcache_area
428 .long feroceon_range_dma_map_area 426 .long feroceon_range_dma_map_area
429 .long feroceon_dma_unmap_area 427 .long feroceon_dma_unmap_area
430 .long feroceon_range_dma_inv_range
431 .long feroceon_range_dma_clean_range
432 .long feroceon_range_dma_flush_range 428 .long feroceon_range_dma_flush_range
433 429
434 .align 5 430 .align 5
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index 55b7fbec6548..caa31154e7db 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -218,7 +218,7 @@ ENTRY(mohawk_flush_kern_dcache_area)
218 * 218 *
219 * (same as v4wb) 219 * (same as v4wb)
220 */ 220 */
221ENTRY(mohawk_dma_inv_range) 221mohawk_dma_inv_range:
222 tst r0, #CACHE_DLINESIZE - 1 222 tst r0, #CACHE_DLINESIZE - 1
223 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 223 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
224 tst r1, #CACHE_DLINESIZE - 1 224 tst r1, #CACHE_DLINESIZE - 1
@@ -241,7 +241,7 @@ ENTRY(mohawk_dma_inv_range)
241 * 241 *
242 * (same as v4wb) 242 * (same as v4wb)
243 */ 243 */
244ENTRY(mohawk_dma_clean_range) 244mohawk_dma_clean_range:
245 bic r0, r0, #CACHE_DLINESIZE - 1 245 bic r0, r0, #CACHE_DLINESIZE - 1
2461: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 2461: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
247 add r0, r0, #CACHE_DLINESIZE 247 add r0, r0, #CACHE_DLINESIZE
@@ -301,8 +301,6 @@ ENTRY(mohawk_cache_fns)
301 .long mohawk_flush_kern_dcache_area 301 .long mohawk_flush_kern_dcache_area
302 .long mohawk_dma_map_area 302 .long mohawk_dma_map_area
303 .long mohawk_dma_unmap_area 303 .long mohawk_dma_unmap_area
304 .long mohawk_dma_inv_range
305 .long mohawk_dma_clean_range
306 .long mohawk_dma_flush_range 304 .long mohawk_dma_flush_range
307 305
308ENTRY(cpu_mohawk_dcache_clean_area) 306ENTRY(cpu_mohawk_dcache_clean_area)
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 4e4ce889b3e6..046b3d88955e 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -257,7 +257,7 @@ ENTRY(xsc3_flush_kern_dcache_area)
257 * - start - virtual start address 257 * - start - virtual start address
258 * - end - virtual end address 258 * - end - virtual end address
259 */ 259 */
260ENTRY(xsc3_dma_inv_range) 260xsc3_dma_inv_range:
261 tst r0, #CACHELINESIZE - 1 261 tst r0, #CACHELINESIZE - 1
262 bic r0, r0, #CACHELINESIZE - 1 262 bic r0, r0, #CACHELINESIZE - 1
263 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line 263 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
@@ -278,7 +278,7 @@ ENTRY(xsc3_dma_inv_range)
278 * - start - virtual start address 278 * - start - virtual start address
279 * - end - virtual end address 279 * - end - virtual end address
280 */ 280 */
281ENTRY(xsc3_dma_clean_range) 281xsc3_dma_clean_range:
282 bic r0, r0, #CACHELINESIZE - 1 282 bic r0, r0, #CACHELINESIZE - 1
2831: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line 2831: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
284 add r0, r0, #CACHELINESIZE 284 add r0, r0, #CACHELINESIZE
@@ -337,8 +337,6 @@ ENTRY(xsc3_cache_fns)
337 .long xsc3_flush_kern_dcache_area 337 .long xsc3_flush_kern_dcache_area
338 .long xsc3_dma_map_area 338 .long xsc3_dma_map_area
339 .long xsc3_dma_unmap_area 339 .long xsc3_dma_unmap_area
340 .long xsc3_dma_inv_range
341 .long xsc3_dma_clean_range
342 .long xsc3_dma_flush_range 340 .long xsc3_dma_flush_range
343 341
344ENTRY(cpu_xsc3_dcache_clean_area) 342ENTRY(cpu_xsc3_dcache_clean_area)
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index a7999f94bf27..63037e2162f2 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -315,7 +315,7 @@ ENTRY(xscale_flush_kern_dcache_area)
315 * - start - virtual start address 315 * - start - virtual start address
316 * - end - virtual end address 316 * - end - virtual end address
317 */ 317 */
318ENTRY(xscale_dma_inv_range) 318xscale_dma_inv_range:
319 tst r0, #CACHELINESIZE - 1 319 tst r0, #CACHELINESIZE - 1
320 bic r0, r0, #CACHELINESIZE - 1 320 bic r0, r0, #CACHELINESIZE - 1
321 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 321 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -336,7 +336,7 @@ ENTRY(xscale_dma_inv_range)
336 * - start - virtual start address 336 * - start - virtual start address
337 * - end - virtual end address 337 * - end - virtual end address
338 */ 338 */
339ENTRY(xscale_dma_clean_range) 339xscale_dma_clean_range:
340 bic r0, r0, #CACHELINESIZE - 1 340 bic r0, r0, #CACHELINESIZE - 1
3411: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3411: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
342 add r0, r0, #CACHELINESIZE 342 add r0, r0, #CACHELINESIZE
@@ -409,8 +409,6 @@ ENTRY(xscale_cache_fns)
409 .long xscale_flush_kern_dcache_area 409 .long xscale_flush_kern_dcache_area
410 .long xscale_dma_map_area 410 .long xscale_dma_map_area
411 .long xscale_dma_unmap_area 411 .long xscale_dma_unmap_area
412 .long xscale_dma_inv_range
413 .long xscale_dma_clean_range
414 .long xscale_dma_flush_range 412 .long xscale_dma_flush_range
415 413
416/* 414/*
@@ -436,8 +434,6 @@ ENTRY(xscale_80200_A0_A1_cache_fns)
436 .long xscale_dma_a0_map_area 434 .long xscale_dma_a0_map_area
437 .long xscale_dma_unmap_area 435 .long xscale_dma_unmap_area
438 .long xscale_dma_flush_range 436 .long xscale_dma_flush_range
439 .long xscale_dma_clean_range
440 .long xscale_dma_flush_range
441 437
442ENTRY(cpu_xscale_dcache_clean_area) 438ENTRY(cpu_xscale_dcache_clean_area)
4431: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 4391: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 10:30:13 -0500