aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mm
diff options
context:
space:
mode:
authorRussell King <rmk+kernel@arm.linux.org.uk>2012-05-21 10:15:33 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-05-21 10:15:33 -0400
commit4ab1056766a4e49f6b9ef324313dd1583f8f8f4e (patch)
tree89f975e7e021dd27dc807e45445e963aeb39fcda /arch/arm/mm
parent4175160b065e74572819a320dcd34129224a4e1c (diff)
parent4cdfc2ec72e940abb4322aa1bc14f43a1486fc5d (diff)
Merge branch 'v3-removal' into for-linus
Conflicts: arch/arm/boot/compressed/head.S
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/Kconfig46
-rw-r--r--arch/arm/mm/Makefile4
-rw-r--r--arch/arm/mm/copypage-v3.c81
-rw-r--r--arch/arm/mm/fault.c3
-rw-r--r--arch/arm/mm/proc-arm6_7.S327
-rw-r--r--arch/arm/mm/tlb-v3.S48
6 files changed, 1 insertions, 508 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 7c8a7d8467bf..101b9681c08c 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -4,23 +4,6 @@ comment "Processor Type"
4# which CPUs we support in the kernel image, and the compiler instruction 4# which CPUs we support in the kernel image, and the compiler instruction
5# optimiser behaviour. 5# optimiser behaviour.
6 6
7# ARM610
8config CPU_ARM610
9 bool "Support ARM610 processor" if ARCH_RPC
10 select CPU_32v3
11 select CPU_CACHE_V3
12 select CPU_CACHE_VIVT
13 select CPU_CP15_MMU
14 select CPU_COPY_V3 if MMU
15 select CPU_TLB_V3 if MMU
16 select CPU_PABRT_LEGACY
17 help
18 The ARM610 is the successor to the ARM3 processor
19 and was produced by VLSI Technology Inc.
20
21 Say Y if you want support for the ARM610 processor.
22 Otherwise, say N.
23
24# ARM7TDMI 7# ARM7TDMI
25config CPU_ARM7TDMI 8config CPU_ARM7TDMI
26 bool "Support ARM7TDMI processor" 9 bool "Support ARM7TDMI processor"
@@ -36,25 +19,6 @@ config CPU_ARM7TDMI
36 Say Y if you want support for the ARM7TDMI processor. 19 Say Y if you want support for the ARM7TDMI processor.
37 Otherwise, say N. 20 Otherwise, say N.
38 21
39# ARM710
40config CPU_ARM710
41 bool "Support ARM710 processor" if ARCH_RPC
42 select CPU_32v3
43 select CPU_CACHE_V3
44 select CPU_CACHE_VIVT
45 select CPU_CP15_MMU
46 select CPU_COPY_V3 if MMU
47 select CPU_TLB_V3 if MMU
48 select CPU_PABRT_LEGACY
49 help
50 A 32-bit RISC microprocessor based on the ARM7 processor core
51 designed by Advanced RISC Machines Ltd. The ARM710 is the
52 successor to the ARM610 processor. It was released in
53 July 1994 by VLSI Technology Inc.
54
55 Say Y if you want support for the ARM710 processor.
56 Otherwise, say N.
57
58# ARM720T 22# ARM720T
59config CPU_ARM720T 23config CPU_ARM720T
60 bool "Support ARM720T processor" if ARCH_INTEGRATOR 24 bool "Support ARM720T processor" if ARCH_INTEGRATOR
@@ -530,9 +494,6 @@ config CPU_CACHE_FA
530 494
531if MMU 495if MMU
532# The copy-page model 496# The copy-page model
533config CPU_COPY_V3
534 bool
535
536config CPU_COPY_V4WT 497config CPU_COPY_V4WT
537 bool 498 bool
538 499
@@ -549,11 +510,6 @@ config CPU_COPY_V6
549 bool 510 bool
550 511
551# This selects the TLB model 512# This selects the TLB model
552config CPU_TLB_V3
553 bool
554 help
555 ARM Architecture Version 3 TLB.
556
557config CPU_TLB_V4WT 513config CPU_TLB_V4WT
558 bool 514 bool
559 help 515 help
@@ -731,7 +687,7 @@ config CPU_HIGH_VECTOR
731 687
732config CPU_ICACHE_DISABLE 688config CPU_ICACHE_DISABLE
733 bool "Disable I-Cache (I-bit)" 689 bool "Disable I-Cache (I-bit)"
734 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) 690 depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
735 help 691 help
736 Say Y here to disable the processor instruction cache. Unless 692 Say Y here to disable the processor instruction cache. Unless
737 you have a reason not to or are unsure, say N. 693 you have a reason not to or are unsure, say N.
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index bca7e61928c7..8a9c4cb50a93 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -44,7 +44,6 @@ obj-$(CONFIG_CPU_CACHE_FA) += cache-fa.o
44AFLAGS_cache-v6.o :=-Wa,-march=armv6 44AFLAGS_cache-v6.o :=-Wa,-march=armv6
45AFLAGS_cache-v7.o :=-Wa,-march=armv7-a 45AFLAGS_cache-v7.o :=-Wa,-march=armv7-a
46 46
47obj-$(CONFIG_CPU_COPY_V3) += copypage-v3.o
48obj-$(CONFIG_CPU_COPY_V4WT) += copypage-v4wt.o 47obj-$(CONFIG_CPU_COPY_V4WT) += copypage-v4wt.o
49obj-$(CONFIG_CPU_COPY_V4WB) += copypage-v4wb.o 48obj-$(CONFIG_CPU_COPY_V4WB) += copypage-v4wb.o
50obj-$(CONFIG_CPU_COPY_FEROCEON) += copypage-feroceon.o 49obj-$(CONFIG_CPU_COPY_FEROCEON) += copypage-feroceon.o
@@ -54,7 +53,6 @@ obj-$(CONFIG_CPU_XSCALE) += copypage-xscale.o
54obj-$(CONFIG_CPU_XSC3) += copypage-xsc3.o 53obj-$(CONFIG_CPU_XSC3) += copypage-xsc3.o
55obj-$(CONFIG_CPU_COPY_FA) += copypage-fa.o 54obj-$(CONFIG_CPU_COPY_FA) += copypage-fa.o
56 55
57obj-$(CONFIG_CPU_TLB_V3) += tlb-v3.o
58obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o 56obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o
59obj-$(CONFIG_CPU_TLB_V4WB) += tlb-v4wb.o 57obj-$(CONFIG_CPU_TLB_V4WB) += tlb-v4wb.o
60obj-$(CONFIG_CPU_TLB_V4WBI) += tlb-v4wbi.o 58obj-$(CONFIG_CPU_TLB_V4WBI) += tlb-v4wbi.o
@@ -66,8 +64,6 @@ obj-$(CONFIG_CPU_TLB_FA) += tlb-fa.o
66AFLAGS_tlb-v6.o :=-Wa,-march=armv6 64AFLAGS_tlb-v6.o :=-Wa,-march=armv6
67AFLAGS_tlb-v7.o :=-Wa,-march=armv7-a 65AFLAGS_tlb-v7.o :=-Wa,-march=armv7-a
68 66
69obj-$(CONFIG_CPU_ARM610) += proc-arm6_7.o
70obj-$(CONFIG_CPU_ARM710) += proc-arm6_7.o
71obj-$(CONFIG_CPU_ARM7TDMI) += proc-arm7tdmi.o 67obj-$(CONFIG_CPU_ARM7TDMI) += proc-arm7tdmi.o
72obj-$(CONFIG_CPU_ARM720T) += proc-arm720.o 68obj-$(CONFIG_CPU_ARM720T) += proc-arm720.o
73obj-$(CONFIG_CPU_ARM740T) += proc-arm740.o 69obj-$(CONFIG_CPU_ARM740T) += proc-arm740.o
diff --git a/arch/arm/mm/copypage-v3.c b/arch/arm/mm/copypage-v3.c
deleted file mode 100644
index 3935bddd4769..000000000000
--- a/arch/arm/mm/copypage-v3.c
+++ /dev/null
@@ -1,81 +0,0 @@
1/*
2 * linux/arch/arm/mm/copypage-v3.c
3 *
4 * Copyright (C) 1995-1999 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/init.h>
11#include <linux/highmem.h>
12
13/*
14 * ARMv3 optimised copy_user_highpage
15 *
16 * FIXME: do we need to handle cache stuff...
17 */
18static void __naked
19v3_copy_user_page(void *kto, const void *kfrom)
20{
21 asm("\n\
22 stmfd sp!, {r4, lr} @ 2\n\
23 mov r2, %2 @ 1\n\
24 ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\
251: stmia %1!, {r3, r4, ip, lr} @ 4\n\
26 ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\
27 stmia %1!, {r3, r4, ip, lr} @ 4\n\
28 ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\
29 stmia %1!, {r3, r4, ip, lr} @ 4\n\
30 ldmia %0!, {r3, r4, ip, lr} @ 4\n\
31 subs r2, r2, #1 @ 1\n\
32 stmia %1!, {r3, r4, ip, lr} @ 4\n\
33 ldmneia %0!, {r3, r4, ip, lr} @ 4\n\
34 bne 1b @ 1\n\
35 ldmfd sp!, {r4, pc} @ 3"
36 :
37 : "r" (kfrom), "r" (kto), "I" (PAGE_SIZE / 64));
38}
39
40void v3_copy_user_highpage(struct page *to, struct page *from,
41 unsigned long vaddr, struct vm_area_struct *vma)
42{
43 void *kto, *kfrom;
44
45 kto = kmap_atomic(to);
46 kfrom = kmap_atomic(from);
47 v3_copy_user_page(kto, kfrom);
48 kunmap_atomic(kfrom);
49 kunmap_atomic(kto);
50}
51
52/*
53 * ARMv3 optimised clear_user_page
54 *
55 * FIXME: do we need to handle cache stuff...
56 */
57void v3_clear_user_highpage(struct page *page, unsigned long vaddr)
58{
59 void *ptr, *kaddr = kmap_atomic(page);
60 asm volatile("\n\
61 mov r1, %2 @ 1\n\
62 mov r2, #0 @ 1\n\
63 mov r3, #0 @ 1\n\
64 mov ip, #0 @ 1\n\
65 mov lr, #0 @ 1\n\
661: stmia %0!, {r2, r3, ip, lr} @ 4\n\
67 stmia %0!, {r2, r3, ip, lr} @ 4\n\
68 stmia %0!, {r2, r3, ip, lr} @ 4\n\
69 stmia %0!, {r2, r3, ip, lr} @ 4\n\
70 subs r1, r1, #1 @ 1\n\
71 bne 1b @ 1"
72 : "=r" (ptr)
73 : "0" (kaddr), "I" (PAGE_SIZE / 64)
74 : "r1", "r2", "r3", "ip", "lr");
75 kunmap_atomic(kaddr);
76}
77
78struct cpu_user_fns v3_user_fns __initdata = {
79 .cpu_clear_user_highpage = v3_clear_user_highpage,
80 .cpu_copy_user_highpage = v3_copy_user_highpage,
81};
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 5bb48356d217..c3bd83450227 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -432,9 +432,6 @@ do_translation_fault(unsigned long addr, unsigned int fsr,
432 432
433 index = pgd_index(addr); 433 index = pgd_index(addr);
434 434
435 /*
436 * FIXME: CP15 C1 is write only on ARMv3 architectures.
437 */
438 pgd = cpu_get_pgd() + index; 435 pgd = cpu_get_pgd() + index;
439 pgd_k = init_mm.pgd + index; 436 pgd_k = init_mm.pgd + index;
440 437
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
deleted file mode 100644
index 4fbeb5b8e6c2..000000000000
--- a/arch/arm/mm/proc-arm6_7.S
+++ /dev/null
@@ -1,327 +0,0 @@
1/*
2 * linux/arch/arm/mm/proc-arm6,7.S
3 *
4 * Copyright (C) 1997-2000 Russell King
5 * hacked for non-paged-MM by Hyok S. Choi, 2003.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * These are the low level assembler for performing cache and TLB
12 * functions on the ARM610 & ARM710.
13 */
14#include <linux/linkage.h>
15#include <linux/init.h>
16#include <asm/assembler.h>
17#include <asm/asm-offsets.h>
18#include <asm/hwcap.h>
19#include <asm/pgtable-hwdef.h>
20#include <asm/pgtable.h>
21#include <asm/ptrace.h>
22
23#include "proc-macros.S"
24
25ENTRY(cpu_arm6_dcache_clean_area)
26ENTRY(cpu_arm7_dcache_clean_area)
27 mov pc, lr
28
29/*
30 * Function: arm6_7_data_abort ()
31 *
32 * Params : r2 = pt_regs
33 * : r4 = aborted context pc
34 * : r5 = aborted context psr
35 *
36 * Purpose : obtain information about current aborted instruction
37 *
38 * Returns : r4-r5, r10-r11, r13 preserved
39 */
40
41ENTRY(cpu_arm7_data_abort)
42 mrc p15, 0, r1, c5, c0, 0 @ get FSR
43 mrc p15, 0, r0, c6, c0, 0 @ get FAR
44 ldr r8, [r4] @ read arm instruction
45 tst r8, #1 << 20 @ L = 0 -> write?
46 orreq r1, r1, #1 << 11 @ yes.
47 and r7, r8, #15 << 24
48 add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine
49 nop
50
51/* 0 */ b .data_unknown
52/* 1 */ b do_DataAbort @ swp
53/* 2 */ b .data_unknown
54/* 3 */ b .data_unknown
55/* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m
56/* 5 */ b .data_arm_lateldrpreconst @ ldr rd, [rn, #m]
57/* 6 */ b .data_arm_lateldrpostreg @ ldr rd, [rn], rm
58/* 7 */ b .data_arm_lateldrprereg @ ldr rd, [rn, rm]
59/* 8 */ b .data_arm_ldmstm @ ldm*a rn, <rlist>
60/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist>
61/* a */ b .data_unknown
62/* b */ b .data_unknown
63/* c */ b do_DataAbort @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
64/* d */ b do_DataAbort @ ldc rd, [rn, #m]
65/* e */ b .data_unknown
66/* f */
67.data_unknown: @ Part of jumptable
68 mov r0, r4
69 mov r1, r8
70 b baddataabort
71
72ENTRY(cpu_arm6_data_abort)
73 mrc p15, 0, r1, c5, c0, 0 @ get FSR
74 mrc p15, 0, r0, c6, c0, 0 @ get FAR
75 ldr r8, [r4] @ read arm instruction
76 tst r8, #1 << 20 @ L = 0 -> write?
77 orreq r1, r1, #1 << 11 @ yes.
78 and r7, r8, #14 << 24
79 teq r7, #8 << 24 @ was it ldm/stm
80 bne do_DataAbort
81
82.data_arm_ldmstm:
83 tst r8, #1 << 21 @ check writeback bit
84 beq do_DataAbort @ no writeback -> no fixup
85 mov r7, #0x11
86 orr r7, r7, #0x1100
87 and r6, r8, r7
88 and r9, r8, r7, lsl #1
89 add r6, r6, r9, lsr #1
90 and r9, r8, r7, lsl #2
91 add r6, r6, r9, lsr #2
92 and r9, r8, r7, lsl #3
93 add r6, r6, r9, lsr #3
94 add r6, r6, r6, lsr #8
95 add r6, r6, r6, lsr #4
96 and r6, r6, #15 @ r6 = no. of registers to transfer.
97 and r9, r8, #15 << 16 @ Extract 'n' from instruction
98 ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
99 tst r8, #1 << 23 @ Check U bit
100 subne r7, r7, r6, lsl #2 @ Undo increment
101 addeq r7, r7, r6, lsl #2 @ Undo decrement
102 str r7, [r2, r9, lsr #14] @ Put register 'Rn'
103 b do_DataAbort
104
105.data_arm_apply_r6_and_rn:
106 and r9, r8, #15 << 16 @ Extract 'n' from instruction
107 ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
108 tst r8, #1 << 23 @ Check U bit
109 subne r7, r7, r6 @ Undo incrmenet
110 addeq r7, r7, r6 @ Undo decrement
111 str r7, [r2, r9, lsr #14] @ Put register 'Rn'
112 b do_DataAbort
113
114.data_arm_lateldrpreconst:
115 tst r8, #1 << 21 @ check writeback bit
116 beq do_DataAbort @ no writeback -> no fixup
117.data_arm_lateldrpostconst:
118 movs r6, r8, lsl #20 @ Get offset
119 beq do_DataAbort @ zero -> no fixup
120 and r9, r8, #15 << 16 @ Extract 'n' from instruction
121 ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
122 tst r8, #1 << 23 @ Check U bit
123 subne r7, r7, r6, lsr #20 @ Undo increment
124 addeq r7, r7, r6, lsr #20 @ Undo decrement
125 str r7, [r2, r9, lsr #14] @ Put register 'Rn'
126 b do_DataAbort
127
128.data_arm_lateldrprereg:
129 tst r8, #1 << 21 @ check writeback bit
130 beq do_DataAbort @ no writeback -> no fixup
131.data_arm_lateldrpostreg:
132 and r7, r8, #15 @ Extract 'm' from instruction
133 ldr r6, [r2, r7, lsl #2] @ Get register 'Rm'
134 mov r9, r8, lsr #7 @ get shift count
135 ands r9, r9, #31
136 and r7, r8, #0x70 @ get shift type
137 orreq r7, r7, #8 @ shift count = 0
138 add pc, pc, r7
139 nop
140
141 mov r6, r6, lsl r9 @ 0: LSL #!0
142 b .data_arm_apply_r6_and_rn
143 b .data_arm_apply_r6_and_rn @ 1: LSL #0
144 nop
145 b .data_unknown @ 2: MUL?
146 nop
147 b .data_unknown @ 3: MUL?
148 nop
149 mov r6, r6, lsr r9 @ 4: LSR #!0
150 b .data_arm_apply_r6_and_rn
151 mov r6, r6, lsr #32 @ 5: LSR #32
152 b .data_arm_apply_r6_and_rn
153 b .data_unknown @ 6: MUL?
154 nop
155 b .data_unknown @ 7: MUL?
156 nop
157 mov r6, r6, asr r9 @ 8: ASR #!0
158 b .data_arm_apply_r6_and_rn
159 mov r6, r6, asr #32 @ 9: ASR #32
160 b .data_arm_apply_r6_and_rn
161 b .data_unknown @ A: MUL?
162 nop
163 b .data_unknown @ B: MUL?
164 nop
165 mov r6, r6, ror r9 @ C: ROR #!0
166 b .data_arm_apply_r6_and_rn
167 mov r6, r6, rrx @ D: RRX
168 b .data_arm_apply_r6_and_rn
169 b .data_unknown @ E: MUL?
170 nop
171 b .data_unknown @ F: MUL?
172
173/*
174 * Function: arm6_7_proc_init (void)
175 * : arm6_7_proc_fin (void)
176 *
177 * Notes : This processor does not require these
178 */
179ENTRY(cpu_arm6_proc_init)
180ENTRY(cpu_arm7_proc_init)
181 mov pc, lr
182
183ENTRY(cpu_arm6_proc_fin)
184ENTRY(cpu_arm7_proc_fin)
185 mov r0, #0x31 @ ....S..DP...M
186 mcr p15, 0, r0, c1, c0, 0 @ disable caches
187 mov pc, lr
188
189ENTRY(cpu_arm6_do_idle)
190ENTRY(cpu_arm7_do_idle)
191 mov pc, lr
192
193/*
194 * Function: arm6_7_switch_mm(unsigned long pgd_phys)
195 * Params : pgd_phys Physical address of page table
196 * Purpose : Perform a task switch, saving the old processes state, and restoring
197 * the new.
198 */
199ENTRY(cpu_arm6_switch_mm)
200ENTRY(cpu_arm7_switch_mm)
201#ifdef CONFIG_MMU
202 mov r1, #0
203 mcr p15, 0, r1, c7, c0, 0 @ flush cache
204 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
205 mcr p15, 0, r1, c5, c0, 0 @ flush TLBs
206#endif
207 mov pc, lr
208
209/*
210 * Function: arm6_7_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
211 * Params : r0 = Address to set
212 * : r1 = value to set
213 * Purpose : Set a PTE and flush it out of any WB cache
214 */
215 .align 5
216ENTRY(cpu_arm6_set_pte_ext)
217ENTRY(cpu_arm7_set_pte_ext)
218#ifdef CONFIG_MMU
219 armv3_set_pte_ext wc_disable=0
220#endif /* CONFIG_MMU */
221 mov pc, lr
222
223/*
224 * Function: _arm6_7_reset
225 * Params : r0 = address to jump to
226 * Notes : This sets up everything for a reset
227 */
228 .pushsection .idmap.text, "ax"
229ENTRY(cpu_arm6_reset)
230ENTRY(cpu_arm7_reset)
231 mov r1, #0
232 mcr p15, 0, r1, c7, c0, 0 @ flush cache
233#ifdef CONFIG_MMU
234 mcr p15, 0, r1, c5, c0, 0 @ flush TLB
235#endif
236 mov r1, #0x30
237 mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc
238 mov pc, r0
239ENDPROC(cpu_arm6_reset)
240ENDPROC(cpu_arm7_reset)
241 .popsection
242
243 __CPUINIT
244
245 .type __arm6_setup, #function
246__arm6_setup: mov r0, #0
247 mcr p15, 0, r0, c7, c0 @ flush caches on v3
248#ifdef CONFIG_MMU
249 mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
250 mov r0, #0x3d @ . ..RS BLDP WCAM
251 orr r0, r0, #0x100 @ . ..01 0011 1101
252#else
253 mov r0, #0x3c @ . ..RS BLDP WCA.
254#endif
255 mov pc, lr
256 .size __arm6_setup, . - __arm6_setup
257
258 .type __arm7_setup, #function
259__arm7_setup: mov r0, #0
260 mcr p15, 0, r0, c7, c0 @ flush caches on v3
261#ifdef CONFIG_MMU
262 mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
263 mcr p15, 0, r0, c3, c0 @ load domain access register
264 mov r0, #0x7d @ . ..RS BLDP WCAM
265 orr r0, r0, #0x100 @ . ..01 0111 1101
266#else
267 mov r0, #0x7c @ . ..RS BLDP WCA.
268#endif
269 mov pc, lr
270 .size __arm7_setup, . - __arm7_setup
271
272 __INITDATA
273
274 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
275 define_processor_functions arm6, dabort=cpu_arm6_data_abort, pabort=legacy_pabort
276 define_processor_functions arm7, dabort=cpu_arm7_data_abort, pabort=legacy_pabort
277
278 .section ".rodata"
279
280 string cpu_arch_name, "armv3"
281 string cpu_elf_name, "v3"
282 string cpu_arm6_name, "ARM6"
283 string cpu_arm610_name, "ARM610"
284 string cpu_arm7_name, "ARM7"
285 string cpu_arm710_name, "ARM710"
286
287 .align
288
289 .section ".proc.info.init", #alloc, #execinstr
290
291.macro arm67_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \
292 cpu_mm_mmu_flags:req, cpu_flush:req, cpu_proc_funcs:req
293 .type __\name\()_proc_info, #object
294__\name\()_proc_info:
295 .long \cpu_val
296 .long \cpu_mask
297 .long \cpu_mm_mmu_flags
298 .long PMD_TYPE_SECT | \
299 PMD_BIT4 | \
300 PMD_SECT_AP_WRITE | \
301 PMD_SECT_AP_READ
302 b \cpu_flush
303 .long cpu_arch_name
304 .long cpu_elf_name
305 .long HWCAP_SWP | HWCAP_26BIT
306 .long \cpu_name
307 .long \cpu_proc_funcs
308 .long v3_tlb_fns
309 .long v3_user_fns
310 .long v3_cache_fns
311 .size __\name\()_proc_info, . - __\name\()_proc_info
312.endm
313
314 arm67_proc_info arm6, 0x41560600, 0xfffffff0, cpu_arm6_name, \
315 0x00000c1e, __arm6_setup, arm6_processor_functions
316 arm67_proc_info arm610, 0x41560610, 0xfffffff0, cpu_arm610_name, \
317 0x00000c1e, __arm6_setup, arm6_processor_functions
318 arm67_proc_info arm7, 0x41007000, 0xffffff00, cpu_arm7_name, \
319 0x00000c1e, __arm7_setup, arm7_processor_functions
320 arm67_proc_info arm710, 0x41007100, 0xfff8ff00, cpu_arm710_name, \
321 PMD_TYPE_SECT | \
322 PMD_SECT_BUFFERABLE | \
323 PMD_SECT_CACHEABLE | \
324 PMD_BIT4 | \
325 PMD_SECT_AP_WRITE | \
326 PMD_SECT_AP_READ, \
327 __arm7_setup, arm7_processor_functions
diff --git a/arch/arm/mm/tlb-v3.S b/arch/arm/mm/tlb-v3.S
deleted file mode 100644
index d253995ec4ca..000000000000
--- a/arch/arm/mm/tlb-v3.S
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * linux/arch/arm/mm/tlbv3.S
3 *
4 * Copyright (C) 1997-2002 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * ARM architecture version 3 TLB handling functions.
11 *
12 * Processors: ARM610, ARM710.
13 */
14#include <linux/linkage.h>
15#include <linux/init.h>
16#include <asm/asm-offsets.h>
17#include <asm/tlbflush.h>
18#include "proc-macros.S"
19
20 .align 5
21/*
22 * v3_flush_user_tlb_range(start, end, mm)
23 *
24 * Invalidate a range of TLB entries in the specified address space.
25 *
26 * - start - range start address
27 * - end - range end address
28 * - mm - mm_struct describing address space
29 */
30 .align 5
31ENTRY(v3_flush_user_tlb_range)
32 vma_vm_mm r2, r2
33 act_mm r3 @ get current->active_mm
34 teq r2, r3 @ == mm ?
35 movne pc, lr @ no, we dont do anything
36ENTRY(v3_flush_kern_tlb_range)
37 bic r0, r0, #0x0ff
38 bic r0, r0, #0xf00
391: mcr p15, 0, r0, c6, c0, 0 @ invalidate TLB entry
40 add r0, r0, #PAGE_SZ
41 cmp r0, r1
42 blo 1b
43 mov pc, lr
44
45 __INITDATA
46
47 /* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
48 define_tlb_functions v3, v3_tlb_flags
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 01:06:24 -0500