diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-03-19 11:39:09 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-05-29 19:48:50 -0400 |
commit | 4374d64933b1d0f0ebbad064289ef44b869d77c1 (patch) | |
tree | 51f5cdcfc6ce98abd5a7cd4214eeff51af9b1ea2 /arch/arm/mm | |
parent | ddf7d79bc739c44f7e7cdffc9eb5d94aa213f53e (diff) |
ARM: l2c: add automatic enable of early BRESP
The AXI bus protocol requires that a write response should only be
sent back to the master when the last write has been accepted. Early
BRESP allows the L2C-310 to send the write response as soon as the
store buffer accepts the write address.
Cortex-A9 processors can signal to the L2C-310 that they wish to be
notified early, and if this optimisation is enabled, the L2C-310 can
signal an early write response.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm')
-rw-r--r-- | arch/arm/mm/cache-l2x0.c | 25 |
1 files changed, 22 insertions, 3 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 3a34db56827b..7e53214f7c36 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include <linux/of_address.h> | 24 | #include <linux/of_address.h> |
25 | 25 | ||
26 | #include <asm/cacheflush.h> | 26 | #include <asm/cacheflush.h> |
27 | #include <asm/cputype.h> | ||
27 | #include <asm/hardware/cache-l2x0.h> | 28 | #include <asm/hardware/cache-l2x0.h> |
28 | #include "cache-tauros3.h" | 29 | #include "cache-tauros3.h" |
29 | #include "cache-aurora-l2.h" | 30 | #include "cache-aurora-l2.h" |
@@ -638,6 +639,24 @@ static void l2c310_resume(void) | |||
638 | } | 639 | } |
639 | } | 640 | } |
640 | 641 | ||
642 | static void __init l2c310_enable(void __iomem *base, u32 aux, unsigned num_lock) | ||
643 | { | ||
644 | unsigned rev = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_PART_MASK; | ||
645 | bool cortex_a9 = read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9; | ||
646 | |||
647 | if (rev >= L310_CACHE_ID_RTL_R2P0) { | ||
648 | if (cortex_a9) { | ||
649 | aux |= L310_AUX_CTRL_EARLY_BRESP; | ||
650 | pr_info("L2C-310 enabling early BRESP for Cortex-A9\n"); | ||
651 | } else if (aux & L310_AUX_CTRL_EARLY_BRESP) { | ||
652 | pr_warn("L2C-310 early BRESP only supported with Cortex-A9\n"); | ||
653 | aux &= ~L310_AUX_CTRL_EARLY_BRESP; | ||
654 | } | ||
655 | } | ||
656 | |||
657 | l2c_enable(base, aux, num_lock); | ||
658 | } | ||
659 | |||
641 | static void __init l2c310_fixup(void __iomem *base, u32 cache_id, | 660 | static void __init l2c310_fixup(void __iomem *base, u32 cache_id, |
642 | struct outer_cache_fns *fns) | 661 | struct outer_cache_fns *fns) |
643 | { | 662 | { |
@@ -699,7 +718,7 @@ static const struct l2c_init_data l2c310_init_fns __initconst = { | |||
699 | .type = "L2C-310", | 718 | .type = "L2C-310", |
700 | .way_size_0 = SZ_8K, | 719 | .way_size_0 = SZ_8K, |
701 | .num_lock = 8, | 720 | .num_lock = 8, |
702 | .enable = l2c_enable, | 721 | .enable = l2c310_enable, |
703 | .fixup = l2c310_fixup, | 722 | .fixup = l2c310_fixup, |
704 | .save = l2c310_save, | 723 | .save = l2c310_save, |
705 | .outer_cache = { | 724 | .outer_cache = { |
@@ -940,7 +959,7 @@ static const struct l2c_init_data of_l2c310_data __initconst = { | |||
940 | .way_size_0 = SZ_8K, | 959 | .way_size_0 = SZ_8K, |
941 | .num_lock = 8, | 960 | .num_lock = 8, |
942 | .of_parse = l2c310_of_parse, | 961 | .of_parse = l2c310_of_parse, |
943 | .enable = l2c_enable, | 962 | .enable = l2c310_enable, |
944 | .fixup = l2c310_fixup, | 963 | .fixup = l2c310_fixup, |
945 | .save = l2c310_save, | 964 | .save = l2c310_save, |
946 | .outer_cache = { | 965 | .outer_cache = { |
@@ -1289,7 +1308,7 @@ static const struct l2c_init_data of_bcm_l2x0_data __initconst = { | |||
1289 | .way_size_0 = SZ_8K, | 1308 | .way_size_0 = SZ_8K, |
1290 | .num_lock = 8, | 1309 | .num_lock = 8, |
1291 | .of_parse = l2c310_of_parse, | 1310 | .of_parse = l2c310_of_parse, |
1292 | .enable = l2c_enable, | 1311 | .enable = l2c310_enable, |
1293 | .save = l2c310_save, | 1312 | .save = l2c310_save, |
1294 | .outer_cache = { | 1313 | .outer_cache = { |
1295 | .inv_range = bcm_inv_range, | 1314 | .inv_range = bcm_inv_range, |