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authorCatalin Marinas <catalin.marinas@arm.com>2006-03-07 09:42:27 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-03-07 09:42:27 -0500
commit6a0e243069b09a323255f6e847c87d531961cd96 (patch)
tree575a7194c86b2b3e1b9db30e283a2f5705e89e99 /arch/arm/mm/tlb-v6.S
parentd11d9b2dd2c43dd99a491df8a83ae28401db0044 (diff)
[ARM] 3352/1: DSB required for the completion of a TLB maintenance operation
Patch from Catalin Marinas Chapter B2.7.3 in the latest ARM ARM (with v6 information) states that the completion of a TLB maintenance operation is only guaranteed by the execution of a DSB (Data Syncronization Barrier, formerly Data Write Barrier or Drain Write Buffer). Note that a DSB is only needed in the flush_tlb_kernel_* functions since the completion is guaranteed by a mode change (i.e. switching back to user mode) for the flush_tlb_user_* functions. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/tlb-v6.S')
-rw-r--r--arch/arm/mm/tlb-v6.S1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mm/tlb-v6.S b/arch/arm/mm/tlb-v6.S
index 6f76b89ef46e..fd6adde39091 100644
--- a/arch/arm/mm/tlb-v6.S
+++ b/arch/arm/mm/tlb-v6.S
@@ -80,6 +80,7 @@ ENTRY(v6wbi_flush_kern_tlb_range)
80 add r0, r0, #PAGE_SZ 80 add r0, r0, #PAGE_SZ
81 cmp r0, r1 81 cmp r0, r1
82 blo 1b 82 blo 1b
83 mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier
83 mov pc, lr 84 mov pc, lr
84 85
85 .section ".text.init", #alloc, #execinstr 86 .section ".text.init", #alloc, #execinstr