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authorJeff Garzik <jgarzik@pobox.com>2005-08-11 00:07:03 -0400
committerJeff Garzik <jgarzik@pobox.com>2005-08-11 00:07:03 -0400
commitcd04b947bc674f8fc9cac38ec30497bae5d664ad (patch)
tree988b0b7ea08063e5499672346eb2f619f0629717 /arch/arm/mm/proc-xscale.S
parentb3df9f813bc7b9db62ae0c90b8990b1cebf97345 (diff)
parentbc68552faad0e134eb22281343d5ae5a4873fa80 (diff)
Merge /spare/repo/linux-2.6/
Diffstat (limited to 'arch/arm/mm/proc-xscale.S')
-rw-r--r--arch/arm/mm/proc-xscale.S136
1 files changed, 0 insertions, 136 deletions
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 2d977b4eeeab..b88de2700146 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -370,142 +370,6 @@ ENTRY(cpu_xscale_dcache_clean_area)
370 bhi 1b 370 bhi 1b
371 mov pc, lr 371 mov pc, lr
372 372
373/* ================================ CACHE LOCKING============================
374 *
375 * The XScale MicroArchitecture implements support for locking entries into
376 * the data and instruction cache. The following functions implement the core
377 * low level instructions needed to accomplish the locking. The developer's
378 * manual states that the code that performs the locking must be in non-cached
379 * memory. To accomplish this, the code in xscale-cache-lock.c copies the
380 * following functions from the cache into a non-cached memory region that
381 * is allocated through consistent_alloc().
382 *
383 */
384 .align 5
385/*
386 * xscale_icache_lock
387 *
388 * r0: starting address to lock
389 * r1: end address to lock
390 */
391ENTRY(xscale_icache_lock)
392
393iLockLoop:
394 bic r0, r0, #CACHELINESIZE - 1
395 mcr p15, 0, r0, c9, c1, 0 @ lock into cache
396 cmp r0, r1 @ are we done?
397 add r0, r0, #CACHELINESIZE @ advance to next cache line
398 bls iLockLoop
399 mov pc, lr
400
401/*
402 * xscale_icache_unlock
403 */
404ENTRY(xscale_icache_unlock)
405 mcr p15, 0, r0, c9, c1, 1 @ Unlock icache
406 mov pc, lr
407
408/*
409 * xscale_dcache_lock
410 *
411 * r0: starting address to lock
412 * r1: end address to lock
413 */
414ENTRY(xscale_dcache_lock)
415 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
416 mov r2, #1
417 mcr p15, 0, r2, c9, c2, 0 @ Put dcache in lock mode
418 cpwait ip @ Wait for completion
419
420 mrs r2, cpsr
421 orr r3, r2, #PSR_F_BIT | PSR_I_BIT
422dLockLoop:
423 msr cpsr_c, r3
424 mcr p15, 0, r0, c7, c10, 1 @ Write back line if it is dirty
425 mcr p15, 0, r0, c7, c6, 1 @ Flush/invalidate line
426 msr cpsr_c, r2
427 ldr ip, [r0], #CACHELINESIZE @ Preload 32 bytes into cache from
428 @ location [r0]. Post-increment
429 @ r3 to next cache line
430 cmp r0, r1 @ Are we done?
431 bls dLockLoop
432
433 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
434 mov r2, #0
435 mcr p15, 0, r2, c9, c2, 0 @ Get out of lock mode
436 cpwait_ret lr, ip
437
438/*
439 * xscale_dcache_unlock
440 */
441ENTRY(xscale_dcache_unlock)
442 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
443 mcr p15, 0, ip, c9, c2, 1 @ Unlock cache
444 mov pc, lr
445
446/*
447 * Needed to determine the length of the code that needs to be copied.
448 */
449 .align 5
450ENTRY(xscale_cache_dummy)
451 mov pc, lr
452
453/* ================================ TLB LOCKING==============================
454 *
455 * The XScale MicroArchitecture implements support for locking entries into
456 * the Instruction and Data TLBs. The following functions provide the
457 * low level support for supporting these under Linux. xscale-lock.c
458 * implements some higher level management code. Most of the following
459 * is taken straight out of the Developer's Manual.
460 */
461
462/*
463 * Lock I-TLB entry
464 *
465 * r0: Virtual address to translate and lock
466 */
467 .align 5
468ENTRY(xscale_itlb_lock)
469 mrs r2, cpsr
470 orr r3, r2, #PSR_F_BIT | PSR_I_BIT
471 msr cpsr_c, r3 @ Disable interrupts
472 mcr p15, 0, r0, c8, c5, 1 @ Invalidate I-TLB entry
473 mcr p15, 0, r0, c10, c4, 0 @ Translate and lock
474 msr cpsr_c, r2 @ Restore interrupts
475 cpwait_ret lr, ip
476
477/*
478 * Lock D-TLB entry
479 *
480 * r0: Virtual address to translate and lock
481 */
482 .align 5
483ENTRY(xscale_dtlb_lock)
484 mrs r2, cpsr
485 orr r3, r2, #PSR_F_BIT | PSR_I_BIT
486 msr cpsr_c, r3 @ Disable interrupts
487 mcr p15, 0, r0, c8, c6, 1 @ Invalidate D-TLB entry
488 mcr p15, 0, r0, c10, c8, 0 @ Translate and lock
489 msr cpsr_c, r2 @ Restore interrupts
490 cpwait_ret lr, ip
491
492/*
493 * Unlock all I-TLB entries
494 */
495 .align 5
496ENTRY(xscale_itlb_unlock)
497 mcr p15, 0, ip, c10, c4, 1 @ Unlock I-TLB
498 mcr p15, 0, ip, c8, c5, 0 @ Invalidate I-TLB
499 cpwait_ret lr, ip
500
501/*
502 * Unlock all D-TLB entries
503 */
504ENTRY(xscale_dtlb_unlock)
505 mcr p15, 0, ip, c10, c8, 1 @ Unlock D-TBL
506 mcr p15, 0, ip, c8, c6, 0 @ Invalidate D-TLB
507 cpwait_ret lr, ip
508
509/* =============================== PageTable ============================== */ 373/* =============================== PageTable ============================== */
510 374
511#define PTE_CACHE_WRITE_ALLOCATE 0 375#define PTE_CACHE_WRITE_ALLOCATE 0