Merge branch 'for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux into devel-stable

Conflicts:
	arch/arm/mm/ioremap.c

1 files changed, 20 insertions, 157 deletions

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 66a185f018a0..7efa2a721d5d 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -19,24 +19,11 @@
 
 #include "proc-macros.S"
 
-#define TTB_S           (1 << 1)
-#define TTB_RGN_NC      (0 << 3)
-#define TTB_RGN_OC_WBWA (1 << 3)
-#define TTB_RGN_OC_WT   (2 << 3)
-#define TTB_RGN_OC_WB   (3 << 3)
-#define TTB_NOS         (1 << 5)
-#define TTB_IRGN_NC     ((0 << 0) | (0 << 6))
-#define TTB_IRGN_WBWA   ((0 << 0) | (1 << 6))
-#define TTB_IRGN_WT     ((1 << 0) | (0 << 6))
-#define TTB_IRGN_WB     ((1 << 0) | (1 << 6))
-
-/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
-#define TTB_FLAGS_UP    TTB_IRGN_WB|TTB_RGN_OC_WB
-#define PMD_FLAGS_UP    PMD_SECT_WB
-
-/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
-#define TTB_FLAGS_SMP   TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
-#define PMD_FLAGS_SMP   PMD_SECT_WBWA|PMD_SECT_S
+#ifdef CONFIG_ARM_LPAE
+#include "proc-v7-3level.S"
+#else
+#include "proc-v7-2level.S"
+#endif
 
 ENTRY(cpu_v7_proc_init)
         mov     pc, lr
@@ -99,127 +86,12 @@ ENTRY(cpu_v7_dcache_clean_area)
         mov     pc, lr
 ENDPROC(cpu_v7_dcache_clean_area)
 
-/*
- *      cpu_v7_switch_mm(pgd_phys, tsk)
- *
- *      Set the translation table base pointer to be pgd_phys
- *
- *      - pgd_phys - physical address of new TTB
- *
- *      It is assumed that:
- *      - we are not using split page tables
- */
-ENTRY(cpu_v7_switch_mm)
-#ifdef CONFIG_MMU
-        mov     r2, #0
-        ldr     r1, [r1, #MM_CONTEXT_ID]        @ get mm->context.id
-        ALT_SMP(orr     r0, r0, #TTB_FLAGS_SMP)
-        ALT_UP(orr      r0, r0, #TTB_FLAGS_UP)
-#ifdef CONFIG_ARM_ERRATA_430973
-        mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
-#endif
-#ifdef CONFIG_ARM_ERRATA_754322
-        dsb
-#endif
-        mcr     p15, 0, r2, c13, c0, 1          @ set reserved context ID
-        isb
-1:      mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
-        isb
-#ifdef CONFIG_ARM_ERRATA_754322
-        dsb
-#endif
-        mcr     p15, 0, r1, c13, c0, 1          @ set context ID
-        isb
-#endif
-        mov     pc, lr
-ENDPROC(cpu_v7_switch_mm)
-
-/*
- *      cpu_v7_set_pte_ext(ptep, pte)
- *
- *      Set a level 2 translation table entry.
- *
- *      - ptep  - pointer to level 2 translation table entry
- *                (hardware version is stored at +2048 bytes)
- *      - pte   - PTE value to store
- *      - ext   - value for extended PTE bits
- */
-ENTRY(cpu_v7_set_pte_ext)
-#ifdef CONFIG_MMU
-        str     r1, [r0]                        @ linux version
-
-        bic     r3, r1, #0x000003f0
-        bic     r3, r3, #PTE_TYPE_MASK
-        orr     r3, r3, r2
-        orr     r3, r3, #PTE_EXT_AP0 | 2
-
-        tst     r1, #1 << 4
-        orrne   r3, r3, #PTE_EXT_TEX(1)
-
-        eor     r1, r1, #L_PTE_DIRTY
-        tst     r1, #L_PTE_RDONLY | L_PTE_DIRTY
-        orrne   r3, r3, #PTE_EXT_APX
-
-        tst     r1, #L_PTE_USER
-        orrne   r3, r3, #PTE_EXT_AP1
-#ifdef CONFIG_CPU_USE_DOMAINS
-        @ allow kernel read/write access to read-only user pages
-        tstne   r3, #PTE_EXT_APX
-        bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
-#endif
-
-        tst     r1, #L_PTE_XN
-        orrne   r3, r3, #PTE_EXT_XN
-
-        tst     r1, #L_PTE_YOUNG
-        tstne   r1, #L_PTE_PRESENT
-        moveq   r3, #0
-
- ARM(   str     r3, [r0, #2048]! )
- THUMB( add     r0, r0, #2048 )
- THUMB( str     r3, [r0] )
-        mcr     p15, 0, r0, c7, c10, 1          @ flush_pte
-#endif
-        mov     pc, lr
-ENDPROC(cpu_v7_set_pte_ext)
-
         string  cpu_v7_name, "ARMv7 Processor"
         .align
 
-        /*
-         * Memory region attributes with SCTLR.TRE=1
-         *
-         *   n = TEX[0],C,B
-         *   TR = PRRR[2n+1:2n]         - memory type
-         *   IR = NMRR[2n+1:2n]         - inner cacheable property
-         *   OR = NMRR[2n+17:2n+16]     - outer cacheable property
-         *
-         *                      n       TR      IR      OR
-         *   UNCACHED           000     00
-         *   BUFFERABLE         001     10      00      00
-         *   WRITETHROUGH       010     10      10      10
-         *   WRITEBACK          011     10      11      11
-         *   reserved           110
-         *   WRITEALLOC         111     10      01      01
-         *   DEV_SHARED         100     01
-         *   DEV_NONSHARED      100     01
-         *   DEV_WC             001     10
-         *   DEV_CACHED         011     10
-         *
-         * Other attributes:
-         *
-         *   DS0 = PRRR[16] = 0         - device shareable property
-         *   DS1 = PRRR[17] = 1         - device shareable property
-         *   NS0 = PRRR[18] = 0         - normal shareable property
-         *   NS1 = PRRR[19] = 1         - normal shareable property
-         *   NOS = PRRR[24+n] = 1       - not outer shareable
-         */
-.equ    PRRR,   0xff0a81a8
-.equ    NMRR,   0x40e040e0
-
 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
 .globl  cpu_v7_suspend_size
-.equ    cpu_v7_suspend_size, 4 * 7
+.equ    cpu_v7_suspend_size, 4 * 8
 #ifdef CONFIG_ARM_CPU_SUSPEND
 ENTRY(cpu_v7_do_suspend)
         stmfd   sp!, {r4 - r10, lr}
@@ -228,10 +100,11 @@ ENTRY(cpu_v7_do_suspend)
         stmia   r0!, {r4 - r5}
         mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
         mrc     p15, 0, r7, c2, c0, 1   @ TTB 1
+        mrc     p15, 0, r11, c2, c0, 2  @ TTB control register
         mrc     p15, 0, r8, c1, c0, 0   @ Control register
         mrc     p15, 0, r9, c1, c0, 1   @ Auxiliary control register
         mrc     p15, 0, r10, c1, c0, 2  @ Co-processor access control
-        stmia   r0, {r6 - r10}
+        stmia   r0, {r6 - r11}
         ldmfd   sp!, {r4 - r10, pc}
 ENDPROC(cpu_v7_do_suspend)
 
@@ -243,13 +116,15 @@ ENTRY(cpu_v7_do_resume)
         ldmia   r0!, {r4 - r5}
         mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
         mcr     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
-        ldmia   r0, {r6 - r10}
+        ldmia   r0, {r6 - r11}
         mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
+#ifndef CONFIG_ARM_LPAE
         ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
         ALT_UP(orr      r1, r1, #TTB_FLAGS_UP)
+#endif
         mcr     p15, 0, r1, c2, c0, 0   @ TTB 0
         mcr     p15, 0, r7, c2, c0, 1   @ TTB 1
-        mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
+        mcr     p15, 0, r11, c2, c0, 2  @ TTB control register
         mrc     p15, 0, r4, c1, c0, 1   @ Read Auxiliary control register
         teq     r4, r9                  @ Is it already set?
         mcrne   p15, 0, r9, c1, c0, 1   @ No, so write it
@@ -379,12 +254,7 @@ __v7_setup:
         dsb
 #ifdef CONFIG_MMU
         mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs
-        mcr     p15, 0, r10, c2, c0, 2          @ TTB control register
-        ALT_SMP(orr     r4, r4, #TTB_FLAGS_SMP)
-        ALT_UP(orr      r4, r4, #TTB_FLAGS_UP)
-        ALT_SMP(orr     r8, r8, #TTB_FLAGS_SMP)
-        ALT_UP(orr      r8, r8, #TTB_FLAGS_UP)
-        mcr     p15, 0, r8, c2, c0, 1           @ load TTB1
+        v7_ttb_setup r10, r4, r8, r5            @ TTBCR, TTBRx setup
         ldr     r5, =PRRR                       @ PRRR
         ldr     r6, =NMRR                       @ NMRR
         mcr     p15, 0, r5, c10, c2, 0          @ write PRRR
@@ -406,16 +276,7 @@ __v7_setup:
         mov     pc, lr                          @ return to head.S:__ret
 ENDPROC(__v7_setup)
 
-        /*   AT
-         *  TFR   EV X F   I D LR    S
-         * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
-         * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
-         *    1    0 110       0011 1100 .111 1101 < we want
-         */
-        .type   v7_crval, #object
-v7_crval:
-        crval   clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
-
+        .align  2
 __v7_setup_stack:
         .space  4 * 11                          @ 11 registers
 
@@ -437,11 +298,11 @@ __v7_setup_stack:
          */
 .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
         ALT_SMP(.long   PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
-                        PMD_FLAGS_SMP | \mm_mmuflags)
+                        PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
         ALT_UP(.long    PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
-                        PMD_FLAGS_UP | \mm_mmuflags)
-        .long   PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | \
-                PMD_SECT_AP_READ | \io_mmuflags
+                        PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
+        .long   PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
         W(b)    \initfunc
         .long   cpu_arch_name
         .long   cpu_elf_name
@@ -454,6 +315,7 @@ __v7_setup_stack:
         .long   v7_cache_fns
 .endm
 
+#ifndef CONFIG_ARM_LPAE
         /*
          * ARM Ltd. Cortex A5 processor.
          */
@@ -473,6 +335,7 @@ __v7_ca9mp_proc_info:
         .long   0xff0ffff0
         __v7_proc __v7_ca9mp_setup
         .size   __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
+#endif  /* CONFIG_ARM_LPAE */
 
         /*
          * ARM Ltd. Cortex A15 processor.