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authorDan Williams <dan.j.williams@intel.com>2009-09-08 17:32:24 -0400
committerDan Williams <dan.j.williams@intel.com>2009-09-08 17:32:24 -0400
commita348a7e6fdbcd2d5192a09719a479bb238fde727 (patch)
tree5ff94185f4e5a810777469d7fe7832a8ec2d3430 /arch/arm/mm/proc-v6.S
parent808347f6a31792079e345ec865e9cfcb6e8ae6b2 (diff)
parent28d0325ce6e0a52f53d8af687e6427fee59004d3 (diff)
Merge commit 'v2.6.31-rc1' into dmaengine
Diffstat (limited to 'arch/arm/mm/proc-v6.S')
-rw-r--r--arch/arm/mm/proc-v6.S3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 087e239704df..524ddae92595 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -170,6 +170,9 @@ __v6_setup:
170#endif /* CONFIG_MMU */ 170#endif /* CONFIG_MMU */
171 adr r5, v6_crval 171 adr r5, v6_crval
172 ldmia r5, {r5, r6} 172 ldmia r5, {r5, r6}
173#ifdef CONFIG_CPU_ENDIAN_BE8
174 orr r6, r6, #1 << 25 @ big-endian page tables
175#endif
173 mrc p15, 0, r0, c1, c0, 0 @ read control register 176 mrc p15, 0, r0, c1, c0, 0 @ read control register
174 bic r0, r0, r5 @ clear bits them 177 bic r0, r0, r5 @ clear bits them
175 orr r0, r0, r6 @ set them 178 orr r0, r0, r6 @ set them