[ARM] Feroceon: L2 cache support

This patch adds support for the unified Feroceon L2 cache controller
as found in e.g. the Marvell Kirkwood and Marvell Discovery Duo
families of ARM SoCs.

Note that:

- Page table walks are outer uncacheable on Kirkwood and Discovery
  Duo, since the ARMv5 spec provides no way to indicate outer
  cacheability of page table walks (specifying it in TTBR[4:3] is
  an ARMv6+ feature).

  This requires adding L2 cache clean instructions to
  proc-feroceon.S (dcache_clean_area(), set_pte()) as well as to
  tlbflush.h ({flush,clean}_pmd_entry()).  The latter case is handled
  by defining a new TLB type (TLB_FEROCEON) which is almost identical
  to the v4wbi one but provides a TLB_L2CLEAN_FR flag.

- The Feroceon L2 cache controller supports L2 range (i.e. 'clean L2
  range by MVA' and 'invalidate L2 range by MVA') operations, and this
  patch uses those range operations for all Linux outer cache
  operations, as they are faster than the regular per-line operations.

  L2 range operations are not interruptible on this hardware, which
  avoids potential livelock issues, but can be bad for interrupt
  latency, so there is a compile-time tunable (MAX_RANGE_SIZE) which
  allows you to select the maximum range size to operate on at once.
  (Valid range is between one cache line and one 4KiB page, and must
  be a multiple of the line size.)

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>

1 files changed, 20 insertions, 0 deletions

diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index c279652a98fd..cecf96ee07d5 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -79,6 +79,13 @@ ENTRY(cpu_feroceon_proc_fin)
         mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
         msr     cpsr_c, ip
         bl      feroceon_flush_kern_cache_all
+
+#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+        mov     r0, #0
+        mcr     p15, 1, r0, c15, c9, 0          @ clean L2
+        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+#endif
+
         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
         bic     r0, r0, #0x1000                 @ ...i............
         bic     r0, r0, #0x000e                 @ ............wca.
@@ -382,10 +389,20 @@ ENTRY(feroceon_range_cache_fns)
 
         .align  5
 ENTRY(cpu_feroceon_dcache_clean_area)
+#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+        mov     r2, r0
+        mov     r3, r1
+#endif
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         add     r0, r0, #CACHE_DLINESIZE
         subs    r1, r1, #CACHE_DLINESIZE
         bhi     1b
+#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+1:      mcr     p15, 1, r2, c15, c9, 1          @ clean L2 entry
+        add     r2, r2, #CACHE_DLINESIZE
+        subs    r3, r3, #CACHE_DLINESIZE
+        bhi     1b
+#endif
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
@@ -449,6 +466,9 @@ ENTRY(cpu_feroceon_set_pte_ext)
         str     r2, [r0]                        @ hardware version
         mov     r0, r0
         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
+#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
+        mcr     p15, 1, r0, c15, c9, 1          @ clean L2 entry
+#endif
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 #endif
         mov     pc, lr