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| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-10-09 16:33:07 -0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-10-09 16:33:07 -0400 |
| commit | 6defd90433729c2d795865165cb34d938d8ff07c (patch) | |
| tree | ebb963c6db463296b8f926d79d7ddc8c1251ca24 /arch/arm/mm/proc-feroceon.S | |
| parent | c97f68145e8067b3ac4b126a6faebf90f9ffc302 (diff) | |
| parent | 99c6bb390cf599b9e0aa6e69beacc4e5d875bf77 (diff) | |
Merge branch 'for-rmk' of git://git.marvell.com/orion
Merge branch 'orion-devel' into devel
Diffstat (limited to 'arch/arm/mm/proc-feroceon.S')
| -rw-r--r-- | arch/arm/mm/proc-feroceon.S | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index 2b8bb383755e..0fe1f8fc3488 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S | |||
| @@ -80,7 +80,8 @@ ENTRY(cpu_feroceon_proc_fin) | |||
| 80 | msr cpsr_c, ip | 80 | msr cpsr_c, ip |
| 81 | bl feroceon_flush_kern_cache_all | 81 | bl feroceon_flush_kern_cache_all |
| 82 | 82 | ||
| 83 | #if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH) | 83 | #if defined(CONFIG_CACHE_FEROCEON_L2) && \ |
| 84 | !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) | ||
| 84 | mov r0, #0 | 85 | mov r0, #0 |
| 85 | mcr p15, 1, r0, c15, c9, 0 @ clean L2 | 86 | mcr p15, 1, r0, c15, c9, 0 @ clean L2 |
| 86 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | 87 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
| @@ -389,7 +390,8 @@ ENTRY(feroceon_range_cache_fns) | |||
| 389 | 390 | ||
| 390 | .align 5 | 391 | .align 5 |
| 391 | ENTRY(cpu_feroceon_dcache_clean_area) | 392 | ENTRY(cpu_feroceon_dcache_clean_area) |
| 392 | #if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH) | 393 | #if defined(CONFIG_CACHE_FEROCEON_L2) && \ |
| 394 | !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) | ||
| 393 | mov r2, r0 | 395 | mov r2, r0 |
| 394 | mov r3, r1 | 396 | mov r3, r1 |
| 395 | #endif | 397 | #endif |
| @@ -397,7 +399,8 @@ ENTRY(cpu_feroceon_dcache_clean_area) | |||
| 397 | add r0, r0, #CACHE_DLINESIZE | 399 | add r0, r0, #CACHE_DLINESIZE |
| 398 | subs r1, r1, #CACHE_DLINESIZE | 400 | subs r1, r1, #CACHE_DLINESIZE |
| 399 | bhi 1b | 401 | bhi 1b |
| 400 | #if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH) | 402 | #if defined(CONFIG_CACHE_FEROCEON_L2) && \ |
| 403 | !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) | ||
| 401 | 1: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry | 404 | 1: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry |
| 402 | add r2, r2, #CACHE_DLINESIZE | 405 | add r2, r2, #CACHE_DLINESIZE |
| 403 | subs r3, r3, #CACHE_DLINESIZE | 406 | subs r3, r3, #CACHE_DLINESIZE |
| @@ -449,7 +452,8 @@ ENTRY(cpu_feroceon_set_pte_ext) | |||
| 449 | armv3_set_pte_ext wc_disable=0 | 452 | armv3_set_pte_ext wc_disable=0 |
| 450 | mov r0, r0 | 453 | mov r0, r0 |
| 451 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 454 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
| 452 | #if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH) | 455 | #if defined(CONFIG_CACHE_FEROCEON_L2) && \ |
| 456 | !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) | ||
| 453 | mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry | 457 | mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry |
| 454 | #endif | 458 | #endif |
| 455 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | 459 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |