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authorDavid Woodhouse <David.Woodhouse@intel.com>2010-02-26 14:04:15 -0500
committerDavid Woodhouse <David.Woodhouse@intel.com>2010-02-26 14:06:24 -0500
commita7790532f5b7358c33a6b1834dc2b318de209f31 (patch)
tree0ceb9e24b3f54cb5c8453fb5a218e2a94a0f1cce /arch/arm/mm/proc-arm946.S
parent2764fb4244cc1bc08df3667924ca4a972e90ac70 (diff)
parent60b341b778cc2929df16c0a504c91621b3c6a4ad (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
The SmartMedia FTL code depends on new kfifo bits from 2.6.33
Diffstat (limited to 'arch/arm/mm/proc-arm946.S')
-rw-r--r--arch/arm/mm/proc-arm946.S11
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 40c0449a139b..9a951239c86c 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -183,16 +183,17 @@ ENTRY(arm946_coherent_user_range)
183 mov pc, lr 183 mov pc, lr
184 184
185/* 185/*
186 * flush_kern_dcache_page(void *page) 186 * flush_kern_dcache_area(void *addr, size_t size)
187 * 187 *
188 * Ensure no D cache aliasing occurs, either with itself or 188 * Ensure no D cache aliasing occurs, either with itself or
189 * the I cache 189 * the I cache
190 * 190 *
191 * - addr - page aligned address 191 * - addr - kernel address
192 * - size - region size
192 * (same as arm926) 193 * (same as arm926)
193 */ 194 */
194ENTRY(arm946_flush_kern_dcache_page) 195ENTRY(arm946_flush_kern_dcache_area)
195 add r1, r0, #PAGE_SZ 196 add r1, r0, r1
1961: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 1971: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
197 add r0, r0, #CACHE_DLINESIZE 198 add r0, r0, #CACHE_DLINESIZE
198 cmp r0, r1 199 cmp r0, r1
@@ -280,7 +281,7 @@ ENTRY(arm946_cache_fns)
280 .long arm946_flush_user_cache_range 281 .long arm946_flush_user_cache_range
281 .long arm946_coherent_kern_range 282 .long arm946_coherent_kern_range
282 .long arm946_coherent_user_range 283 .long arm946_coherent_user_range
283 .long arm946_flush_kern_dcache_page 284 .long arm946_flush_kern_dcache_area
284 .long arm946_dma_inv_range 285 .long arm946_dma_inv_range
285 .long arm946_dma_clean_range 286 .long arm946_dma_clean_range
286 .long arm946_dma_flush_range 287 .long arm946_dma_flush_range