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author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-06-05 18:57:04 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-06-05 18:57:04 -0400 |
commit | eb3d3ec567e868c8a3bfbfdfc9465ffd52983d11 (patch) | |
tree | 75acf38b8d73cd281e5ce4dcc941faf48e244b98 /arch/arm/mm/ioremap.c | |
parent | c3c55a07203947f72afa50a3218460b27307c47d (diff) | |
parent | bd63ce27d9d62bc40a962b991cbbbe4f0dc913d2 (diff) |
Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm into next
Pull ARM updates from Russell King:
- Major clean-up of the L2 cache support code. The existing mess was
becoming rather unmaintainable through all the additions that others
have done over time. This turns it into a much nicer structure, and
implements a few performance improvements as well.
- Clean up some of the CP15 control register tweaks for alignment
support, moving some code and data into alignment.c
- DMA properties for ARM, from Santosh and reviewed by DT people. This
adds DT properties to specify bus translations we can't discover
automatically, and to indicate whether devices are coherent.
- Hibernation support for ARM
- Make ftrace work with read-only text in modules
- add suspend support for PJ4B CPUs
- rework interrupt masking for undefined instruction handling, which
allows us to enable interrupts earlier in the handling of these
exceptions.
- support for big endian page tables
- fix stacktrace support to exclude stacktrace functions from the
trace, and add save_stack_trace_regs() implementation so that kprobes
can record stack traces.
- Add support for the Cortex-A17 CPU.
- Remove last vestiges of ARM710 support.
- Removal of ARM "meminfo" structure, finally converting us solely to
memblock to handle the early memory initialisation.
* 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (142 commits)
ARM: ensure C page table setup code follows assembly code (part II)
ARM: ensure C page table setup code follows assembly code
ARM: consolidate last remaining open-coded alignment trap enable
ARM: remove global cr_no_alignment
ARM: remove CPU_CP15 conditional from alignment.c
ARM: remove unused adjust_cr() function
ARM: move "noalign" command line option to alignment.c
ARM: provide common method to clear bits in CPU control register
ARM: 8025/1: Get rid of meminfo
ARM: 8060/1: mm: allow sub-architectures to override PCI I/O memory type
ARM: 8066/1: correction for ARM patch 8031/2
ARM: 8049/1: ftrace/add save_stack_trace_regs() implementation
ARM: 8065/1: remove last use of CONFIG_CPU_ARM710
ARM: 8062/1: Modify ldrt fixup handler to re-execute the userspace instruction
ARM: 8047/1: rwsem: use asm-generic rwsem implementation
ARM: l2c: trial at enabling some Cortex-A9 optimisations
ARM: l2c: add warnings for stuff modifying aux_ctrl register values
ARM: l2c: print a warning with L2C-310 caches if the cache size is modified
ARM: l2c: remove old .set_debug method
ARM: l2c: kill L2X0_AUX_CTRL_MASK before anyone else makes use of this
...
Diffstat (limited to 'arch/arm/mm/ioremap.c')
-rw-r--r-- | arch/arm/mm/ioremap.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index f9c32ba73544..d1e5ad7ab3bc 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c | |||
@@ -438,6 +438,13 @@ void __arm_iounmap(volatile void __iomem *io_addr) | |||
438 | EXPORT_SYMBOL(__arm_iounmap); | 438 | EXPORT_SYMBOL(__arm_iounmap); |
439 | 439 | ||
440 | #ifdef CONFIG_PCI | 440 | #ifdef CONFIG_PCI |
441 | static int pci_ioremap_mem_type = MT_DEVICE; | ||
442 | |||
443 | void pci_ioremap_set_mem_type(int mem_type) | ||
444 | { | ||
445 | pci_ioremap_mem_type = mem_type; | ||
446 | } | ||
447 | |||
441 | int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr) | 448 | int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr) |
442 | { | 449 | { |
443 | BUG_ON(offset + SZ_64K > IO_SPACE_LIMIT); | 450 | BUG_ON(offset + SZ_64K > IO_SPACE_LIMIT); |
@@ -445,7 +452,7 @@ int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr) | |||
445 | return ioremap_page_range(PCI_IO_VIRT_BASE + offset, | 452 | return ioremap_page_range(PCI_IO_VIRT_BASE + offset, |
446 | PCI_IO_VIRT_BASE + offset + SZ_64K, | 453 | PCI_IO_VIRT_BASE + offset + SZ_64K, |
447 | phys_addr, | 454 | phys_addr, |
448 | __pgprot(get_mem_type(MT_DEVICE)->prot_pte)); | 455 | __pgprot(get_mem_type(pci_ioremap_mem_type)->prot_pte)); |
449 | } | 456 | } |
450 | EXPORT_SYMBOL_GPL(pci_ioremap_io); | 457 | EXPORT_SYMBOL_GPL(pci_ioremap_io); |
451 | #endif | 458 | #endif |