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authorRussell King <rmk+kernel@arm.linux.org.uk>2014-03-15 12:48:13 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-05-29 19:48:08 -0400
commit09a5d180ed9d5aeb9bd6b0ba2c63ad4be05cb9b9 (patch)
tree1665f95058aea4c31e761e8b2e5dca86c7320e80 /arch/arm/mm/cache-l2x0.c
parentb98556f26dca7f7a7401cdb67b77848f1176a379 (diff)
ARM: l2c: clean up save/resume functions
Rename the pl310 save/resume functions to have a l2c310 prefix - this is it's official name. Use a local cached copy of the l2x0_base virtual address, and also realise that many of the resume function tails are the same as the enable functions, so make a call to the enable function instead of duplicating that code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/cache-l2x0.c')
-rw-r--r--arch/arm/mm/cache-l2x0.c109
1 files changed, 52 insertions, 57 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 4d985c17291c..e3f4fcbcc88b 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -385,17 +385,10 @@ static void l2x0_enable(void __iomem *base, u32 aux, unsigned num_lock)
385 385
386static void l2x0_resume(void) 386static void l2x0_resume(void)
387{ 387{
388 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { 388 void __iomem *base = l2x0_base;
389 /* restore aux ctrl and enable l2 */
390 l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));
391
392 writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base +
393 L2X0_AUX_CTRL);
394
395 l2x0_inv_all();
396 389
397 writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL); 390 if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN))
398 } 391 l2x0_enable(base, l2x0_saved_regs.aux_ctrl, 0);
399} 392}
400 393
401static const struct l2c_init_data l2x0_init_fns __initconst = { 394static const struct l2c_init_data l2x0_init_fns __initconst = {
@@ -438,10 +431,9 @@ static const struct l2c_init_data l2x0_init_fns __initconst = {
438 * Affects: store buffer 431 * Affects: store buffer
439 * store buffer is not automatically drained. 432 * store buffer is not automatically drained.
440 */ 433 */
441static void __init pl310_save(void __iomem *base) 434static void __init l2c310_save(void __iomem *base)
442{ 435{
443 u32 l2x0_revision = readl_relaxed(base + L2X0_CACHE_ID) & 436 unsigned revision;
444 L2X0_CACHE_ID_RTL_MASK;
445 437
446 l2x0_saved_regs.tag_latency = readl_relaxed(base + 438 l2x0_saved_regs.tag_latency = readl_relaxed(base +
447 L2X0_TAG_LATENCY_CTRL); 439 L2X0_TAG_LATENCY_CTRL);
@@ -452,49 +444,49 @@ static void __init pl310_save(void __iomem *base)
452 l2x0_saved_regs.filter_start = readl_relaxed(base + 444 l2x0_saved_regs.filter_start = readl_relaxed(base +
453 L2X0_ADDR_FILTER_START); 445 L2X0_ADDR_FILTER_START);
454 446
455 if (l2x0_revision >= L310_CACHE_ID_RTL_R2P0) { 447 revision = readl_relaxed(base + L2X0_CACHE_ID) &
456 /* 448 L2X0_CACHE_ID_RTL_MASK;
457 * From r2p0, there is Prefetch offset/control register 449
458 */ 450 /* From r2p0, there is Prefetch offset/control register */
451 if (revision >= L310_CACHE_ID_RTL_R2P0)
459 l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base + 452 l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base +
460 L2X0_PREFETCH_CTRL); 453 L2X0_PREFETCH_CTRL);
461 /* 454
462 * From r3p0, there is Power control register 455 /* From r3p0, there is Power control register */
463 */ 456 if (revision >= L310_CACHE_ID_RTL_R3P0)
464 if (l2x0_revision >= L310_CACHE_ID_RTL_R3P0) 457 l2x0_saved_regs.pwr_ctrl = readl_relaxed(base +
465 l2x0_saved_regs.pwr_ctrl = readl_relaxed(base + 458 L2X0_POWER_CTRL);
466 L2X0_POWER_CTRL);
467 }
468} 459}
469 460
470static void pl310_resume(void) 461static void l2c310_resume(void)
471{ 462{
472 u32 l2x0_revision; 463 void __iomem *base = l2x0_base;
464
465 if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) {
466 unsigned revision;
473 467
474 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
475 /* restore pl310 setup */ 468 /* restore pl310 setup */
476 writel_relaxed(l2x0_saved_regs.tag_latency, 469 writel_relaxed(l2x0_saved_regs.tag_latency,
477 l2x0_base + L2X0_TAG_LATENCY_CTRL); 470 base + L2X0_TAG_LATENCY_CTRL);
478 writel_relaxed(l2x0_saved_regs.data_latency, 471 writel_relaxed(l2x0_saved_regs.data_latency,
479 l2x0_base + L2X0_DATA_LATENCY_CTRL); 472 base + L2X0_DATA_LATENCY_CTRL);
480 writel_relaxed(l2x0_saved_regs.filter_end, 473 writel_relaxed(l2x0_saved_regs.filter_end,
481 l2x0_base + L2X0_ADDR_FILTER_END); 474 base + L2X0_ADDR_FILTER_END);
482 writel_relaxed(l2x0_saved_regs.filter_start, 475 writel_relaxed(l2x0_saved_regs.filter_start,
483 l2x0_base + L2X0_ADDR_FILTER_START); 476 base + L2X0_ADDR_FILTER_START);
484 477
485 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) & 478 revision = readl_relaxed(base + L2X0_CACHE_ID) &
486 L2X0_CACHE_ID_RTL_MASK; 479 L2X0_CACHE_ID_RTL_MASK;
487 480
488 if (l2x0_revision >= L310_CACHE_ID_RTL_R2P0) { 481 if (revision >= L310_CACHE_ID_RTL_R2P0)
489 writel_relaxed(l2x0_saved_regs.prefetch_ctrl, 482 writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
490 l2x0_base + L2X0_PREFETCH_CTRL); 483 base + L2X0_PREFETCH_CTRL);
491 if (l2x0_revision >= L310_CACHE_ID_RTL_R3P0) 484 if (revision >= L310_CACHE_ID_RTL_R3P0)
492 writel_relaxed(l2x0_saved_regs.pwr_ctrl, 485 writel_relaxed(l2x0_saved_regs.pwr_ctrl,
493 l2x0_base + L2X0_POWER_CTRL); 486 base + L2X0_POWER_CTRL);
494 }
495 }
496 487
497 l2x0_resume(); 488 l2c_enable(base, l2x0_saved_regs.aux_ctrl, 8);
489 }
498} 490}
499 491
500static void __init l2c310_fixup(void __iomem *base, u32 cache_id, 492static void __init l2c310_fixup(void __iomem *base, u32 cache_id,
@@ -530,7 +522,7 @@ static const struct l2c_init_data l2c310_init_fns __initconst = {
530 .num_lock = 8, 522 .num_lock = 8,
531 .enable = l2c_enable, 523 .enable = l2c_enable,
532 .fixup = l2c310_fixup, 524 .fixup = l2c310_fixup,
533 .save = pl310_save, 525 .save = l2c310_save,
534 .outer_cache = { 526 .outer_cache = {
535 .inv_range = l2x0_inv_range, 527 .inv_range = l2x0_inv_range,
536 .clean_range = l2x0_clean_range, 528 .clean_range = l2x0_clean_range,
@@ -538,7 +530,7 @@ static const struct l2c_init_data l2c310_init_fns __initconst = {
538 .flush_all = l2x0_flush_all, 530 .flush_all = l2x0_flush_all,
539 .disable = l2x0_disable, 531 .disable = l2x0_disable,
540 .sync = l2x0_cache_sync, 532 .sync = l2x0_cache_sync,
541 .resume = pl310_resume, 533 .resume = l2c310_resume,
542 }, 534 },
543}; 535};
544 536
@@ -744,7 +736,7 @@ static const struct l2c_init_data of_pl310_data __initconst = {
744 .of_parse = pl310_of_parse, 736 .of_parse = pl310_of_parse,
745 .enable = l2c_enable, 737 .enable = l2c_enable,
746 .fixup = l2c310_fixup, 738 .fixup = l2c310_fixup,
747 .save = pl310_save, 739 .save = l2c310_save,
748 .outer_cache = { 740 .outer_cache = {
749 .inv_range = l2x0_inv_range, 741 .inv_range = l2x0_inv_range,
750 .clean_range = l2x0_clean_range, 742 .clean_range = l2x0_clean_range,
@@ -752,7 +744,7 @@ static const struct l2c_init_data of_pl310_data __initconst = {
752 .flush_all = l2x0_flush_all, 744 .flush_all = l2x0_flush_all,
753 .disable = l2x0_disable, 745 .disable = l2x0_disable,
754 .sync = l2x0_cache_sync, 746 .sync = l2x0_cache_sync,
755 .resume = pl310_resume, 747 .resume = l2c310_resume,
756 }, 748 },
757}; 749};
758 750
@@ -862,10 +854,11 @@ static void aurora_save(void __iomem *base)
862 854
863static void aurora_resume(void) 855static void aurora_resume(void)
864{ 856{
865 if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { 857 void __iomem *base = l2x0_base;
866 writel_relaxed(l2x0_saved_regs.aux_ctrl, 858
867 l2x0_base + L2X0_AUX_CTRL); 859 if (!(readl(base + L2X0_CTRL) & L2X0_CTRL_EN)) {
868 writel_relaxed(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL); 860 writel_relaxed(l2x0_saved_regs.aux_ctrl, base + L2X0_AUX_CTRL);
861 writel_relaxed(l2x0_saved_regs.ctrl, base + L2X0_CTRL);
869 } 862 }
870} 863}
871 864
@@ -1089,7 +1082,7 @@ static const struct l2c_init_data of_bcm_l2x0_data __initconst = {
1089 .of_parse = pl310_of_parse, 1082 .of_parse = pl310_of_parse,
1090 .enable = l2c_enable, 1083 .enable = l2c_enable,
1091 .fixup = l2c310_fixup, 1084 .fixup = l2c310_fixup,
1092 .save = pl310_save, 1085 .save = l2c310_save,
1093 .outer_cache = { 1086 .outer_cache = {
1094 .inv_range = bcm_inv_range, 1087 .inv_range = bcm_inv_range,
1095 .clean_range = bcm_clean_range, 1088 .clean_range = bcm_clean_range,
@@ -1097,7 +1090,7 @@ static const struct l2c_init_data of_bcm_l2x0_data __initconst = {
1097 .flush_all = l2x0_flush_all, 1090 .flush_all = l2x0_flush_all,
1098 .disable = l2x0_disable, 1091 .disable = l2x0_disable,
1099 .sync = l2x0_cache_sync, 1092 .sync = l2x0_cache_sync,
1100 .resume = pl310_resume, 1093 .resume = l2c310_resume,
1101 }, 1094 },
1102}; 1095};
1103 1096
@@ -1111,14 +1104,16 @@ static void __init tauros3_save(void __iomem *base)
1111 1104
1112static void tauros3_resume(void) 1105static void tauros3_resume(void)
1113{ 1106{
1114 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { 1107 void __iomem *base = l2x0_base;
1108
1109 if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) {
1115 writel_relaxed(l2x0_saved_regs.aux2_ctrl, 1110 writel_relaxed(l2x0_saved_regs.aux2_ctrl,
1116 l2x0_base + TAUROS3_AUX2_CTRL); 1111 base + TAUROS3_AUX2_CTRL);
1117 writel_relaxed(l2x0_saved_regs.prefetch_ctrl, 1112 writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
1118 l2x0_base + L2X0_PREFETCH_CTRL); 1113 base + L2X0_PREFETCH_CTRL);
1119 }
1120 1114
1121 l2x0_resume(); 1115 l2c_enable(base, l2x0_saved_regs.aux_ctrl, 8);
1116 }
1122} 1117}
1123 1118
1124static const struct l2c_init_data of_tauros3_data __initconst = { 1119static const struct l2c_init_data of_tauros3_data __initconst = {