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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-12-04 11:13:29 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-12-14 14:21:42 -0500
commitff2e27ae0b17f53a6a289c87d325f706598f3788 (patch)
tree1288f491bce11b3d8a6d48604fd00d68bea6eb98 /arch/arm/mach-vexpress
parent384895330e0f3954d9478fd0853145f9c169df12 (diff)
ARM: GIC: consolidate gic_cpu_base_addr to common GIC code
Every architecture using the GIC has a gic_cpu_base_addr pointer for GIC 0 for their entry assembly code to use to decode the cause of the current interrupt. Move this into the common GIC code. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-vexpress')
-rw-r--r--arch/arm/mach-vexpress/core.h2
-rw-r--r--arch/arm/mach-vexpress/ct-ca9x4.c6
2 files changed, 2 insertions, 6 deletions
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index 57dd95ce41f9..362780d868de 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -22,5 +22,3 @@ struct map_desc;
22 22
23void v2m_map_io(struct map_desc *tile, size_t num); 23void v2m_map_io(struct map_desc *tile, size_t num);
24extern struct sys_timer v2m_timer; 24extern struct sys_timer v2m_timer;
25
26extern void __iomem *gic_cpu_base_addr;
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 25a3ca6e5a48..8e0a3b7c8638 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -60,12 +60,10 @@ static void __init ct_ca9x4_map_io(void)
60 v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc)); 60 v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
61} 61}
62 62
63void __iomem *gic_cpu_base_addr;
64
65static void __init ct_ca9x4_init_irq(void) 63static void __init ct_ca9x4_init_irq(void)
66{ 64{
67 gic_cpu_base_addr = MMIO_P2V(A9_MPCORE_GIC_CPU); 65 gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
68 gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST), gic_cpu_base_addr); 66 MMIO_P2V(A9_MPCORE_GIC_CPU));
69} 67}
70 68
71#if 0 69#if 0