Merge branch 'smp' into misc

Conflicts:
	arch/arm/kernel/entry-armv.S
	arch/arm/mm/ioremap.c

5 files changed, 32 insertions, 71 deletions

diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 73fb1a551ec6..608a1372b172 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -75,14 +75,14 @@ void __init ux500_init_irq(void)
 static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
 {
         /* wait for the operation to complete */
-        while (readl(reg) & mask)
+        while (readl_relaxed(reg) & mask)
                 ;
 }
 
 static inline void ux500_cache_sync(void)
 {
         void __iomem *base = __io_address(UX500_L2CC_BASE);
-        writel(0, base + L2X0_CACHE_SYNC);
+        writel_relaxed(0, base + L2X0_CACHE_SYNC);
         ux500_cache_wait(base + L2X0_CACHE_SYNC, 1);
 }
 
@@ -107,7 +107,7 @@ static void ux500_l2x0_inv_all(void)
         uint32_t l2x0_way_mask = (1<<16) - 1;   /* Bitmask of active ways */
 
         /* invalidate all ways */
-        writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
+        writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
         ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
         ux500_cache_sync();
 }
diff --git a/arch/arm/mach-ux500/headsmp.S b/arch/arm/mach-ux500/headsmp.S
index a6be2cdf2b2f..64fa451edcfd 100644
--- a/arch/arm/mach-ux500/headsmp.S
+++ b/arch/arm/mach-ux500/headsmp.S
@@ -23,7 +23,6 @@ ENTRY(u8500_secondary_startup)
         ldmia   r4, {r5, r6}
         sub     r4, r4, r5
         add     r6, r6, r4
-        dsb
 pen:    ldr     r7, [r6]
         cmp     r7, r0
         bne     pen
diff --git a/arch/arm/mach-ux500/hotplug.c b/arch/arm/mach-ux500/hotplug.c
index b782a03024be..dd8037ebccf8 100644
--- a/arch/arm/mach-ux500/hotplug.c
+++ b/arch/arm/mach-ux500/hotplug.c
@@ -11,14 +11,11 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/smp.h>
-#include <linux/completion.h>
 
 #include <asm/cacheflush.h>
 
 extern volatile int pen_release;
 
-static DECLARE_COMPLETION(cpu_killed);
-
 static inline void platform_do_lowpower(unsigned int cpu)
 {
         flush_cache_all();
@@ -38,7 +35,7 @@ static inline void platform_do_lowpower(unsigned int cpu)
 
 int platform_cpu_kill(unsigned int cpu)
 {
-        return wait_for_completion_timeout(&cpu_killed, 5000);
+        return 1;
 }
 
 /*
@@ -48,19 +45,6 @@ int platform_cpu_kill(unsigned int cpu)
  */
 void platform_cpu_die(unsigned int cpu)
 {
-#ifdef DEBUG
-        unsigned int this_cpu = hard_smp_processor_id();
-
-        if (cpu != this_cpu) {
-                printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n",
-                           this_cpu, cpu);
-                BUG();
-        }
-#endif
-
-        printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
-        complete(&cpu_killed);
-
         /* directly enter low power state, skipping secure registers */
         platform_do_lowpower(cpu);
 }
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
index 197e8417375e..ca2b15b1b3b1 100644
--- a/arch/arm/mach-ux500/include/mach/smp.h
+++ b/arch/arm/mach-ux500/include/mach/smp.h
@@ -10,7 +10,6 @@
 #define ASMARM_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
-#include <asm/smp_mpidr.h>
 
 /* This is required to wakeup the secondary core */
 extern void u8500_secondary_startup(void);
@@ -18,8 +17,8 @@ extern void u8500_secondary_startup(void);
 /*
  * We use IRQ1 as the IPI
  */
-static inline void smp_cross_call(const struct cpumask *mask)
+static inline void smp_cross_call(const struct cpumask *mask, int ipi)
 {
-        gic_raise_softirq(mask, 1);
+        gic_raise_softirq(mask, ipi);
 }
 #endif
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index 9e4c678de785..f71175a766d7 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -18,7 +18,6 @@
 #include <linux/io.h>
 
 #include <asm/cacheflush.h>
-#include <asm/localtimer.h>
 #include <asm/smp_scu.h>
 #include <mach/hardware.h>
 
@@ -28,17 +27,23 @@
  */
 volatile int __cpuinitdata pen_release = -1;
 
-static unsigned int __init get_core_count(void)
+/*
+ * Write pen_release in a way that is guaranteed to be visible to all
+ * observers, irrespective of whether they're taking part in coherency
+ * or not.  This is necessary for the hotplug code to work reliably.
+ */
+static void write_pen_release(int val)
 {
-        return scu_get_core_count(__io_address(UX500_SCU_BASE));
+        pen_release = val;
+        smp_wmb();
+        __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
+        outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
 }
 
 static DEFINE_SPINLOCK(boot_lock);
 
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
-        trace_hardirqs_off();
-
         /*
          * if any interrupts are already enabled for the primary
          * core (e.g. timer irq), then they will not have been enabled
@@ -50,7 +55,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
          * let the primary processor know we're out of the
          * pen, then head off into the C entry point
          */
-        pen_release = -1;
+        write_pen_release(-1);
 
         /*
          * Synchronise with the boot thread.
@@ -74,11 +79,9 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
          * the holding pen - release it, then wait for it to flag
          * that it has been released by resetting pen_release.
          */
-        pen_release = cpu;
-        __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
-        outer_clean_range(__pa(&pen_release), __pa(&pen_release) + 1);
+        write_pen_release(cpu);
 
-        smp_cross_call(cpumask_of(cpu));
+        smp_cross_call(cpumask_of(cpu), 1);
 
         timeout = jiffies + (1 * HZ);
         while (time_before(jiffies, timeout)) {
@@ -97,9 +100,6 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 
 static void __init wakeup_secondary(void)
 {
-        /* nobody is to be released from the pen yet */
-        pen_release = -1;
-
         /*
          * write the address of secondary startup into the backup ram register
          * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
@@ -126,40 +126,26 @@ static void __init wakeup_secondary(void)
  */
 void __init smp_init_cpus(void)
 {
-        unsigned int i, ncores = get_core_count();
+        unsigned int i, ncores;
 
-        for (i = 0; i < ncores; i++)
-                set_cpu_possible(i, true);
-}
-
-void __init smp_prepare_cpus(unsigned int max_cpus)
-{
-        unsigned int ncores = get_core_count();
-        unsigned int cpu = smp_processor_id();
-        int i;
+        ncores = scu_get_core_count(__io_address(UX500_SCU_BASE));
 
         /* sanity check */
-        if (ncores == 0) {
-                printk(KERN_ERR
-                       "U8500: strange CM count of 0? Default to 1\n");
-                ncores = 1;
-        }
-
-        if (ncores > num_possible_cpus())       {
+        if (ncores > NR_CPUS) {
                 printk(KERN_WARNING
                        "U8500: no. of cores (%d) greater than configured "
                        "maximum of %d - clipping\n",
-                       ncores, num_possible_cpus());
-                ncores = num_possible_cpus();
+                       ncores, NR_CPUS);
+                ncores = NR_CPUS;
         }
 
-        smp_store_cpu_info(cpu);
+        for (i = 0; i < ncores; i++)
+                set_cpu_possible(i, true);
+}
 
-        /*
-         * are we trying to boot more cores than exist?
-         */
-        if (max_cpus > ncores)
-                max_cpus = ncores;
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+        int i;
 
         /*
          * Initialise the present map, which describes the set of CPUs
@@ -168,13 +154,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
         for (i = 0; i < max_cpus; i++)
                 set_cpu_present(i, true);
 
-        if (max_cpus > 1) {
-                /*
-                 * Enable the local timer or broadcast device for the
-                 * boot CPU, but only if we have more than one CPU.
-                 */
-                percpu_timer_setup();
-                scu_enable(__io_address(UX500_SCU_BASE));
-                wakeup_secondary();
-        }
+        scu_enable(__io_address(UX500_SCU_BASE));
+        wakeup_secondary();
 }