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authorAndreas Westin <andreas.westin@stericsson.com>2012-05-10 04:14:06 -0400
committerHerbert Xu <herbert@gondor.apana.org.au>2012-05-15 03:25:32 -0400
commit585d188f8072aa3722d5c1ec1f0f2ea82e474778 (patch)
tree6b988ce236ed31fec51099458e23190737ac3218 /arch/arm/mach-ux500/clock.c
parentb29e2679d0da91c60d3ac190d9c3bd65ac2f68c5 (diff)
mach-ux500: crypto - core support for CRYP/HASH module.
This adds the required platform data and calls to enable the CRYP/HASH driver. Signed-off-by: Andreas Westin <andreas.westin@stericsson.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'arch/arm/mach-ux500/clock.c')
-rw-r--r--arch/arm/mach-ux500/clock.c18
1 files changed, 10 insertions, 8 deletions
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index ec35f0aa5665..2efc1fe236c3 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -382,14 +382,15 @@ static DEFINE_PRCC_CLK(5, usb, 0, 0, NULL);
382/* Peripheral Cluster #6 */ 382/* Peripheral Cluster #6 */
383 383
384/* MTU ID in data */ 384/* MTU ID in data */
385static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 8, -1, NULL, clk_mtu_get_rate, 1); 385static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 9, -1, NULL, clk_mtu_get_rate, 1);
386static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 7, -1, NULL, clk_mtu_get_rate, 0); 386static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 8, -1, NULL, clk_mtu_get_rate, 0);
387static DEFINE_PRCC_CLK(6, cfgreg, 6, 6, NULL); 387static DEFINE_PRCC_CLK(6, cfgreg, 7, 7, NULL);
388static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL); 388static DEFINE_PRCC_CLK(6, hash1, 6, -1, NULL);
389static DEFINE_PRCC_CLK(6, unipro, 4, 1, &clk_uniproclk); 389static DEFINE_PRCC_CLK(6, unipro, 5, 1, &clk_uniproclk);
390static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL); 390static DEFINE_PRCC_CLK(6, pka, 4, -1, NULL);
391static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL); 391static DEFINE_PRCC_CLK(6, hash0, 3, -1, NULL);
392static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL); 392static DEFINE_PRCC_CLK(6, cryp0, 2, -1, NULL);
393static DEFINE_PRCC_CLK(6, cryp1, 1, -1, NULL);
393static DEFINE_PRCC_CLK(6, rng, 0, 0, &clk_rngclk); 394static DEFINE_PRCC_CLK(6, rng, 0, 0, &clk_rngclk);
394 395
395static struct clk clk_dummy_apb_pclk = { 396static struct clk clk_dummy_apb_pclk = {
@@ -431,6 +432,7 @@ static struct clk_lookup u8500_clks[] = {
431 CLK(pka, "pka", NULL), 432 CLK(pka, "pka", NULL),
432 CLK(hash0, "hash0", NULL), 433 CLK(hash0, "hash0", NULL),
433 CLK(cryp0, "cryp0", NULL), 434 CLK(cryp0, "cryp0", NULL),
435 CLK(cryp1, "cryp1", NULL),
434 436
435 /* PRCMU level clock gating */ 437 /* PRCMU level clock gating */
436 438