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authorColin Cross <ccross@android.com>2011-02-12 19:05:31 -0500
committerColin Cross <ccross@android.com>2011-02-21 03:10:11 -0500
commitf151961173bf28047d01b410969f05e485f56d7e (patch)
tree02a9d357cf99d2002b98c8a18002322ef5c5c3d8 /arch/arm/mach-tegra
parent3ec349fbf1e88e84d4dffc54b6cb32129a32b7b0 (diff)
ARM: tegra: clock: Move unshared clk struct members into union
Creates a union of a struct for each type of clock to reduce memory usage and clarify which members are used by all clocks and which are used by a single type. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r--arch/arm/mach-tegra/clock.h85
-rw-r--r--arch/arm/mach-tegra/tegra2_clocks.c234
2 files changed, 176 insertions, 143 deletions
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index 198f2344d02f..20f0ce69bbaf 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -47,7 +47,7 @@ struct clk_mux_sel {
47 u32 value; 47 u32 value;
48}; 48};
49 49
50struct clk_pll_table { 50struct clk_pll_freq_table {
51 unsigned long input_rate; 51 unsigned long input_rate;
52 unsigned long output_rate; 52 unsigned long output_rate;
53 u16 n; 53 u16 n;
@@ -74,51 +74,54 @@ enum clk_state {
74 74
75struct clk { 75struct clk {
76 /* node for master clocks list */ 76 /* node for master clocks list */
77 struct list_head node; 77 struct list_head node; /* node for list of all clocks */
78 struct list_head children; /* list of children */ 78 struct list_head children; /* list of children */
79 struct list_head sibling; /* node for children */ 79 struct list_head sibling; /* node for children */
80#ifdef CONFIG_DEBUG_FS 80 struct clk_lookup lookup;
81 struct dentry *dent; 81
82 struct dentry *parent_dent;
83#endif
84 struct clk_ops *ops;
85 struct clk *parent;
86 struct clk_lookup lookup;
87 unsigned long rate;
88 unsigned long max_rate;
89 u32 flags;
90 u32 refcnt;
91 const char *name;
92 u32 reg;
93 u32 reg_shift;
94 unsigned int clk_num;
95 enum clk_state state;
96#ifdef CONFIG_DEBUG_FS 82#ifdef CONFIG_DEBUG_FS
97 bool set; 83 struct dentry *dent;
84 bool set;
98#endif 85#endif
86 struct clk_ops *ops;
87 unsigned long rate;
88 unsigned long max_rate;
89 u32 flags;
90 const char *name;
91
92 u32 refcnt;
93 enum clk_state state;
94 struct clk *parent;
95 u32 div;
96 u32 mul;
99 97
100 /* PLL */
101 unsigned long input_min;
102 unsigned long input_max;
103 unsigned long cf_min;
104 unsigned long cf_max;
105 unsigned long vco_min;
106 unsigned long vco_max;
107 const struct clk_pll_table *pll_table;
108 int pll_lock_delay;
109
110 /* DIV */
111 u32 div;
112 u32 mul;
113
114 /* MUX */
115 const struct clk_mux_sel *inputs; 98 const struct clk_mux_sel *inputs;
116 u32 sel; 99 u32 reg;
117 u32 reg_mask; 100 u32 reg_shift;
118 101
119 /* Virtual cpu clock */ 102 union {
120 struct clk *main; 103 struct {
121 struct clk *backup; 104 unsigned int clk_num;
105 } periph;
106 struct {
107 unsigned long input_min;
108 unsigned long input_max;
109 unsigned long cf_min;
110 unsigned long cf_max;
111 unsigned long vco_min;
112 unsigned long vco_max;
113 const struct clk_pll_freq_table *freq_table;
114 int lock_delay;
115 } pll;
116 struct {
117 u32 sel;
118 u32 reg_mask;
119 } mux;
120 struct {
121 struct clk *main;
122 struct clk *backup;
123 } cpu;
124 } u;
122}; 125};
123 126
124 127
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index a36bda93112a..324c4d33ad16 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -109,9 +109,9 @@
109 109
110#define PLLE_MISC_READY (1 << 15) 110#define PLLE_MISC_READY (1 << 15)
111 111
112#define PERIPH_CLK_TO_ENB_REG(c) ((c->clk_num / 32) * 4) 112#define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4)
113#define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->clk_num / 32) * 8) 113#define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8)
114#define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->clk_num % 32)) 114#define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32))
115 115
116#define SUPER_CLK_MUX 0x00 116#define SUPER_CLK_MUX 0x00
117#define SUPER_STATE_SHIFT 28 117#define SUPER_STATE_SHIFT 28
@@ -378,24 +378,24 @@ static void tegra2_cpu_clk_disable(struct clk *c)
378static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate) 378static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate)
379{ 379{
380 int ret; 380 int ret;
381 ret = clk_set_parent_locked(c->parent, c->backup); 381 ret = clk_set_parent_locked(c->parent, c->u.cpu.backup);
382 if (ret) { 382 if (ret) {
383 pr_err("Failed to switch cpu to clock %s\n", c->backup->name); 383 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.backup->name);
384 return ret; 384 return ret;
385 } 385 }
386 386
387 if (rate == c->backup->rate) 387 if (rate == c->u.cpu.backup->rate)
388 goto out; 388 goto out;
389 389
390 ret = clk_set_rate_locked(c->main, rate); 390 ret = clk_set_rate_locked(c->u.cpu.main, rate);
391 if (ret) { 391 if (ret) {
392 pr_err("Failed to change cpu pll to %lu\n", rate); 392 pr_err("Failed to change cpu pll to %lu\n", rate);
393 return ret; 393 return ret;
394 } 394 }
395 395
396 ret = clk_set_parent_locked(c->parent, c->main); 396 ret = clk_set_parent_locked(c->parent, c->u.cpu.main);
397 if (ret) { 397 if (ret) {
398 pr_err("Failed to switch cpu to clock %s\n", c->main->name); 398 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name);
399 return ret; 399 return ret;
400 } 400 }
401 401
@@ -543,7 +543,7 @@ static struct clk_ops tegra_blink_clk_ops = {
543/* PLL Functions */ 543/* PLL Functions */
544static int tegra2_pll_clk_wait_for_lock(struct clk *c) 544static int tegra2_pll_clk_wait_for_lock(struct clk *c)
545{ 545{
546 udelay(c->pll_lock_delay); 546 udelay(c->u.pll.lock_delay);
547 547
548 return 0; 548 return 0;
549} 549}
@@ -600,12 +600,12 @@ static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
600{ 600{
601 u32 val; 601 u32 val;
602 unsigned long input_rate; 602 unsigned long input_rate;
603 const struct clk_pll_table *sel; 603 const struct clk_pll_freq_table *sel;
604 604
605 pr_debug("%s: %s %lu\n", __func__, c->name, rate); 605 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
606 606
607 input_rate = c->parent->rate; 607 input_rate = c->parent->rate;
608 for (sel = c->pll_table; sel->input_rate != 0; sel++) { 608 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
609 if (sel->input_rate == input_rate && sel->output_rate == rate) { 609 if (sel->input_rate == input_rate && sel->output_rate == rate) {
610 c->mul = sel->n; 610 c->mul = sel->n;
611 c->div = sel->m * sel->p; 611 c->div = sel->m * sel->p;
@@ -1138,7 +1138,7 @@ static struct clk tegra_clk_32k = {
1138 .max_rate = 32768, 1138 .max_rate = 32768,
1139}; 1139};
1140 1140
1141static struct clk_pll_table tegra_pll_s_table[] = { 1141static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
1142 {32768, 12000000, 366, 1, 1, 0}, 1142 {32768, 12000000, 366, 1, 1, 0},
1143 {32768, 13000000, 397, 1, 1, 0}, 1143 {32768, 13000000, 397, 1, 1, 0},
1144 {32768, 19200000, 586, 1, 1, 0}, 1144 {32768, 19200000, 586, 1, 1, 0},
@@ -1150,17 +1150,19 @@ static struct clk tegra_pll_s = {
1150 .name = "pll_s", 1150 .name = "pll_s",
1151 .flags = PLL_ALT_MISC_REG, 1151 .flags = PLL_ALT_MISC_REG,
1152 .ops = &tegra_pll_ops, 1152 .ops = &tegra_pll_ops,
1153 .reg = 0xf0,
1154 .input_min = 32768,
1155 .input_max = 32768,
1156 .parent = &tegra_clk_32k, 1153 .parent = &tegra_clk_32k,
1157 .cf_min = 0, /* FIXME */
1158 .cf_max = 0, /* FIXME */
1159 .vco_min = 12000000,
1160 .vco_max = 26000000,
1161 .pll_table = tegra_pll_s_table,
1162 .max_rate = 26000000, 1154 .max_rate = 26000000,
1163 .pll_lock_delay = 300, 1155 .reg = 0xf0,
1156 .u.pll = {
1157 .input_min = 32768,
1158 .input_max = 32768,
1159 .cf_min = 0, /* FIXME */
1160 .cf_max = 0, /* FIXME */
1161 .vco_min = 12000000,
1162 .vco_max = 26000000,
1163 .freq_table = tegra_pll_s_freq_table,
1164 .lock_delay = 300,
1165 },
1164}; 1166};
1165 1167
1166static struct clk_mux_sel tegra_clk_m_sel[] = { 1168static struct clk_mux_sel tegra_clk_m_sel[] = {
@@ -1168,18 +1170,18 @@ static struct clk_mux_sel tegra_clk_m_sel[] = {
1168 { .input = &tegra_pll_s, .value = 1}, 1170 { .input = &tegra_pll_s, .value = 1},
1169 { 0, 0}, 1171 { 0, 0},
1170}; 1172};
1173
1171static struct clk tegra_clk_m = { 1174static struct clk tegra_clk_m = {
1172 .name = "clk_m", 1175 .name = "clk_m",
1173 .flags = ENABLE_ON_INIT, 1176 .flags = ENABLE_ON_INIT,
1174 .ops = &tegra_clk_m_ops, 1177 .ops = &tegra_clk_m_ops,
1175 .inputs = tegra_clk_m_sel, 1178 .inputs = tegra_clk_m_sel,
1176 .reg = 0x1fc, 1179 .reg = 0x1fc,
1177 .reg_mask = (1<<28),
1178 .reg_shift = 28, 1180 .reg_shift = 28,
1179 .max_rate = 26000000, 1181 .max_rate = 26000000,
1180}; 1182};
1181 1183
1182static struct clk_pll_table tegra_pll_c_table[] = { 1184static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
1183 { 0, 0, 0, 0, 0, 0 }, 1185 { 0, 0, 0, 0, 0, 0 },
1184}; 1186};
1185 1187
@@ -1188,16 +1190,18 @@ static struct clk tegra_pll_c = {
1188 .flags = PLL_HAS_CPCON, 1190 .flags = PLL_HAS_CPCON,
1189 .ops = &tegra_pll_ops, 1191 .ops = &tegra_pll_ops,
1190 .reg = 0x80, 1192 .reg = 0x80,
1191 .input_min = 2000000,
1192 .input_max = 31000000,
1193 .parent = &tegra_clk_m, 1193 .parent = &tegra_clk_m,
1194 .cf_min = 1000000,
1195 .cf_max = 6000000,
1196 .vco_min = 20000000,
1197 .vco_max = 1400000000,
1198 .pll_table = tegra_pll_c_table,
1199 .max_rate = 600000000, 1194 .max_rate = 600000000,
1200 .pll_lock_delay = 300, 1195 .u.pll = {
1196 .input_min = 2000000,
1197 .input_max = 31000000,
1198 .cf_min = 1000000,
1199 .cf_max = 6000000,
1200 .vco_min = 20000000,
1201 .vco_max = 1400000000,
1202 .freq_table = tegra_pll_c_freq_table,
1203 .lock_delay = 300,
1204 },
1201}; 1205};
1202 1206
1203static struct clk tegra_pll_c_out1 = { 1207static struct clk tegra_pll_c_out1 = {
@@ -1210,7 +1214,7 @@ static struct clk tegra_pll_c_out1 = {
1210 .max_rate = 600000000, 1214 .max_rate = 600000000,
1211}; 1215};
1212 1216
1213static struct clk_pll_table tegra_pll_m_table[] = { 1217static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
1214 { 12000000, 666000000, 666, 12, 1, 8}, 1218 { 12000000, 666000000, 666, 12, 1, 8},
1215 { 13000000, 666000000, 666, 13, 1, 8}, 1219 { 13000000, 666000000, 666, 13, 1, 8},
1216 { 19200000, 666000000, 555, 16, 1, 8}, 1220 { 19200000, 666000000, 555, 16, 1, 8},
@@ -1227,16 +1231,18 @@ static struct clk tegra_pll_m = {
1227 .flags = PLL_HAS_CPCON, 1231 .flags = PLL_HAS_CPCON,
1228 .ops = &tegra_pll_ops, 1232 .ops = &tegra_pll_ops,
1229 .reg = 0x90, 1233 .reg = 0x90,
1230 .input_min = 2000000,
1231 .input_max = 31000000,
1232 .parent = &tegra_clk_m, 1234 .parent = &tegra_clk_m,
1233 .cf_min = 1000000,
1234 .cf_max = 6000000,
1235 .vco_min = 20000000,
1236 .vco_max = 1200000000,
1237 .pll_table = tegra_pll_m_table,
1238 .max_rate = 800000000, 1235 .max_rate = 800000000,
1239 .pll_lock_delay = 300, 1236 .u.pll = {
1237 .input_min = 2000000,
1238 .input_max = 31000000,
1239 .cf_min = 1000000,
1240 .cf_max = 6000000,
1241 .vco_min = 20000000,
1242 .vco_max = 1200000000,
1243 .freq_table = tegra_pll_m_freq_table,
1244 .lock_delay = 300,
1245 },
1240}; 1246};
1241 1247
1242static struct clk tegra_pll_m_out1 = { 1248static struct clk tegra_pll_m_out1 = {
@@ -1249,7 +1255,7 @@ static struct clk tegra_pll_m_out1 = {
1249 .max_rate = 600000000, 1255 .max_rate = 600000000,
1250}; 1256};
1251 1257
1252static struct clk_pll_table tegra_pll_p_table[] = { 1258static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
1253 { 12000000, 216000000, 432, 12, 2, 8}, 1259 { 12000000, 216000000, 432, 12, 2, 8},
1254 { 13000000, 216000000, 432, 13, 2, 8}, 1260 { 13000000, 216000000, 432, 13, 2, 8},
1255 { 19200000, 216000000, 90, 4, 2, 1}, 1261 { 19200000, 216000000, 90, 4, 2, 1},
@@ -1266,16 +1272,18 @@ static struct clk tegra_pll_p = {
1266 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 1272 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
1267 .ops = &tegra_pll_ops, 1273 .ops = &tegra_pll_ops,
1268 .reg = 0xa0, 1274 .reg = 0xa0,
1269 .input_min = 2000000,
1270 .input_max = 31000000,
1271 .parent = &tegra_clk_m, 1275 .parent = &tegra_clk_m,
1272 .cf_min = 1000000,
1273 .cf_max = 6000000,
1274 .vco_min = 20000000,
1275 .vco_max = 1400000000,
1276 .pll_table = tegra_pll_p_table,
1277 .max_rate = 432000000, 1276 .max_rate = 432000000,
1278 .pll_lock_delay = 300, 1277 .u.pll = {
1278 .input_min = 2000000,
1279 .input_max = 31000000,
1280 .cf_min = 1000000,
1281 .cf_max = 6000000,
1282 .vco_min = 20000000,
1283 .vco_max = 1400000000,
1284 .freq_table = tegra_pll_p_freq_table,
1285 .lock_delay = 300,
1286 },
1279}; 1287};
1280 1288
1281static struct clk tegra_pll_p_out1 = { 1289static struct clk tegra_pll_p_out1 = {
@@ -1318,7 +1326,7 @@ static struct clk tegra_pll_p_out4 = {
1318 .max_rate = 432000000, 1326 .max_rate = 432000000,
1319}; 1327};
1320 1328
1321static struct clk_pll_table tegra_pll_a_table[] = { 1329static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
1322 { 28800000, 56448000, 49, 25, 1, 1}, 1330 { 28800000, 56448000, 49, 25, 1, 1},
1323 { 28800000, 73728000, 64, 25, 1, 1}, 1331 { 28800000, 73728000, 64, 25, 1, 1},
1324 { 28800000, 11289600, 49, 25, 1, 1}, 1332 { 28800000, 11289600, 49, 25, 1, 1},
@@ -1332,16 +1340,18 @@ static struct clk tegra_pll_a = {
1332 .flags = PLL_HAS_CPCON, 1340 .flags = PLL_HAS_CPCON,
1333 .ops = &tegra_pll_ops, 1341 .ops = &tegra_pll_ops,
1334 .reg = 0xb0, 1342 .reg = 0xb0,
1335 .input_min = 2000000,
1336 .input_max = 31000000,
1337 .parent = &tegra_pll_p_out1, 1343 .parent = &tegra_pll_p_out1,
1338 .cf_min = 1000000,
1339 .cf_max = 6000000,
1340 .vco_min = 20000000,
1341 .vco_max = 1400000000,
1342 .pll_table = tegra_pll_a_table,
1343 .max_rate = 56448000, 1344 .max_rate = 56448000,
1344 .pll_lock_delay = 300, 1345 .u.pll = {
1346 .input_min = 2000000,
1347 .input_max = 31000000,
1348 .cf_min = 1000000,
1349 .cf_max = 6000000,
1350 .vco_min = 20000000,
1351 .vco_max = 1400000000,
1352 .freq_table = tegra_pll_a_freq_table,
1353 .lock_delay = 300,
1354 },
1345}; 1355};
1346 1356
1347static struct clk tegra_pll_a_out0 = { 1357static struct clk tegra_pll_a_out0 = {
@@ -1354,7 +1364,7 @@ static struct clk tegra_pll_a_out0 = {
1354 .max_rate = 56448000, 1364 .max_rate = 56448000,
1355}; 1365};
1356 1366
1357static struct clk_pll_table tegra_pll_d_table[] = { 1367static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
1358 { 12000000, 216000000, 216, 12, 1, 4}, 1368 { 12000000, 216000000, 216, 12, 1, 4},
1359 { 13000000, 216000000, 216, 13, 1, 4}, 1369 { 13000000, 216000000, 216, 13, 1, 4},
1360 { 19200000, 216000000, 135, 12, 1, 3}, 1370 { 19200000, 216000000, 135, 12, 1, 3},
@@ -1378,16 +1388,18 @@ static struct clk tegra_pll_d = {
1378 .flags = PLL_HAS_CPCON | PLLD, 1388 .flags = PLL_HAS_CPCON | PLLD,
1379 .ops = &tegra_pll_ops, 1389 .ops = &tegra_pll_ops,
1380 .reg = 0xd0, 1390 .reg = 0xd0,
1381 .input_min = 2000000,
1382 .input_max = 40000000,
1383 .parent = &tegra_clk_m, 1391 .parent = &tegra_clk_m,
1384 .cf_min = 1000000,
1385 .cf_max = 6000000,
1386 .vco_min = 40000000,
1387 .vco_max = 1000000000,
1388 .pll_table = tegra_pll_d_table,
1389 .max_rate = 1000000000, 1392 .max_rate = 1000000000,
1390 .pll_lock_delay = 1000, 1393 .u.pll = {
1394 .input_min = 2000000,
1395 .input_max = 40000000,
1396 .cf_min = 1000000,
1397 .cf_max = 6000000,
1398 .vco_min = 40000000,
1399 .vco_max = 1000000000,
1400 .freq_table = tegra_pll_d_freq_table,
1401 .lock_delay = 1000,
1402 },
1391}; 1403};
1392 1404
1393static struct clk tegra_pll_d_out0 = { 1405static struct clk tegra_pll_d_out0 = {
@@ -1398,7 +1410,7 @@ static struct clk tegra_pll_d_out0 = {
1398 .max_rate = 500000000, 1410 .max_rate = 500000000,
1399}; 1411};
1400 1412
1401static struct clk_pll_table tegra_pll_u_table[] = { 1413static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
1402 { 12000000, 480000000, 960, 12, 2, 0}, 1414 { 12000000, 480000000, 960, 12, 2, 0},
1403 { 13000000, 480000000, 960, 13, 2, 0}, 1415 { 13000000, 480000000, 960, 13, 2, 0},
1404 { 19200000, 480000000, 200, 4, 2, 0}, 1416 { 19200000, 480000000, 200, 4, 2, 0},
@@ -1411,19 +1423,21 @@ static struct clk tegra_pll_u = {
1411 .flags = PLLU, 1423 .flags = PLLU,
1412 .ops = &tegra_pll_ops, 1424 .ops = &tegra_pll_ops,
1413 .reg = 0xc0, 1425 .reg = 0xc0,
1414 .input_min = 2000000,
1415 .input_max = 40000000,
1416 .parent = &tegra_clk_m, 1426 .parent = &tegra_clk_m,
1417 .cf_min = 1000000,
1418 .cf_max = 6000000,
1419 .vco_min = 480000000,
1420 .vco_max = 960000000,
1421 .pll_table = tegra_pll_u_table,
1422 .max_rate = 480000000, 1427 .max_rate = 480000000,
1423 .pll_lock_delay = 1000, 1428 .u.pll = {
1424}; 1429 .input_min = 2000000,
1425 1430 .input_max = 40000000,
1426static struct clk_pll_table tegra_pll_x_table[] = { 1431 .cf_min = 1000000,
1432 .cf_max = 6000000,
1433 .vco_min = 480000000,
1434 .vco_max = 960000000,
1435 .freq_table = tegra_pll_u_freq_table,
1436 .lock_delay = 1000,
1437 },
1438};
1439
1440static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
1427 /* 1 GHz */ 1441 /* 1 GHz */
1428 { 12000000, 1000000000, 1000, 12, 1, 12}, 1442 { 12000000, 1000000000, 1000, 12, 1, 12},
1429 { 13000000, 1000000000, 1000, 13, 1, 12}, 1443 { 13000000, 1000000000, 1000, 13, 1, 12},
@@ -1474,19 +1488,21 @@ static struct clk tegra_pll_x = {
1474 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG, 1488 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
1475 .ops = &tegra_pllx_ops, 1489 .ops = &tegra_pllx_ops,
1476 .reg = 0xe0, 1490 .reg = 0xe0,
1477 .input_min = 2000000,
1478 .input_max = 31000000,
1479 .parent = &tegra_clk_m, 1491 .parent = &tegra_clk_m,
1480 .cf_min = 1000000,
1481 .cf_max = 6000000,
1482 .vco_min = 20000000,
1483 .vco_max = 1200000000,
1484 .pll_table = tegra_pll_x_table,
1485 .max_rate = 1000000000, 1492 .max_rate = 1000000000,
1486 .pll_lock_delay = 300, 1493 .u.pll = {
1487}; 1494 .input_min = 2000000,
1488 1495 .input_max = 31000000,
1489static struct clk_pll_table tegra_pll_e_table[] = { 1496 .cf_min = 1000000,
1497 .cf_max = 6000000,
1498 .vco_min = 20000000,
1499 .vco_max = 1200000000,
1500 .freq_table = tegra_pll_x_freq_table,
1501 .lock_delay = 300,
1502 },
1503};
1504
1505static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
1490 { 12000000, 100000000, 200, 24, 1, 0 }, 1506 { 12000000, 100000000, 200, 24, 1, 0 },
1491 { 0, 0, 0, 0, 0, 0 }, 1507 { 0, 0, 0, 0, 0, 0 },
1492}; 1508};
@@ -1495,41 +1511,49 @@ static struct clk tegra_pll_e = {
1495 .name = "pll_e", 1511 .name = "pll_e",
1496 .flags = PLL_ALT_MISC_REG, 1512 .flags = PLL_ALT_MISC_REG,
1497 .ops = &tegra_plle_ops, 1513 .ops = &tegra_plle_ops,
1498 .input_min = 12000000,
1499 .input_max = 12000000,
1500 .max_rate = 100000000,
1501 .parent = &tegra_clk_m, 1514 .parent = &tegra_clk_m,
1502 .reg = 0xe8, 1515 .reg = 0xe8,
1503 .pll_table = tegra_pll_e_table, 1516 .max_rate = 100000000,
1517 .u.pll = {
1518 .input_min = 12000000,
1519 .input_max = 12000000,
1520 .freq_table = tegra_pll_e_freq_table,
1521 },
1504}; 1522};
1505 1523
1506static struct clk tegra_clk_d = { 1524static struct clk tegra_clk_d = {
1507 .name = "clk_d", 1525 .name = "clk_d",
1508 .flags = PERIPH_NO_RESET, 1526 .flags = PERIPH_NO_RESET,
1509 .ops = &tegra_clk_double_ops, 1527 .ops = &tegra_clk_double_ops,
1510 .clk_num = 90,
1511 .reg = 0x34, 1528 .reg = 0x34,
1512 .reg_shift = 12, 1529 .reg_shift = 12,
1513 .parent = &tegra_clk_m, 1530 .parent = &tegra_clk_m,
1514 .max_rate = 52000000, 1531 .max_rate = 52000000,
1532 .u.periph = {
1533 .clk_num = 90,
1534 },
1515}; 1535};
1516 1536
1517/* dap_mclk1, belongs to the cdev1 pingroup. */ 1537/* dap_mclk1, belongs to the cdev1 pingroup. */
1518static struct clk tegra_dev1_clk = { 1538static struct clk tegra_dev1_clk = {
1519 .name = "clk_dev1", 1539 .name = "clk_dev1",
1520 .ops = &tegra_cdev_clk_ops, 1540 .ops = &tegra_cdev_clk_ops,
1521 .clk_num = 94,
1522 .rate = 26000000, 1541 .rate = 26000000,
1523 .max_rate = 26000000, 1542 .max_rate = 26000000,
1543 .u.periph = {
1544 .clk_num = 94,
1545 },
1524}; 1546};
1525 1547
1526/* dap_mclk2, belongs to the cdev2 pingroup. */ 1548/* dap_mclk2, belongs to the cdev2 pingroup. */
1527static struct clk tegra_dev2_clk = { 1549static struct clk tegra_dev2_clk = {
1528 .name = "clk_dev2", 1550 .name = "clk_dev2",
1529 .ops = &tegra_cdev_clk_ops, 1551 .ops = &tegra_cdev_clk_ops,
1530 .clk_num = 93,
1531 .rate = 26000000, 1552 .rate = 26000000,
1532 .max_rate = 26000000, 1553 .max_rate = 26000000,
1554 .u.periph = {
1555 .clk_num = 93,
1556 },
1533}; 1557};
1534 1558
1535/* initialized before peripheral clocks */ 1559/* initialized before peripheral clocks */
@@ -1564,10 +1588,12 @@ static struct clk tegra_clk_audio_2x = {
1564 .flags = PERIPH_NO_RESET, 1588 .flags = PERIPH_NO_RESET,
1565 .max_rate = 48000000, 1589 .max_rate = 48000000,
1566 .ops = &tegra_clk_double_ops, 1590 .ops = &tegra_clk_double_ops,
1567 .clk_num = 89,
1568 .reg = 0x34, 1591 .reg = 0x34,
1569 .reg_shift = 8, 1592 .reg_shift = 8,
1570 .parent = &tegra_clk_audio, 1593 .parent = &tegra_clk_audio,
1594 .u.periph = {
1595 .clk_num = 89,
1596 },
1571}; 1597};
1572 1598
1573struct clk_lookup tegra_audio_clk_lookups[] = { 1599struct clk_lookup tegra_audio_clk_lookups[] = {
@@ -1645,10 +1671,12 @@ static struct clk tegra_clk_sclk = {
1645static struct clk tegra_clk_virtual_cpu = { 1671static struct clk tegra_clk_virtual_cpu = {
1646 .name = "cpu", 1672 .name = "cpu",
1647 .parent = &tegra_clk_cclk, 1673 .parent = &tegra_clk_cclk,
1648 .main = &tegra_pll_x,
1649 .backup = &tegra_pll_p,
1650 .ops = &tegra_cpu_ops, 1674 .ops = &tegra_cpu_ops,
1651 .max_rate = 1000000000, 1675 .max_rate = 1000000000,
1676 .u.cpu = {
1677 .main = &tegra_pll_x,
1678 .backup = &tegra_pll_p,
1679 },
1652}; 1680};
1653 1681
1654static struct clk tegra_clk_hclk = { 1682static struct clk tegra_clk_hclk = {
@@ -1768,11 +1796,13 @@ static struct clk_mux_sel mux_pclk[] = {
1768 .con_id = _con, \ 1796 .con_id = _con, \
1769 }, \ 1797 }, \
1770 .ops = &tegra_periph_clk_ops, \ 1798 .ops = &tegra_periph_clk_ops, \
1771 .clk_num = _clk_num, \
1772 .reg = _reg, \ 1799 .reg = _reg, \
1773 .inputs = _inputs, \ 1800 .inputs = _inputs, \
1774 .flags = _flags, \ 1801 .flags = _flags, \
1775 .max_rate = _max, \ 1802 .max_rate = _max, \
1803 .u.periph = { \
1804 .clk_num = _clk_num, \
1805 }, \
1776 } 1806 }
1777 1807
1778struct clk tegra_list_clks[] = { 1808struct clk tegra_list_clks[] = {
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 06:33:35 -0500