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authorDmitry Torokhov <dmitry.torokhov@gmail.com>2012-09-05 01:57:19 -0400
committerDmitry Torokhov <dmitry.torokhov@gmail.com>2012-09-05 01:57:19 -0400
commite6c340171f0daaccc95b90abbeed2b837157ee11 (patch)
tree843d4035be59bd791321910e52157ce527b3b4b3 /arch/arm/mach-tegra
parenta85442ade272121927a56e02f7dfde1127482df2 (diff)
parent4cbe5a555fa58a79b6ecbb6c531b8bab0650778d (diff)
Merge tag 'v3.6-rc4' into next
Linux 3.6-rc4 # gpg: Signature made Sat 01 Sep 2012 10:40:33 AM PDT using RSA key ID 00411886 # gpg: Good signature from "Linus Torvalds <torvalds@linux-foundation.org>"
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r--arch/arm/mach-tegra/Kconfig39
-rw-r--r--arch/arm/mach-tegra/Makefile18
-rw-r--r--arch/arm/mach-tegra/Makefile.boot13
-rw-r--r--arch/arm/mach-tegra/apbio.c194
-rw-r--r--arch/arm/mach-tegra/apbio.h19
-rw-r--r--arch/arm/mach-tegra/board-dt-tegra20.c75
-rw-r--r--arch/arm/mach-tegra/board-dt-tegra30.c11
-rw-r--r--arch/arm/mach-tegra/board-harmony-pcie.c15
-rw-r--r--arch/arm/mach-tegra/board-harmony-power.c60
-rw-r--r--arch/arm/mach-tegra/board-paz00.c7
-rw-r--r--arch/arm/mach-tegra/board-seaboard-pinmux.c197
-rw-r--r--arch/arm/mach-tegra/board-seaboard.c306
-rw-r--r--arch/arm/mach-tegra/board-seaboard.h47
-rw-r--r--arch/arm/mach-tegra/board.h9
-rw-r--r--arch/arm/mach-tegra/common.c3
-rw-r--r--arch/arm/mach-tegra/cpu-tegra.c6
-rw-r--r--arch/arm/mach-tegra/cpuidle.c6
-rw-r--r--arch/arm/mach-tegra/dma.c4
-rw-r--r--arch/arm/mach-tegra/pcie.c6
-rw-r--r--arch/arm/mach-tegra/powergate.c4
-rw-r--r--arch/arm/mach-tegra/sleep.S29
-rw-r--r--arch/arm/mach-tegra/tegra2_clocks.c58
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.c28
-rw-r--r--arch/arm/mach-tegra/timer.c4
-rw-r--r--arch/arm/mach-tegra/usb_phy.c16
25 files changed, 422 insertions, 752 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 6a113a9bb87a..9077aaa398d9 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -63,40 +63,15 @@ comment "Tegra board type"
63config MACH_HARMONY 63config MACH_HARMONY
64 bool "Harmony board" 64 bool "Harmony board"
65 depends on ARCH_TEGRA_2x_SOC 65 depends on ARCH_TEGRA_2x_SOC
66 select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
67 help 66 help
68 Support for nVidia Harmony development platform 67 Support for nVidia Harmony development platform
69 68
70config MACH_KAEN
71 bool "Kaen board"
72 depends on ARCH_TEGRA_2x_SOC
73 select MACH_SEABOARD
74 select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
75 help
76 Support for the Kaen version of Seaboard
77
78config MACH_PAZ00 69config MACH_PAZ00
79 bool "Paz00 board" 70 bool "Paz00 board"
80 depends on ARCH_TEGRA_2x_SOC 71 depends on ARCH_TEGRA_2x_SOC
81 help 72 help
82 Support for the Toshiba AC100/Dynabook AZ netbook 73 Support for the Toshiba AC100/Dynabook AZ netbook
83 74
84config MACH_SEABOARD
85 bool "Seaboard board"
86 depends on ARCH_TEGRA_2x_SOC
87 select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
88 help
89 Support for nVidia Seaboard development platform. It will
90 also be included for some of the derivative boards that
91 have large similarities with the seaboard design.
92
93config MACH_TEGRA_DT
94 bool "Generic Tegra20 board (FDT support)"
95 depends on ARCH_TEGRA_2x_SOC
96 select USE_OF
97 help
98 Support for generic NVIDIA Tegra20 boards using Flattened Device Tree
99
100config MACH_TRIMSLICE 75config MACH_TRIMSLICE
101 bool "TrimSlice board" 76 bool "TrimSlice board"
102 depends on ARCH_TEGRA_2x_SOC 77 depends on ARCH_TEGRA_2x_SOC
@@ -104,20 +79,6 @@ config MACH_TRIMSLICE
104 help 79 help
105 Support for CompuLab TrimSlice platform 80 Support for CompuLab TrimSlice platform
106 81
107config MACH_WARIO
108 bool "Wario board"
109 depends on ARCH_TEGRA_2x_SOC
110 select MACH_SEABOARD
111 help
112 Support for the Wario version of Seaboard
113
114config MACH_VENTANA
115 bool "Ventana board"
116 depends on ARCH_TEGRA_2x_SOC
117 select MACH_TEGRA_DT
118 help
119 Support for the nVidia Ventana development platform
120
121choice 82choice
122 prompt "Default low-level debug console UART" 83 prompt "Default low-level debug console UART"
123 default TEGRA_DEBUG_UART_NONE 84 default TEGRA_DEBUG_UART_NONE
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 2eb4445ddb14..c3d7303b9ac8 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -8,21 +8,24 @@ obj-y += timer.o
8obj-y += fuse.o 8obj-y += fuse.o
9obj-y += pmc.o 9obj-y += pmc.o
10obj-y += flowctrl.o 10obj-y += flowctrl.o
11obj-y += powergate.o
12obj-y += apbio.o
11obj-$(CONFIG_CPU_IDLE) += cpuidle.o 13obj-$(CONFIG_CPU_IDLE) += cpuidle.o
12obj-$(CONFIG_CPU_IDLE) += sleep.o 14obj-$(CONFIG_CPU_IDLE) += sleep.o
13obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o
14obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o 15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o 16obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
16obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o
17obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o 17obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
18obj-$(CONFIG_SMP) += platsmp.o headsmp.o 18obj-$(CONFIG_SMP) += platsmp.o headsmp.o
19obj-$(CONFIG_SMP) += reset.o 19obj-$(CONFIG_SMP) += reset.o
20obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 20obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
21obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o apbio.o 21obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o
22obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o 22obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o
23obj-$(CONFIG_TEGRA_PCI) += pcie.o 23obj-$(CONFIG_TEGRA_PCI) += pcie.o
24obj-$(CONFIG_USB_SUPPORT) += usb_phy.o 24obj-$(CONFIG_USB_SUPPORT) += usb_phy.o
25 25
26obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-dt-tegra20.o
27obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o
28
26obj-$(CONFIG_MACH_HARMONY) += board-harmony.o 29obj-$(CONFIG_MACH_HARMONY) += board-harmony.o
27obj-$(CONFIG_MACH_HARMONY) += board-harmony-pinmux.o 30obj-$(CONFIG_MACH_HARMONY) += board-harmony-pinmux.o
28obj-$(CONFIG_MACH_HARMONY) += board-harmony-pcie.o 31obj-$(CONFIG_MACH_HARMONY) += board-harmony-pcie.o
@@ -31,14 +34,5 @@ obj-$(CONFIG_MACH_HARMONY) += board-harmony-power.o
31obj-$(CONFIG_MACH_PAZ00) += board-paz00.o 34obj-$(CONFIG_MACH_PAZ00) += board-paz00.o
32obj-$(CONFIG_MACH_PAZ00) += board-paz00-pinmux.o 35obj-$(CONFIG_MACH_PAZ00) += board-paz00-pinmux.o
33 36
34obj-$(CONFIG_MACH_SEABOARD) += board-seaboard.o
35obj-$(CONFIG_MACH_SEABOARD) += board-seaboard-pinmux.o
36
37obj-$(CONFIG_MACH_TEGRA_DT) += board-dt-tegra20.o
38obj-$(CONFIG_MACH_TEGRA_DT) += board-harmony-pinmux.o
39obj-$(CONFIG_MACH_TEGRA_DT) += board-seaboard-pinmux.o
40obj-$(CONFIG_MACH_TEGRA_DT) += board-paz00-pinmux.o
41obj-$(CONFIG_MACH_TEGRA_DT) += board-trimslice-pinmux.o
42
43obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice.o 37obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice.o
44obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice-pinmux.o 38obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice-pinmux.o
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
index 9a82094092d7..7a1bb62ddcf0 100644
--- a/arch/arm/mach-tegra/Makefile.boot
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -2,9 +2,10 @@ zreladdr-$(CONFIG_ARCH_TEGRA_2x_SOC) += 0x00008000
2params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100 2params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100
3initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000 3initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000
4 4
5dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb 5dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-harmony.dtb
6dtb-$(CONFIG_MACH_PAZ00) += tegra-paz00.dtb 6dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-paz00.dtb
7dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb 7dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-seaboard.dtb
8dtb-$(CONFIG_MACH_TRIMSLICE) += tegra-trimslice.dtb 8dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-trimslice.dtb
9dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb 9dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-ventana.dtb
10dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra-cardhu.dtb 10dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-whistler.dtb
11dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu.dtb
diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c
index e75451e517bd..dc0fe389be56 100644
--- a/arch/arm/mach-tegra/apbio.c
+++ b/arch/arm/mach-tegra/apbio.c
@@ -15,6 +15,9 @@
15 15
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/io.h> 17#include <linux/io.h>
18#include <mach/iomap.h>
19#include <linux/of.h>
20#include <linux/dmaengine.h>
18#include <linux/dma-mapping.h> 21#include <linux/dma-mapping.h>
19#include <linux/spinlock.h> 22#include <linux/spinlock.h>
20#include <linux/completion.h> 23#include <linux/completion.h>
@@ -22,17 +25,21 @@
22#include <linux/mutex.h> 25#include <linux/mutex.h>
23 26
24#include <mach/dma.h> 27#include <mach/dma.h>
25#include <mach/iomap.h>
26 28
27#include "apbio.h" 29#include "apbio.h"
28 30
31#if defined(CONFIG_TEGRA_SYSTEM_DMA) || defined(CONFIG_TEGRA20_APB_DMA)
29static DEFINE_MUTEX(tegra_apb_dma_lock); 32static DEFINE_MUTEX(tegra_apb_dma_lock);
30
31static struct tegra_dma_channel *tegra_apb_dma;
32static u32 *tegra_apb_bb; 33static u32 *tegra_apb_bb;
33static dma_addr_t tegra_apb_bb_phys; 34static dma_addr_t tegra_apb_bb_phys;
34static DECLARE_COMPLETION(tegra_apb_wait); 35static DECLARE_COMPLETION(tegra_apb_wait);
35 36
37static u32 tegra_apb_readl_direct(unsigned long offset);
38static void tegra_apb_writel_direct(u32 value, unsigned long offset);
39
40#if defined(CONFIG_TEGRA_SYSTEM_DMA)
41static struct tegra_dma_channel *tegra_apb_dma;
42
36bool tegra_apb_init(void) 43bool tegra_apb_init(void)
37{ 44{
38 struct tegra_dma_channel *ch; 45 struct tegra_dma_channel *ch;
@@ -72,13 +79,13 @@ static void apb_dma_complete(struct tegra_dma_req *req)
72 complete(&tegra_apb_wait); 79 complete(&tegra_apb_wait);
73} 80}
74 81
75u32 tegra_apb_readl(unsigned long offset) 82static u32 tegra_apb_readl_using_dma(unsigned long offset)
76{ 83{
77 struct tegra_dma_req req; 84 struct tegra_dma_req req;
78 int ret; 85 int ret;
79 86
80 if (!tegra_apb_dma && !tegra_apb_init()) 87 if (!tegra_apb_dma && !tegra_apb_init())
81 return readl(IO_TO_VIRT(offset)); 88 return tegra_apb_readl_direct(offset);
82 89
83 mutex_lock(&tegra_apb_dma_lock); 90 mutex_lock(&tegra_apb_dma_lock);
84 req.complete = apb_dma_complete; 91 req.complete = apb_dma_complete;
@@ -108,13 +115,13 @@ u32 tegra_apb_readl(unsigned long offset)
108 return *((u32 *)tegra_apb_bb); 115 return *((u32 *)tegra_apb_bb);
109} 116}
110 117
111void tegra_apb_writel(u32 value, unsigned long offset) 118static void tegra_apb_writel_using_dma(u32 value, unsigned long offset)
112{ 119{
113 struct tegra_dma_req req; 120 struct tegra_dma_req req;
114 int ret; 121 int ret;
115 122
116 if (!tegra_apb_dma && !tegra_apb_init()) { 123 if (!tegra_apb_dma && !tegra_apb_init()) {
117 writel(value, IO_TO_VIRT(offset)); 124 tegra_apb_writel_direct(value, offset);
118 return; 125 return;
119 } 126 }
120 127
@@ -143,3 +150,176 @@ void tegra_apb_writel(u32 value, unsigned long offset)
143 150
144 mutex_unlock(&tegra_apb_dma_lock); 151 mutex_unlock(&tegra_apb_dma_lock);
145} 152}
153
154#else
155static struct dma_chan *tegra_apb_dma_chan;
156static struct dma_slave_config dma_sconfig;
157
158bool tegra_apb_dma_init(void)
159{
160 dma_cap_mask_t mask;
161
162 mutex_lock(&tegra_apb_dma_lock);
163
164 /* Check to see if we raced to setup */
165 if (tegra_apb_dma_chan)
166 goto skip_init;
167
168 dma_cap_zero(mask);
169 dma_cap_set(DMA_SLAVE, mask);
170 tegra_apb_dma_chan = dma_request_channel(mask, NULL, NULL);
171 if (!tegra_apb_dma_chan) {
172 /*
173 * This is common until the device is probed, so don't
174 * shout about it.
175 */
176 pr_debug("%s: can not allocate dma channel\n", __func__);
177 goto err_dma_alloc;
178 }
179
180 tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32),
181 &tegra_apb_bb_phys, GFP_KERNEL);
182 if (!tegra_apb_bb) {
183 pr_err("%s: can not allocate bounce buffer\n", __func__);
184 goto err_buff_alloc;
185 }
186
187 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
188 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
189 dma_sconfig.slave_id = TEGRA_DMA_REQ_SEL_CNTR;
190 dma_sconfig.src_maxburst = 1;
191 dma_sconfig.dst_maxburst = 1;
192
193skip_init:
194 mutex_unlock(&tegra_apb_dma_lock);
195 return true;
196
197err_buff_alloc:
198 dma_release_channel(tegra_apb_dma_chan);
199 tegra_apb_dma_chan = NULL;
200
201err_dma_alloc:
202 mutex_unlock(&tegra_apb_dma_lock);
203 return false;
204}
205
206static void apb_dma_complete(void *args)
207{
208 complete(&tegra_apb_wait);
209}
210
211static int do_dma_transfer(unsigned long apb_add,
212 enum dma_transfer_direction dir)
213{
214 struct dma_async_tx_descriptor *dma_desc;
215 int ret;
216
217 if (dir == DMA_DEV_TO_MEM)
218 dma_sconfig.src_addr = apb_add;
219 else
220 dma_sconfig.dst_addr = apb_add;
221
222 ret = dmaengine_slave_config(tegra_apb_dma_chan, &dma_sconfig);
223 if (ret)
224 return ret;
225
226 dma_desc = dmaengine_prep_slave_single(tegra_apb_dma_chan,
227 tegra_apb_bb_phys, sizeof(u32), dir,
228 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
229 if (!dma_desc)
230 return -EINVAL;
231
232 dma_desc->callback = apb_dma_complete;
233 dma_desc->callback_param = NULL;
234
235 INIT_COMPLETION(tegra_apb_wait);
236
237 dmaengine_submit(dma_desc);
238 dma_async_issue_pending(tegra_apb_dma_chan);
239 ret = wait_for_completion_timeout(&tegra_apb_wait,
240 msecs_to_jiffies(50));
241
242 if (WARN(ret == 0, "apb read dma timed out")) {
243 dmaengine_terminate_all(tegra_apb_dma_chan);
244 return -EFAULT;
245 }
246 return 0;
247}
248
249static u32 tegra_apb_readl_using_dma(unsigned long offset)
250{
251 int ret;
252
253 if (!tegra_apb_dma_chan && !tegra_apb_dma_init())
254 return tegra_apb_readl_direct(offset);
255
256 mutex_lock(&tegra_apb_dma_lock);
257 ret = do_dma_transfer(offset, DMA_DEV_TO_MEM);
258 if (ret < 0) {
259 pr_err("error in reading offset 0x%08lx using dma\n", offset);
260 *(u32 *)tegra_apb_bb = 0;
261 }
262 mutex_unlock(&tegra_apb_dma_lock);
263 return *((u32 *)tegra_apb_bb);
264}
265
266static void tegra_apb_writel_using_dma(u32 value, unsigned long offset)
267{
268 int ret;
269
270 if (!tegra_apb_dma_chan && !tegra_apb_dma_init()) {
271 tegra_apb_writel_direct(value, offset);
272 return;
273 }
274
275 mutex_lock(&tegra_apb_dma_lock);
276 *((u32 *)tegra_apb_bb) = value;
277 ret = do_dma_transfer(offset, DMA_MEM_TO_DEV);
278 if (ret < 0)
279 pr_err("error in writing offset 0x%08lx using dma\n", offset);
280 mutex_unlock(&tegra_apb_dma_lock);
281}
282#endif
283#else
284#define tegra_apb_readl_using_dma tegra_apb_readl_direct
285#define tegra_apb_writel_using_dma tegra_apb_writel_direct
286#endif
287
288typedef u32 (*apbio_read_fptr)(unsigned long offset);
289typedef void (*apbio_write_fptr)(u32 value, unsigned long offset);
290
291static apbio_read_fptr apbio_read;
292static apbio_write_fptr apbio_write;
293
294static u32 tegra_apb_readl_direct(unsigned long offset)
295{
296 return readl(IO_TO_VIRT(offset));
297}
298
299static void tegra_apb_writel_direct(u32 value, unsigned long offset)
300{
301 writel(value, IO_TO_VIRT(offset));
302}
303
304void tegra_apb_io_init(void)
305{
306 /* Need to use dma only when it is Tegra20 based platform */
307 if (of_machine_is_compatible("nvidia,tegra20") ||
308 !of_have_populated_dt()) {
309 apbio_read = tegra_apb_readl_using_dma;
310 apbio_write = tegra_apb_writel_using_dma;
311 } else {
312 apbio_read = tegra_apb_readl_direct;
313 apbio_write = tegra_apb_writel_direct;
314 }
315}
316
317u32 tegra_apb_readl(unsigned long offset)
318{
319 return apbio_read(offset);
320}
321
322void tegra_apb_writel(u32 value, unsigned long offset)
323{
324 apbio_write(value, offset);
325}
diff --git a/arch/arm/mach-tegra/apbio.h b/arch/arm/mach-tegra/apbio.h
index 8b49e8c89a64..f05d71c303c7 100644
--- a/arch/arm/mach-tegra/apbio.h
+++ b/arch/arm/mach-tegra/apbio.h
@@ -16,24 +16,7 @@
16#ifndef __MACH_TEGRA_APBIO_H 16#ifndef __MACH_TEGRA_APBIO_H
17#define __MACH_TEGRA_APBIO_H 17#define __MACH_TEGRA_APBIO_H
18 18
19#ifdef CONFIG_TEGRA_SYSTEM_DMA 19void tegra_apb_io_init(void);
20
21u32 tegra_apb_readl(unsigned long offset); 20u32 tegra_apb_readl(unsigned long offset);
22void tegra_apb_writel(u32 value, unsigned long offset); 21void tegra_apb_writel(u32 value, unsigned long offset);
23
24#else
25#include <asm/io.h>
26#include <mach/io.h>
27
28static inline u32 tegra_apb_readl(unsigned long offset)
29{
30 return readl(IO_TO_VIRT(offset));
31}
32
33static inline void tegra_apb_writel(u32 value, unsigned long offset)
34{
35 writel(value, IO_TO_VIRT(offset));
36}
37#endif
38
39#endif 22#endif
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index eb7249db50a5..c0999633a9ab 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -64,6 +64,8 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
64 &tegra_ehci2_pdata), 64 &tegra_ehci2_pdata),
65 OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2", 65 OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2",
66 &tegra_ehci3_pdata), 66 &tegra_ehci3_pdata),
67 OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL),
68 OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
67 {} 69 {}
68}; 70};
69 71
@@ -81,11 +83,6 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
81 { NULL, NULL, 0, 0}, 83 { NULL, NULL, 0, 0},
82}; 84};
83 85
84static struct of_device_id tegra_dt_match_table[] __initdata = {
85 { .compatible = "simple-bus", },
86 {}
87};
88
89static void __init tegra_dt_init(void) 86static void __init tegra_dt_init(void)
90{ 87{
91 tegra_clk_init_from_table(tegra_dt_clk_init_table); 88 tegra_clk_init_from_table(tegra_dt_clk_init_table);
@@ -94,10 +91,74 @@ static void __init tegra_dt_init(void)
94 * Finished with the static registrations now; fill in the missing 91 * Finished with the static registrations now; fill in the missing
95 * devices 92 * devices
96 */ 93 */
97 of_platform_populate(NULL, tegra_dt_match_table, 94 of_platform_populate(NULL, of_default_bus_match_table,
98 tegra20_auxdata_lookup, NULL); 95 tegra20_auxdata_lookup, NULL);
99} 96}
100 97
98#ifdef CONFIG_MACH_TRIMSLICE
99static void __init trimslice_init(void)
100{
101 int ret;
102
103 ret = tegra_pcie_init(true, true);
104 if (ret)
105 pr_err("tegra_pci_init() failed: %d\n", ret);
106}
107#endif
108
109#ifdef CONFIG_MACH_HARMONY
110static void __init harmony_init(void)
111{
112 int ret;
113
114 ret = harmony_regulator_init();
115 if (ret) {
116 pr_err("harmony_regulator_init() failed: %d\n", ret);
117 return;
118 }
119
120 ret = harmony_pcie_init();
121 if (ret)
122 pr_err("harmony_pcie_init() failed: %d\n", ret);
123}
124#endif
125
126#ifdef CONFIG_MACH_PAZ00
127static void __init paz00_init(void)
128{
129 tegra_paz00_wifikill_init();
130}
131#endif
132
133static struct {
134 char *machine;
135 void (*init)(void);
136} board_init_funcs[] = {
137#ifdef CONFIG_MACH_TRIMSLICE
138 { "compulab,trimslice", trimslice_init },
139#endif
140#ifdef CONFIG_MACH_HARMONY
141 { "nvidia,harmony", harmony_init },
142#endif
143#ifdef CONFIG_MACH_PAZ00
144 { "compal,paz00", paz00_init },
145#endif
146};
147
148static void __init tegra_dt_init_late(void)
149{
150 int i;
151
152 tegra_init_late();
153
154 for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) {
155 if (of_machine_is_compatible(board_init_funcs[i].machine)) {
156 board_init_funcs[i].init();
157 break;
158 }
159 }
160}
161
101static const char *tegra20_dt_board_compat[] = { 162static const char *tegra20_dt_board_compat[] = {
102 "nvidia,tegra20", 163 "nvidia,tegra20",
103 NULL 164 NULL
@@ -110,7 +171,7 @@ DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
110 .handle_irq = gic_handle_irq, 171 .handle_irq = gic_handle_irq,
111 .timer = &tegra_timer, 172 .timer = &tegra_timer,
112 .init_machine = tegra_dt_init, 173 .init_machine = tegra_dt_init,
113 .init_late = tegra_init_late, 174 .init_late = tegra_dt_init_late,
114 .restart = tegra_assert_system_reset, 175 .restart = tegra_assert_system_reset,
115 .dt_compat = tegra20_dt_board_compat, 176 .dt_compat = tegra20_dt_board_compat,
116MACHINE_END 177MACHINE_END
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index 4f76fa7a5da3..53bf60f11580 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -33,14 +33,11 @@
33#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
34#include <asm/hardware/gic.h> 34#include <asm/hardware/gic.h>
35 35
36#include <mach/iomap.h>
37
36#include "board.h" 38#include "board.h"
37#include "clock.h" 39#include "clock.h"
38 40
39static struct of_device_id tegra_dt_match_table[] __initdata = {
40 { .compatible = "simple-bus", },
41 {}
42};
43
44struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = { 41struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
45 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL), 42 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL),
46 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000200, "sdhci-tegra.1", NULL), 43 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000200, "sdhci-tegra.1", NULL),
@@ -52,6 +49,8 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
52 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL), 49 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL),
53 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL), 50 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL),
54 OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL), 51 OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL),
52 OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL),
53 OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
55 {} 54 {}
56}; 55};
57 56
@@ -74,7 +73,7 @@ static void __init tegra30_dt_init(void)
74{ 73{
75 tegra_clk_init_from_table(tegra_dt_clk_init_table); 74 tegra_clk_init_from_table(tegra_dt_clk_init_table);
76 75
77 of_platform_populate(NULL, tegra_dt_match_table, 76 of_platform_populate(NULL, of_default_bus_match_table,
78 tegra30_auxdata_lookup, NULL); 77 tegra30_auxdata_lookup, NULL);
79} 78}
80 79
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
index 33c4fedab840..e8c3fda9bec2 100644
--- a/arch/arm/mach-tegra/board-harmony-pcie.c
+++ b/arch/arm/mach-tegra/board-harmony-pcie.c
@@ -27,14 +27,11 @@
27 27
28#ifdef CONFIG_TEGRA_PCI 28#ifdef CONFIG_TEGRA_PCI
29 29
30static int __init harmony_pcie_init(void) 30int __init harmony_pcie_init(void)
31{ 31{
32 struct regulator *regulator = NULL; 32 struct regulator *regulator = NULL;
33 int err; 33 int err;
34 34
35 if (!machine_is_harmony())
36 return 0;
37
38 err = gpio_request(TEGRA_GPIO_EN_VDD_1V05_GPIO, "EN_VDD_1V05"); 35 err = gpio_request(TEGRA_GPIO_EN_VDD_1V05_GPIO, "EN_VDD_1V05");
39 if (err) 36 if (err)
40 return err; 37 return err;
@@ -62,7 +59,15 @@ err_reg:
62 return err; 59 return err;
63} 60}
64 61
62static int __init harmony_pcie_initcall(void)
63{
64 if (!machine_is_harmony())
65 return 0;
66
67 return harmony_pcie_init();
68}
69
65/* PCI should be initialized after I2C, mfd and regulators */ 70/* PCI should be initialized after I2C, mfd and regulators */
66subsys_initcall_sync(harmony_pcie_init); 71subsys_initcall_sync(harmony_pcie_initcall);
67 72
68#endif 73#endif
diff --git a/arch/arm/mach-tegra/board-harmony-power.c b/arch/arm/mach-tegra/board-harmony-power.c
index 82f32300796c..b7344beec102 100644
--- a/arch/arm/mach-tegra/board-harmony-power.c
+++ b/arch/arm/mach-tegra/board-harmony-power.c
@@ -19,7 +19,12 @@
19#include <linux/platform_device.h> 19#include <linux/platform_device.h>
20#include <linux/gpio.h> 20#include <linux/gpio.h>
21#include <linux/regulator/machine.h> 21#include <linux/regulator/machine.h>
22#include <linux/regulator/fixed.h>
22#include <linux/mfd/tps6586x.h> 23#include <linux/mfd/tps6586x.h>
24#include <linux/of.h>
25#include <linux/of_i2c.h>
26
27#include <asm/mach-types.h>
23 28
24#include <mach/irqs.h> 29#include <mach/irqs.h>
25 30
@@ -30,7 +35,9 @@ static struct regulator_consumer_supply tps658621_ldo0_supply[] = {
30}; 35};
31 36
32static struct regulator_init_data ldo0_data = { 37static struct regulator_init_data ldo0_data = {
38 .supply_regulator = "vdd_sm2",
33 .constraints = { 39 .constraints = {
40 .name = "vdd_ldo0",
34 .min_uV = 3300 * 1000, 41 .min_uV = 3300 * 1000,
35 .max_uV = 3300 * 1000, 42 .max_uV = 3300 * 1000,
36 .valid_modes_mask = (REGULATOR_MODE_NORMAL | 43 .valid_modes_mask = (REGULATOR_MODE_NORMAL |
@@ -44,9 +51,11 @@ static struct regulator_init_data ldo0_data = {
44 .consumer_supplies = tps658621_ldo0_supply, 51 .consumer_supplies = tps658621_ldo0_supply,
45}; 52};
46 53
47#define HARMONY_REGULATOR_INIT(_id, _minmv, _maxmv) \ 54#define HARMONY_REGULATOR_INIT(_id, _name, _supply, _minmv, _maxmv, _on)\
48 static struct regulator_init_data _id##_data = { \ 55 static struct regulator_init_data _id##_data = { \
56 .supply_regulator = _supply, \
49 .constraints = { \ 57 .constraints = { \
58 .name = _name, \
50 .min_uV = (_minmv)*1000, \ 59 .min_uV = (_minmv)*1000, \
51 .max_uV = (_maxmv)*1000, \ 60 .max_uV = (_maxmv)*1000, \
52 .valid_modes_mask = (REGULATOR_MODE_NORMAL | \ 61 .valid_modes_mask = (REGULATOR_MODE_NORMAL | \
@@ -54,21 +63,22 @@ static struct regulator_init_data ldo0_data = {
54 .valid_ops_mask = (REGULATOR_CHANGE_MODE | \ 63 .valid_ops_mask = (REGULATOR_CHANGE_MODE | \
55 REGULATOR_CHANGE_STATUS | \ 64 REGULATOR_CHANGE_STATUS | \
56 REGULATOR_CHANGE_VOLTAGE), \ 65 REGULATOR_CHANGE_VOLTAGE), \
66 .always_on = _on, \
57 }, \ 67 }, \
58 } 68 }
59 69
60HARMONY_REGULATOR_INIT(sm0, 725, 1500); 70HARMONY_REGULATOR_INIT(sm0, "vdd_sm0", "vdd_sys", 725, 1500, 1);
61HARMONY_REGULATOR_INIT(sm1, 725, 1500); 71HARMONY_REGULATOR_INIT(sm1, "vdd_sm1", "vdd_sys", 725, 1500, 1);
62HARMONY_REGULATOR_INIT(sm2, 3000, 4550); 72HARMONY_REGULATOR_INIT(sm2, "vdd_sm2", "vdd_sys", 3000, 4550, 1);
63HARMONY_REGULATOR_INIT(ldo1, 725, 1500); 73HARMONY_REGULATOR_INIT(ldo1, "vdd_ldo1", "vdd_sm2", 725, 1500, 1);
64HARMONY_REGULATOR_INIT(ldo2, 725, 1500); 74HARMONY_REGULATOR_INIT(ldo2, "vdd_ldo2", "vdd_sm2", 725, 1500, 0);
65HARMONY_REGULATOR_INIT(ldo3, 1250, 3300); 75HARMONY_REGULATOR_INIT(ldo3, "vdd_ldo3", "vdd_sm2", 1250, 3300, 1);
66HARMONY_REGULATOR_INIT(ldo4, 1700, 2475); 76HARMONY_REGULATOR_INIT(ldo4, "vdd_ldo4", "vdd_sm2", 1700, 2475, 1);
67HARMONY_REGULATOR_INIT(ldo5, 1250, 3300); 77HARMONY_REGULATOR_INIT(ldo5, "vdd_ldo5", NULL, 1250, 3300, 1);
68HARMONY_REGULATOR_INIT(ldo6, 1250, 3300); 78HARMONY_REGULATOR_INIT(ldo6, "vdd_ldo6", "vdd_sm2", 1250, 3300, 0);
69HARMONY_REGULATOR_INIT(ldo7, 1250, 3300); 79HARMONY_REGULATOR_INIT(ldo7, "vdd_ldo7", "vdd_sm2", 1250, 3300, 0);
70HARMONY_REGULATOR_INIT(ldo8, 1250, 3300); 80HARMONY_REGULATOR_INIT(ldo8, "vdd_ldo8", "vdd_sm2", 1250, 3300, 0);
71HARMONY_REGULATOR_INIT(ldo9, 1250, 3300); 81HARMONY_REGULATOR_INIT(ldo9, "vdd_ldo9", "vdd_sm2", 1250, 3300, 1);
72 82
73#define TPS_REG(_id, _data) \ 83#define TPS_REG(_id, _data) \
74 { \ 84 { \
@@ -110,7 +120,29 @@ static struct i2c_board_info __initdata harmony_regulators[] = {
110 120
111int __init harmony_regulator_init(void) 121int __init harmony_regulator_init(void)
112{ 122{
113 i2c_register_board_info(3, harmony_regulators, 1); 123 regulator_register_always_on(0, "vdd_sys",
124 NULL, 0, 5000000);
125
126 if (machine_is_harmony()) {
127 i2c_register_board_info(3, harmony_regulators, 1);
128 } else { /* Harmony, booted using device tree */
129 struct device_node *np;
130 struct i2c_adapter *adapter;
131
132 np = of_find_node_by_path("/i2c@7000d000");
133 if (np == NULL) {
134 pr_err("Could not find device_node for DVC I2C\n");
135 return -ENODEV;
136 }
137
138 adapter = of_find_i2c_adapter_by_node(np);
139 if (!adapter) {
140 pr_err("Could not find i2c_adapter for DVC I2C\n");
141 return -ENODEV;
142 }
143
144 i2c_new_device(adapter, harmony_regulators);
145 }
114 146
115 return 0; 147 return 0;
116} 148}
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index bbc1907e98a6..4b64af5cab27 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -148,7 +148,6 @@ static struct platform_device *paz00_devices[] __initdata = {
148 &debug_uart, 148 &debug_uart,
149 &tegra_sdhci_device4, 149 &tegra_sdhci_device4,
150 &tegra_sdhci_device1, 150 &tegra_sdhci_device1,
151 &wifi_rfkill_device,
152 &leds_gpio, 151 &leds_gpio,
153 &gpio_keys_device, 152 &gpio_keys_device,
154}; 153};
@@ -201,6 +200,11 @@ static struct tegra_sdhci_platform_data sdhci_pdata4 = {
201 .is_8bit = 1, 200 .is_8bit = 1,
202}; 201};
203 202
203void __init tegra_paz00_wifikill_init(void)
204{
205 platform_device_register(&wifi_rfkill_device);
206}
207
204static void __init tegra_paz00_init(void) 208static void __init tegra_paz00_init(void)
205{ 209{
206 tegra_clk_init_from_table(paz00_clk_init_table); 210 tegra_clk_init_from_table(paz00_clk_init_table);
@@ -211,6 +215,7 @@ static void __init tegra_paz00_init(void)
211 tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4; 215 tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
212 216
213 platform_add_devices(paz00_devices, ARRAY_SIZE(paz00_devices)); 217 platform_add_devices(paz00_devices, ARRAY_SIZE(paz00_devices));
218 tegra_paz00_wifikill_init();
214 219
215 paz00_i2c_init(); 220 paz00_i2c_init();
216 paz00_usb_init(); 221 paz00_usb_init();
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
deleted file mode 100644
index 11fc8a568c64..000000000000
--- a/arch/arm/mach-tegra/board-seaboard-pinmux.c
+++ /dev/null
@@ -1,197 +0,0 @@
1/*
2 * Copyright (C) 2010-2012 NVIDIA Corporation
3 * Copyright (C) 2011 Google, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#include <linux/kernel.h>
17
18#include "board-seaboard.h"
19#include "board-pinmux.h"
20
21static unsigned long seaboard_pincfg_drive_sdio1[] = {
22 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE, 0),
23 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SCHMITT, 0),
24 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_LOW_POWER_MODE, 3),
25 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH, 31),
26 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH, 31),
27 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING, 3),
28 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, 3),
29};
30
31static struct pinctrl_map common_map[] = {
32 TEGRA_MAP_MUXCONF("ata", "ide", none, driven),
33 TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
34 TEGRA_MAP_MUXCONF("atc", "nand", none, driven),
35 TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
36 TEGRA_MAP_MUXCONF("ate", "gmi", none, tristate),
37 TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
38 TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", none, driven),
39 TEGRA_MAP_MUXCONF("crtp", "crt", up, tristate),
40 TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", none, tristate),
41 TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
42 TEGRA_MAP_MUXCONF("dap2", "dap2", none, driven),
43 TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
44 TEGRA_MAP_MUXCONF("dap4", "dap4", none, driven),
45 TEGRA_MAP_MUXCONF("dta", "vi", down, driven),
46 TEGRA_MAP_MUXCONF("dtb", "vi", down, driven),
47 TEGRA_MAP_MUXCONF("dtc", "vi", down, driven),
48 TEGRA_MAP_MUXCONF("dtd", "vi", down, driven),
49 TEGRA_MAP_MUXCONF("dte", "vi", down, tristate),
50 TEGRA_MAP_MUXCONF("dtf", "i2c3", none, driven),
51 TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
52 TEGRA_MAP_MUXCONF("gmb", "gmi", up, tristate),
53 TEGRA_MAP_MUXCONF("gmc", "uartd", none, driven),
54 TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
55 TEGRA_MAP_MUXCONF("gpu", "pwm", none, driven),
56 TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
57 TEGRA_MAP_MUXCONF("gpv", "pcie", none, tristate),
58 TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
59 TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
60 TEGRA_MAP_MUXCONF("irrx", "uartb", none, driven),
61 TEGRA_MAP_MUXCONF("irtx", "uartb", none, driven),
62 TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
63 TEGRA_MAP_MUXCONF("kbcb", "kbc", up, driven),
64 TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
65 TEGRA_MAP_MUXCONF("kbcd", "kbc", up, driven),
66 TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
67 TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
68 TEGRA_MAP_MUXCONF("lcsn", "rsvd4", na, tristate),
69 TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
70 TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
71 TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
72 TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
73 TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
74 TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
75 TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
76 TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
77 TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
78 TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
79 TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
80 TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
81 TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
82 TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
83 TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
84 TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
85 TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
86 TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
87 TEGRA_MAP_MUXCONF("ldc", "rsvd4", na, tristate),
88 TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
89 TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
90 TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
91 TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
92 TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
93 TEGRA_MAP_MUXCONF("lm0", "rsvd4", na, driven),
94 TEGRA_MAP_MUXCONF("lm1", "crt", na, tristate),
95 TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
96 TEGRA_MAP_MUXCONF("lpw1", "rsvd4", na, tristate),
97 TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
98 TEGRA_MAP_MUXCONF("lsdi", "rsvd4", na, tristate),
99 TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
100 TEGRA_MAP_MUXCONF("lvp0", "rsvd4", na, tristate),
101 TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
102 TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
103 TEGRA_MAP_MUXCONF("owc", "rsvd2", none, tristate),
104 TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
105 TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
106 TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
107 TEGRA_MAP_MUXCONF("sdb", "sdio3", na, driven),
108 TEGRA_MAP_MUXCONF("sdc", "sdio3", none, driven),
109 TEGRA_MAP_MUXCONF("sdd", "sdio3", none, driven),
110 TEGRA_MAP_MUXCONF("sdio1", "sdio1", up, driven),
111 TEGRA_MAP_MUXCONF("slxa", "pcie", up, tristate),
112 TEGRA_MAP_MUXCONF("slxd", "spdif", none, driven),
113 TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
114 TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, driven),
115 TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, driven),
116 TEGRA_MAP_MUXCONF("spib", "gmi", none, tristate),
117 TEGRA_MAP_MUXCONF("spid", "spi1", none, tristate),
118 TEGRA_MAP_MUXCONF("spie", "spi1", none, tristate),
119 TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
120 TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
121 TEGRA_MAP_MUXCONF("uaa", "ulpi", up, driven),
122 TEGRA_MAP_MUXCONF("uab", "ulpi", up, driven),
123 TEGRA_MAP_MUXCONF("uac", "rsvd2", none, driven),
124 TEGRA_MAP_MUXCONF("uad", "irda", none, driven),
125 TEGRA_MAP_MUXCONF("uca", "uartc", none, driven),
126 TEGRA_MAP_MUXCONF("ucb", "uartc", none, driven),
127 TEGRA_MAP_MUXCONF("uda", "ulpi", none, driven),
128 TEGRA_MAP_CONF("ck32", none, na),
129 TEGRA_MAP_CONF("ddrc", none, na),
130 TEGRA_MAP_CONF("pmca", none, na),
131 TEGRA_MAP_CONF("pmcb", none, na),
132 TEGRA_MAP_CONF("pmcc", none, na),
133 TEGRA_MAP_CONF("pmcd", none, na),
134 TEGRA_MAP_CONF("pmce", none, na),
135 TEGRA_MAP_CONF("xm2c", none, na),
136 TEGRA_MAP_CONF("xm2d", none, na),
137 TEGRA_MAP_CONF("ls", up, na),
138 TEGRA_MAP_CONF("lc", up, na),
139 TEGRA_MAP_CONF("ld17_0", down, na),
140 TEGRA_MAP_CONF("ld19_18", down, na),
141 TEGRA_MAP_CONF("ld21_20", down, na),
142 TEGRA_MAP_CONF("ld23_22", down, na),
143};
144
145static struct pinctrl_map seaboard_map[] = {
146 TEGRA_MAP_MUXCONF("ddc", "rsvd2", none, tristate),
147 TEGRA_MAP_MUXCONF("gmd", "sflash", none, driven),
148 TEGRA_MAP_MUXCONF("lpw0", "hdmi", na, driven),
149 TEGRA_MAP_MUXCONF("lpw2", "hdmi", na, driven),
150 TEGRA_MAP_MUXCONF("lsc1", "hdmi", na, tristate),
151 TEGRA_MAP_MUXCONF("lsck", "hdmi", na, tristate),
152 TEGRA_MAP_MUXCONF("lsda", "hdmi", na, tristate),
153 TEGRA_MAP_MUXCONF("slxc", "spdif", none, tristate),
154 TEGRA_MAP_MUXCONF("spia", "gmi", up, tristate),
155 TEGRA_MAP_MUXCONF("spic", "gmi", up, driven),
156 TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, tristate),
157 PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, "drive_sdio1", seaboard_pincfg_drive_sdio1),
158};
159
160static struct pinctrl_map ventana_map[] = {
161 TEGRA_MAP_MUXCONF("ddc", "rsvd2", none, driven),
162 TEGRA_MAP_MUXCONF("gmd", "sflash", none, tristate),
163 TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
164 TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
165 TEGRA_MAP_MUXCONF("lsc1", "displaya", na, driven),
166 TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
167 TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
168 TEGRA_MAP_MUXCONF("slxc", "sdio3", none, driven),
169 TEGRA_MAP_MUXCONF("spia", "gmi", none, tristate),
170 TEGRA_MAP_MUXCONF("spic", "gmi", none, tristate),
171 TEGRA_MAP_MUXCONF("spig", "spi2_alt", none, tristate),
172};
173
174static struct tegra_board_pinmux_conf common_conf = {
175 .maps = common_map,
176 .map_count = ARRAY_SIZE(common_map),
177};
178
179static struct tegra_board_pinmux_conf seaboard_conf = {
180 .maps = seaboard_map,
181 .map_count = ARRAY_SIZE(seaboard_map),
182};
183
184static struct tegra_board_pinmux_conf ventana_conf = {
185 .maps = ventana_map,
186 .map_count = ARRAY_SIZE(ventana_map),
187};
188
189void seaboard_pinmux_init(void)
190{
191 tegra_board_pinmux_init(&common_conf, &seaboard_conf);
192}
193
194void ventana_pinmux_init(void)
195{
196 tegra_board_pinmux_init(&common_conf, &ventana_conf);
197}
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
deleted file mode 100644
index 71e9f3fc7fba..000000000000
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ /dev/null
@@ -1,306 +0,0 @@
1/*
2 * Copyright (c) 2010, 2011 NVIDIA Corporation.
3 * Copyright (C) 2010, 2011 Google, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 */
16
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/platform_device.h>
20#include <linux/serial_8250.h>
21#include <linux/of_serial.h>
22#include <linux/i2c.h>
23#include <linux/delay.h>
24#include <linux/input.h>
25#include <linux/io.h>
26#include <linux/gpio.h>
27#include <linux/gpio_keys.h>
28#include <linux/platform_data/tegra_usb.h>
29
30#include <sound/wm8903.h>
31
32#include <mach/iomap.h>
33#include <mach/irqs.h>
34#include <mach/sdhci.h>
35#include <mach/tegra_wm8903_pdata.h>
36
37#include <asm/mach-types.h>
38#include <asm/mach/arch.h>
39#include <asm/hardware/gic.h>
40
41#include "board.h"
42#include "board-seaboard.h"
43#include "clock.h"
44#include "devices.h"
45#include "gpio-names.h"
46
47static struct plat_serial8250_port debug_uart_platform_data[] = {
48 {
49 /* Memory and IRQ filled in before registration */
50 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
51 .type = PORT_TEGRA,
52 .handle_break = tegra_serial_handle_break,
53 .iotype = UPIO_MEM,
54 .regshift = 2,
55 .uartclk = 216000000,
56 }, {
57 .flags = 0,
58 }
59};
60
61static struct platform_device debug_uart = {
62 .name = "serial8250",
63 .id = PLAT8250_DEV_PLATFORM,
64 .dev = {
65 .platform_data = debug_uart_platform_data,
66 },
67};
68
69static __initdata struct tegra_clk_init_table seaboard_clk_init_table[] = {
70 /* name parent rate enabled */
71 { "uartb", "pll_p", 216000000, true},
72 { "uartd", "pll_p", 216000000, true},
73 { "pll_a", "pll_p_out1", 56448000, true },
74 { "pll_a_out0", "pll_a", 11289600, true },
75 { "cdev1", NULL, 0, true },
76 { "i2s1", "pll_a_out0", 11289600, false},
77 { "usbd", "clk_m", 12000000, true},
78 { "usb3", "clk_m", 12000000, true},
79 { NULL, NULL, 0, 0},
80};
81
82static struct gpio_keys_button seaboard_gpio_keys_buttons[] = {
83 {
84 .code = SW_LID,
85 .gpio = TEGRA_GPIO_LIDSWITCH,
86 .active_low = 0,
87 .desc = "Lid",
88 .type = EV_SW,
89 .wakeup = 1,
90 .debounce_interval = 1,
91 },
92 {
93 .code = KEY_POWER,
94 .gpio = TEGRA_GPIO_POWERKEY,
95 .active_low = 1,
96 .desc = "Power",
97 .type = EV_KEY,
98 .wakeup = 1,
99 },
100};
101
102static struct gpio_keys_platform_data seaboard_gpio_keys = {
103 .buttons = seaboard_gpio_keys_buttons,
104 .nbuttons = ARRAY_SIZE(seaboard_gpio_keys_buttons),
105};
106
107static struct platform_device seaboard_gpio_keys_device = {
108 .name = "gpio-keys",
109 .id = -1,
110 .dev = {
111 .platform_data = &seaboard_gpio_keys,
112 }
113};
114
115static struct tegra_sdhci_platform_data sdhci_pdata1 = {
116 .cd_gpio = -1,
117 .wp_gpio = -1,
118 .power_gpio = -1,
119};
120
121static struct tegra_sdhci_platform_data sdhci_pdata3 = {
122 .cd_gpio = TEGRA_GPIO_SD2_CD,
123 .wp_gpio = TEGRA_GPIO_SD2_WP,
124 .power_gpio = TEGRA_GPIO_SD2_POWER,
125};
126
127static struct tegra_sdhci_platform_data sdhci_pdata4 = {
128 .cd_gpio = -1,
129 .wp_gpio = -1,
130 .power_gpio = -1,
131 .is_8bit = 1,
132};
133
134static struct tegra_wm8903_platform_data seaboard_audio_pdata = {
135 .gpio_spkr_en = TEGRA_GPIO_SPKR_EN,
136 .gpio_hp_det = TEGRA_GPIO_HP_DET,
137 .gpio_hp_mute = -1,
138 .gpio_int_mic_en = -1,
139 .gpio_ext_mic_en = -1,
140};
141
142static struct platform_device seaboard_audio_device = {
143 .name = "tegra-snd-wm8903",
144 .id = 0,
145 .dev = {
146 .platform_data = &seaboard_audio_pdata,
147 },
148};
149
150static struct platform_device *seaboard_devices[] __initdata = {
151 &debug_uart,
152 &tegra_pmu_device,
153 &tegra_sdhci_device4,
154 &tegra_sdhci_device3,
155 &tegra_sdhci_device1,
156 &seaboard_gpio_keys_device,
157 &tegra_i2s_device1,
158 &tegra_das_device,
159 &seaboard_audio_device,
160};
161
162static struct i2c_board_info __initdata isl29018_device = {
163 I2C_BOARD_INFO("isl29018", 0x44),
164};
165
166static struct i2c_board_info __initdata adt7461_device = {
167 I2C_BOARD_INFO("adt7461", 0x4c),
168};
169
170static struct wm8903_platform_data wm8903_pdata = {
171 .irq_active_low = 0,
172 .micdet_cfg = 0,
173 .micdet_delay = 100,
174 .gpio_base = SEABOARD_GPIO_WM8903(0),
175 .gpio_cfg = {
176 0,
177 0,
178 WM8903_GPIO_CONFIG_ZERO,
179 0,
180 0,
181 },
182};
183
184static struct i2c_board_info __initdata wm8903_device = {
185 I2C_BOARD_INFO("wm8903", 0x1a),
186 .platform_data = &wm8903_pdata,
187};
188
189static int seaboard_ehci_init(void)
190{
191 struct tegra_ehci_platform_data *pdata;
192
193 pdata = tegra_ehci1_device.dev.platform_data;
194 pdata->vbus_gpio = TEGRA_GPIO_USB1;
195
196 platform_device_register(&tegra_ehci1_device);
197 platform_device_register(&tegra_ehci3_device);
198
199 return 0;
200}
201
202static void __init seaboard_i2c_init(void)
203{
204 isl29018_device.irq = gpio_to_irq(TEGRA_GPIO_ISL29018_IRQ);
205 i2c_register_board_info(0, &isl29018_device, 1);
206
207 wm8903_device.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
208 i2c_register_board_info(0, &wm8903_device, 1);
209
210 i2c_register_board_info(3, &adt7461_device, 1);
211
212 platform_device_register(&tegra_i2c_device1);
213 platform_device_register(&tegra_i2c_device2);
214 platform_device_register(&tegra_i2c_device3);
215 platform_device_register(&tegra_i2c_device4);
216}
217
218static void __init seaboard_common_init(void)
219{
220 seaboard_pinmux_init();
221
222 tegra_clk_init_from_table(seaboard_clk_init_table);
223
224 tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
225 tegra_sdhci_device3.dev.platform_data = &sdhci_pdata3;
226 tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
227
228 platform_add_devices(seaboard_devices, ARRAY_SIZE(seaboard_devices));
229
230 seaboard_ehci_init();
231}
232
233static void __init tegra_seaboard_init(void)
234{
235 /* Seaboard uses UARTD for the debug port. */
236 debug_uart_platform_data[0].membase = IO_ADDRESS(TEGRA_UARTD_BASE);
237 debug_uart_platform_data[0].mapbase = TEGRA_UARTD_BASE;
238 debug_uart_platform_data[0].irq = INT_UARTD;
239
240 seaboard_common_init();
241
242 seaboard_i2c_init();
243}
244
245static void __init tegra_kaen_init(void)
246{
247 /* Kaen uses UARTB for the debug port. */
248 debug_uart_platform_data[0].membase = IO_ADDRESS(TEGRA_UARTB_BASE);
249 debug_uart_platform_data[0].mapbase = TEGRA_UARTB_BASE;
250 debug_uart_platform_data[0].irq = INT_UARTB;
251
252 seaboard_audio_pdata.gpio_hp_mute = TEGRA_GPIO_KAEN_HP_MUTE;
253
254 seaboard_common_init();
255
256 seaboard_i2c_init();
257}
258
259static void __init tegra_wario_init(void)
260{
261 /* Wario uses UARTB for the debug port. */
262 debug_uart_platform_data[0].membase = IO_ADDRESS(TEGRA_UARTB_BASE);
263 debug_uart_platform_data[0].mapbase = TEGRA_UARTB_BASE;
264 debug_uart_platform_data[0].irq = INT_UARTB;
265
266 seaboard_common_init();
267
268 seaboard_i2c_init();
269}
270
271
272MACHINE_START(SEABOARD, "seaboard")
273 .atag_offset = 0x100,
274 .map_io = tegra_map_common_io,
275 .init_early = tegra20_init_early,
276 .init_irq = tegra_init_irq,
277 .handle_irq = gic_handle_irq,
278 .timer = &tegra_timer,
279 .init_machine = tegra_seaboard_init,
280 .init_late = tegra_init_late,
281 .restart = tegra_assert_system_reset,
282MACHINE_END
283
284MACHINE_START(KAEN, "kaen")
285 .atag_offset = 0x100,
286 .map_io = tegra_map_common_io,
287 .init_early = tegra20_init_early,
288 .init_irq = tegra_init_irq,
289 .handle_irq = gic_handle_irq,
290 .timer = &tegra_timer,
291 .init_machine = tegra_kaen_init,
292 .init_late = tegra_init_late,
293 .restart = tegra_assert_system_reset,
294MACHINE_END
295
296MACHINE_START(WARIO, "wario")
297 .atag_offset = 0x100,
298 .map_io = tegra_map_common_io,
299 .init_early = tegra20_init_early,
300 .init_irq = tegra_init_irq,
301 .handle_irq = gic_handle_irq,
302 .timer = &tegra_timer,
303 .init_machine = tegra_wario_init,
304 .init_late = tegra_init_late,
305 .restart = tegra_assert_system_reset,
306MACHINE_END
diff --git a/arch/arm/mach-tegra/board-seaboard.h b/arch/arm/mach-tegra/board-seaboard.h
deleted file mode 100644
index 4c45d4ca3c49..000000000000
--- a/arch/arm/mach-tegra/board-seaboard.h
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * arch/arm/mach-tegra/board-seaboard.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef _MACH_TEGRA_BOARD_SEABOARD_H
18#define _MACH_TEGRA_BOARD_SEABOARD_H
19
20#include <mach/gpio-tegra.h>
21
22#define SEABOARD_GPIO_TPS6586X(_x_) (TEGRA_NR_GPIOS + (_x_))
23#define SEABOARD_GPIO_WM8903(_x_) (SEABOARD_GPIO_TPS6586X(4) + (_x_))
24
25#define TEGRA_GPIO_SD2_CD TEGRA_GPIO_PI5
26#define TEGRA_GPIO_SD2_WP TEGRA_GPIO_PH1
27#define TEGRA_GPIO_SD2_POWER TEGRA_GPIO_PI6
28#define TEGRA_GPIO_LIDSWITCH TEGRA_GPIO_PC7
29#define TEGRA_GPIO_USB1 TEGRA_GPIO_PD0
30#define TEGRA_GPIO_POWERKEY TEGRA_GPIO_PV2
31#define TEGRA_GPIO_BACKLIGHT TEGRA_GPIO_PD4
32#define TEGRA_GPIO_LVDS_SHUTDOWN TEGRA_GPIO_PB2
33#define TEGRA_GPIO_BACKLIGHT_PWM TEGRA_GPIO_PU5
34#define TEGRA_GPIO_BACKLIGHT_VDD TEGRA_GPIO_PW0
35#define TEGRA_GPIO_EN_VDD_PNL TEGRA_GPIO_PC6
36#define TEGRA_GPIO_MAGNETOMETER TEGRA_GPIO_PN5
37#define TEGRA_GPIO_ISL29018_IRQ TEGRA_GPIO_PZ2
38#define TEGRA_GPIO_AC_ONLINE TEGRA_GPIO_PV3
39#define TEGRA_GPIO_WWAN_PWR SEABOARD_GPIO_TPS6586X(2)
40#define TEGRA_GPIO_CDC_IRQ TEGRA_GPIO_PX3
41#define TEGRA_GPIO_SPKR_EN SEABOARD_GPIO_WM8903(2)
42#define TEGRA_GPIO_HP_DET TEGRA_GPIO_PX1
43#define TEGRA_GPIO_KAEN_HP_MUTE TEGRA_GPIO_PA5
44
45void seaboard_pinmux_init(void);
46
47#endif
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 65014968fc6c..f88e5143c767 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -46,5 +46,14 @@ int __init tegra_powergate_debugfs_init(void);
46static inline int tegra_powergate_debugfs_init(void) { return 0; } 46static inline int tegra_powergate_debugfs_init(void) { return 0; }
47#endif 47#endif
48 48
49int __init harmony_regulator_init(void);
50#ifdef CONFIG_TEGRA_PCI
51int __init harmony_pcie_init(void);
52#else
53static inline int harmony_pcie_init(void) { return 0; }
54#endif
55
56void __init tegra_paz00_wifikill_init(void);
57
49extern struct sys_timer tegra_timer; 58extern struct sys_timer tegra_timer;
50#endif 59#endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 204a5c8b0b57..96fef6bcc651 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -33,6 +33,7 @@
33#include "clock.h" 33#include "clock.h"
34#include "fuse.h" 34#include "fuse.h"
35#include "pmc.h" 35#include "pmc.h"
36#include "apbio.h"
36 37
37/* 38/*
38 * Storage for debug-macro.S's state. 39 * Storage for debug-macro.S's state.
@@ -127,6 +128,7 @@ static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
127#ifdef CONFIG_ARCH_TEGRA_2x_SOC 128#ifdef CONFIG_ARCH_TEGRA_2x_SOC
128void __init tegra20_init_early(void) 129void __init tegra20_init_early(void)
129{ 130{
131 tegra_apb_io_init();
130 tegra_init_fuse(); 132 tegra_init_fuse();
131 tegra2_init_clocks(); 133 tegra2_init_clocks();
132 tegra_clk_init_from_table(tegra20_clk_init_table); 134 tegra_clk_init_from_table(tegra20_clk_init_table);
@@ -138,6 +140,7 @@ void __init tegra20_init_early(void)
138#ifdef CONFIG_ARCH_TEGRA_3x_SOC 140#ifdef CONFIG_ARCH_TEGRA_3x_SOC
139void __init tegra30_init_early(void) 141void __init tegra30_init_early(void)
140{ 142{
143 tegra_apb_io_init();
141 tegra_init_fuse(); 144 tegra_init_fuse();
142 tegra30_init_clocks(); 145 tegra30_init_clocks();
143 tegra_clk_init_from_table(tegra30_clk_init_table); 146 tegra_clk_init_from_table(tegra30_clk_init_table);
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index 7a065f0cf633..ceb52db1e2f1 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -189,8 +189,8 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
189 return PTR_ERR(emc_clk); 189 return PTR_ERR(emc_clk);
190 } 190 }
191 191
192 clk_enable(emc_clk); 192 clk_prepare_enable(emc_clk);
193 clk_enable(cpu_clk); 193 clk_prepare_enable(cpu_clk);
194 194
195 cpufreq_frequency_table_cpuinfo(policy, freq_table); 195 cpufreq_frequency_table_cpuinfo(policy, freq_table);
196 cpufreq_frequency_table_get_attr(freq_table, policy->cpu); 196 cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
@@ -212,7 +212,7 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
212static int tegra_cpu_exit(struct cpufreq_policy *policy) 212static int tegra_cpu_exit(struct cpufreq_policy *policy)
213{ 213{
214 cpufreq_frequency_table_cpuinfo(policy, freq_table); 214 cpufreq_frequency_table_cpuinfo(policy, freq_table);
215 clk_disable(emc_clk); 215 clk_disable_unprepare(emc_clk);
216 clk_put(emc_clk); 216 clk_put(emc_clk);
217 clk_put(cpu_clk); 217 clk_put(cpu_clk);
218 return 0; 218 return 0;
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index d83a8c0296f5..566e2f88899b 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -27,9 +27,9 @@
27#include <linux/cpuidle.h> 27#include <linux/cpuidle.h>
28#include <linux/hrtimer.h> 28#include <linux/hrtimer.h>
29 29
30#include <mach/iomap.h> 30#include <asm/proc-fns.h>
31 31
32extern void tegra_cpu_wfi(void); 32#include <mach/iomap.h>
33 33
34static int tegra_idle_enter_lp3(struct cpuidle_device *dev, 34static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
35 struct cpuidle_driver *drv, int index); 35 struct cpuidle_driver *drv, int index);
@@ -64,7 +64,7 @@ static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
64 64
65 enter = ktime_get(); 65 enter = ktime_get();
66 66
67 tegra_cpu_wfi(); 67 cpu_do_idle();
68 68
69 exit = ktime_sub(ktime_get(), enter); 69 exit = ktime_sub(ktime_get(), enter);
70 us = ktime_to_us(exit); 70 us = ktime_to_us(exit);
diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c
index abea4f6e2dd5..29c5114d607c 100644
--- a/arch/arm/mach-tegra/dma.c
+++ b/arch/arm/mach-tegra/dma.c
@@ -714,13 +714,13 @@ int __init tegra_dma_init(void)
714 714
715 bitmap_fill(channel_usage, NV_DMA_MAX_CHANNELS); 715 bitmap_fill(channel_usage, NV_DMA_MAX_CHANNELS);
716 716
717 c = clk_get_sys("tegra-dma", NULL); 717 c = clk_get_sys("tegra-apbdma", NULL);
718 if (IS_ERR(c)) { 718 if (IS_ERR(c)) {
719 pr_err("Unable to get clock for APB DMA\n"); 719 pr_err("Unable to get clock for APB DMA\n");
720 ret = PTR_ERR(c); 720 ret = PTR_ERR(c);
721 goto fail; 721 goto fail;
722 } 722 }
723 ret = clk_enable(c); 723 ret = clk_prepare_enable(c);
724 if (ret != 0) { 724 if (ret != 0) {
725 pr_err("Unable to enable clock for APB DMA\n"); 725 pr_err("Unable to enable clock for APB DMA\n");
726 goto fail; 726 goto fail;
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 0e09137506ec..d3ad5150d660 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -723,9 +723,9 @@ static int tegra_pcie_power_regate(void)
723 723
724 tegra_pcie_xclk_clamp(false); 724 tegra_pcie_xclk_clamp(false);
725 725
726 clk_enable(tegra_pcie.afi_clk); 726 clk_prepare_enable(tegra_pcie.afi_clk);
727 clk_enable(tegra_pcie.pex_clk); 727 clk_prepare_enable(tegra_pcie.pex_clk);
728 return clk_enable(tegra_pcie.pll_e); 728 return clk_prepare_enable(tegra_pcie.pll_e);
729} 729}
730 730
731static int tegra_pcie_clocks_get(void) 731static int tegra_pcie_clocks_get(void)
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index f5b12fb4ff12..15d506501ccc 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -146,7 +146,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
146 if (ret) 146 if (ret)
147 goto err_power; 147 goto err_power;
148 148
149 ret = clk_enable(clk); 149 ret = clk_prepare_enable(clk);
150 if (ret) 150 if (ret)
151 goto err_clk; 151 goto err_clk;
152 152
@@ -162,7 +162,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
162 return 0; 162 return 0;
163 163
164err_clamp: 164err_clamp:
165 clk_disable(clk); 165 clk_disable_unprepare(clk);
166err_clk: 166err_clk:
167 tegra_powergate_power_off(id); 167 tegra_powergate_power_off(id);
168err_power: 168err_power:
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 5b20197bae7f..d29b156a8011 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -62,32 +62,3 @@
62 movw \reg, #:lower16:\val 62 movw \reg, #:lower16:\val
63 movt \reg, #:upper16:\val 63 movt \reg, #:upper16:\val
64.endm 64.endm
65
66/*
67 * tegra_cpu_wfi
68 *
69 * puts current CPU in clock-gated wfi using the flow controller
70 *
71 * corrupts r0-r3
72 * must be called with MMU on
73 */
74
75ENTRY(tegra_cpu_wfi)
76 cpu_id r0
77 cpu_to_halt_reg r1, r0
78 cpu_to_csr_reg r2, r0
79 mov32 r0, TEGRA_FLOW_CTRL_VIRT
80 mov r3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
81 str r3, [r0, r2] @ clear event & interrupt status
82 mov r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT | FLOW_CTRL_JTAG_RESUME
83 str r3, [r0, r1] @ put flow controller in wait irq mode
84 dsb
85 wfi
86 mov r3, #0
87 str r3, [r0, r1] @ clear flow controller halt status
88 mov r3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
89 str r3, [r0, r2] @ clear event & interrupt status
90 dsb
91 mov pc, lr
92ENDPROC(tegra_cpu_wfi)
93
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index b59315ce3691..a703844b2061 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -69,6 +69,8 @@
69 69
70#define PERIPH_CLK_SOURCE_MASK (3<<30) 70#define PERIPH_CLK_SOURCE_MASK (3<<30)
71#define PERIPH_CLK_SOURCE_SHIFT 30 71#define PERIPH_CLK_SOURCE_SHIFT 30
72#define PERIPH_CLK_SOURCE_PWM_MASK (7<<28)
73#define PERIPH_CLK_SOURCE_PWM_SHIFT 28
72#define PERIPH_CLK_SOURCE_ENABLE (1<<28) 74#define PERIPH_CLK_SOURCE_ENABLE (1<<28)
73#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF 75#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
74#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF 76#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
@@ -908,9 +910,20 @@ static void tegra2_periph_clk_init(struct clk *c)
908 u32 val = clk_readl(c->reg); 910 u32 val = clk_readl(c->reg);
909 const struct clk_mux_sel *mux = NULL; 911 const struct clk_mux_sel *mux = NULL;
910 const struct clk_mux_sel *sel; 912 const struct clk_mux_sel *sel;
913 u32 shift;
914 u32 mask;
915
916 if (c->flags & MUX_PWM) {
917 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
918 mask = PERIPH_CLK_SOURCE_PWM_MASK;
919 } else {
920 shift = PERIPH_CLK_SOURCE_SHIFT;
921 mask = PERIPH_CLK_SOURCE_MASK;
922 }
923
911 if (c->flags & MUX) { 924 if (c->flags & MUX) {
912 for (sel = c->inputs; sel->input != NULL; sel++) { 925 for (sel = c->inputs; sel->input != NULL; sel++) {
913 if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value) 926 if ((val & mask) >> shift == sel->value)
914 mux = sel; 927 mux = sel;
915 } 928 }
916 BUG_ON(!mux); 929 BUG_ON(!mux);
@@ -1023,12 +1036,23 @@ static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
1023{ 1036{
1024 u32 val; 1037 u32 val;
1025 const struct clk_mux_sel *sel; 1038 const struct clk_mux_sel *sel;
1039 u32 mask, shift;
1040
1026 pr_debug("%s: %s %s\n", __func__, c->name, p->name); 1041 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1042
1043 if (c->flags & MUX_PWM) {
1044 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
1045 mask = PERIPH_CLK_SOURCE_PWM_MASK;
1046 } else {
1047 shift = PERIPH_CLK_SOURCE_SHIFT;
1048 mask = PERIPH_CLK_SOURCE_MASK;
1049 }
1050
1027 for (sel = c->inputs; sel->input != NULL; sel++) { 1051 for (sel = c->inputs; sel->input != NULL; sel++) {
1028 if (sel->input == p) { 1052 if (sel->input == p) {
1029 val = clk_readl(c->reg); 1053 val = clk_readl(c->reg);
1030 val &= ~PERIPH_CLK_SOURCE_MASK; 1054 val &= ~mask;
1031 val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT; 1055 val |= (sel->value) << shift;
1032 1056
1033 if (c->refcnt) 1057 if (c->refcnt)
1034 clk_enable(p); 1058 clk_enable(p);
@@ -2149,14 +2173,14 @@ static struct clk tegra_clk_emc = {
2149 } 2173 }
2150 2174
2151static struct clk tegra_list_clks[] = { 2175static struct clk tegra_list_clks[] = {
2152 PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 108000000, mux_pclk, 0), 2176 PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 108000000, mux_pclk, 0),
2153 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET), 2177 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET),
2154 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0), 2178 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
2155 PERIPH_CLK("i2s1", "tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), 2179 PERIPH_CLK("i2s1", "tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2156 PERIPH_CLK("i2s2", "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), 2180 PERIPH_CLK("i2s2", "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2157 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), 2181 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
2158 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71), 2182 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71),
2159 PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71), 2183 PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM),
2160 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), 2184 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2161 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), 2185 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2162 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), 2186 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
@@ -2189,11 +2213,11 @@ static struct clk tegra_list_clks[] = {
2189 PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0), 2213 PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2190 PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0), 2214 PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2191 PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0), 2215 PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
2192 PERIPH_CLK("uarta", "uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX), 2216 PERIPH_CLK("uarta", "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2193 PERIPH_CLK("uartb", "uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX), 2217 PERIPH_CLK("uartb", "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2194 PERIPH_CLK("uartc", "uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX), 2218 PERIPH_CLK("uartc", "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2195 PERIPH_CLK("uartd", "uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX), 2219 PERIPH_CLK("uartd", "tegra-uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2196 PERIPH_CLK("uarte", "uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX), 2220 PERIPH_CLK("uarte", "tegra-uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
2197 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */ 2221 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
2198 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ 2222 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
2199 PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ 2223 PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
@@ -2245,20 +2269,16 @@ static struct clk tegra_list_clks[] = {
2245 * table under two names. 2269 * table under two names.
2246 */ 2270 */
2247static struct clk_duplicate tegra_clk_duplicates[] = { 2271static struct clk_duplicate tegra_clk_duplicates[] = {
2248 CLK_DUPLICATE("uarta", "tegra_uart.0", NULL), 2272 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
2249 CLK_DUPLICATE("uartb", "tegra_uart.1", NULL), 2273 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
2250 CLK_DUPLICATE("uartc", "tegra_uart.2", NULL), 2274 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
2251 CLK_DUPLICATE("uartd", "tegra_uart.3", NULL), 2275 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
2252 CLK_DUPLICATE("uarte", "tegra_uart.4", NULL), 2276 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
2253 CLK_DUPLICATE("usbd", "utmip-pad", NULL), 2277 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
2254 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL), 2278 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
2255 CLK_DUPLICATE("usbd", "tegra-otg", NULL), 2279 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
2256 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"), 2280 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
2257 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"), 2281 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
2258 CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
2259 CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
2260 CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
2261 CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
2262 CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"), 2282 CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
2263 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"), 2283 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
2264 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"), 2284 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index e33fe4b14a2a..6674f100e16f 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -2871,7 +2871,7 @@ static struct clk tegra30_clk_twd = {
2871 }, \ 2871 }, \
2872 } 2872 }
2873struct clk tegra_list_clks[] = { 2873struct clk tegra_list_clks[] = {
2874 PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 26000000, mux_clk_m, 0), 2874 PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0),
2875 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB), 2875 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
2876 PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB), 2876 PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
2877 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0), 2877 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
@@ -2886,7 +2886,7 @@ struct clk tegra_list_clks[] = {
2886 PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), 2886 PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2887 PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), 2887 PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2888 PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB), 2888 PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB),
2889 PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB), 2889 PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
2890 PERIPH_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), 2890 PERIPH_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2891 PERIPH_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), 2891 PERIPH_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2892 PERIPH_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), 2892 PERIPH_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
@@ -2924,16 +2924,11 @@ struct clk tegra_list_clks[] = {
2924 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), 2924 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2925 PERIPH_CLK("i2c4", "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), 2925 PERIPH_CLK("i2c4", "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2926 PERIPH_CLK("i2c5", "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), 2926 PERIPH_CLK("i2c5", "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2927 PERIPH_CLK("uarta", "tegra_uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB), 2927 PERIPH_CLK("uarta", "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2928 PERIPH_CLK("uartb", "tegra_uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB), 2928 PERIPH_CLK("uartb", "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2929 PERIPH_CLK("uartc", "tegra_uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB), 2929 PERIPH_CLK("uartc", "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2930 PERIPH_CLK("uartd", "tegra_uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB), 2930 PERIPH_CLK("uartd", "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2931 PERIPH_CLK("uarte", "tegra_uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB), 2931 PERIPH_CLK("uarte", "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2932 PERIPH_CLK("uarta_dbg", "serial8250.0", "uarta", 6, 0x178, 800000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2933 PERIPH_CLK("uartb_dbg", "serial8250.0", "uartb", 7, 0x17c, 800000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2934 PERIPH_CLK("uartc_dbg", "serial8250.0", "uartc", 55, 0x1a0, 800000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2935 PERIPH_CLK("uartd_dbg", "serial8250.0", "uartd", 65, 0x1c0, 800000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2936 PERIPH_CLK("uarte_dbg", "serial8250.0", "uarte", 66, 0x1c4, 800000000, mux_pllp_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2937 PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops), 2932 PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
2938 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET), 2933 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
2939 PERIPH_CLK("3d2", "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET), 2934 PERIPH_CLK("3d2", "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
@@ -2983,6 +2978,11 @@ struct clk tegra_list_clks[] = {
2983 * table under two names. 2978 * table under two names.
2984 */ 2979 */
2985struct clk_duplicate tegra_clk_duplicates[] = { 2980struct clk_duplicate tegra_clk_duplicates[] = {
2981 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
2982 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
2983 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
2984 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
2985 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
2986 CLK_DUPLICATE("usbd", "utmip-pad", NULL), 2986 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
2987 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL), 2987 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
2988 CLK_DUPLICATE("usbd", "tegra-otg", NULL), 2988 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
@@ -2990,10 +2990,6 @@ struct clk_duplicate tegra_clk_duplicates[] = {
2990 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"), 2990 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
2991 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"), 2991 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
2992 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"), 2992 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
2993 CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
2994 CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
2995 CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
2996 CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
2997 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"), 2993 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
2998 CLK_DUPLICATE("bsev", "nvavp", "bsev"), 2994 CLK_DUPLICATE("bsev", "nvavp", "bsev"),
2999 CLK_DUPLICATE("vde", "tegra-aes", "vde"), 2995 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index 315672c7bd48..57b5bdc13b9b 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -189,7 +189,7 @@ static void __init tegra_init_timer(void)
189 " Assuming 12Mhz input clock.\n"); 189 " Assuming 12Mhz input clock.\n");
190 rate = 12000000; 190 rate = 12000000;
191 } else { 191 } else {
192 clk_enable(clk); 192 clk_prepare_enable(clk);
193 rate = clk_get_rate(clk); 193 rate = clk_get_rate(clk);
194 } 194 }
195 195
@@ -201,7 +201,7 @@ static void __init tegra_init_timer(void)
201 if (IS_ERR(clk)) 201 if (IS_ERR(clk))
202 pr_warn("Unable to get rtc-tegra clock\n"); 202 pr_warn("Unable to get rtc-tegra clock\n");
203 else 203 else
204 clk_enable(clk); 204 clk_prepare_enable(clk);
205 205
206 switch (rate) { 206 switch (rate) {
207 case 12000000: 207 case 12000000:
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
index 54e353c8e304..022b33a05c3a 100644
--- a/arch/arm/mach-tegra/usb_phy.c
+++ b/arch/arm/mach-tegra/usb_phy.c
@@ -247,7 +247,7 @@ static void utmip_pad_power_on(struct tegra_usb_phy *phy)
247 unsigned long val, flags; 247 unsigned long val, flags;
248 void __iomem *base = phy->pad_regs; 248 void __iomem *base = phy->pad_regs;
249 249
250 clk_enable(phy->pad_clk); 250 clk_prepare_enable(phy->pad_clk);
251 251
252 spin_lock_irqsave(&utmip_pad_lock, flags); 252 spin_lock_irqsave(&utmip_pad_lock, flags);
253 253
@@ -259,7 +259,7 @@ static void utmip_pad_power_on(struct tegra_usb_phy *phy)
259 259
260 spin_unlock_irqrestore(&utmip_pad_lock, flags); 260 spin_unlock_irqrestore(&utmip_pad_lock, flags);
261 261
262 clk_disable(phy->pad_clk); 262 clk_disable_unprepare(phy->pad_clk);
263} 263}
264 264
265static int utmip_pad_power_off(struct tegra_usb_phy *phy) 265static int utmip_pad_power_off(struct tegra_usb_phy *phy)
@@ -272,7 +272,7 @@ static int utmip_pad_power_off(struct tegra_usb_phy *phy)
272 return -EINVAL; 272 return -EINVAL;
273 } 273 }
274 274
275 clk_enable(phy->pad_clk); 275 clk_prepare_enable(phy->pad_clk);
276 276
277 spin_lock_irqsave(&utmip_pad_lock, flags); 277 spin_lock_irqsave(&utmip_pad_lock, flags);
278 278
@@ -284,7 +284,7 @@ static int utmip_pad_power_off(struct tegra_usb_phy *phy)
284 284
285 spin_unlock_irqrestore(&utmip_pad_lock, flags); 285 spin_unlock_irqrestore(&utmip_pad_lock, flags);
286 286
287 clk_disable(phy->pad_clk); 287 clk_disable_unprepare(phy->pad_clk);
288 288
289 return 0; 289 return 0;
290} 290}
@@ -580,7 +580,7 @@ static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
580 msleep(5); 580 msleep(5);
581 gpio_direction_output(config->reset_gpio, 1); 581 gpio_direction_output(config->reset_gpio, 1);
582 582
583 clk_enable(phy->clk); 583 clk_prepare_enable(phy->clk);
584 msleep(1); 584 msleep(1);
585 585
586 val = readl(base + USB_SUSP_CTRL); 586 val = readl(base + USB_SUSP_CTRL);
@@ -689,7 +689,7 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
689 err = PTR_ERR(phy->pll_u); 689 err = PTR_ERR(phy->pll_u);
690 goto err0; 690 goto err0;
691 } 691 }
692 clk_enable(phy->pll_u); 692 clk_prepare_enable(phy->pll_u);
693 693
694 parent_rate = clk_get_rate(clk_get_parent(phy->pll_u)); 694 parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
695 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) { 695 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
@@ -735,7 +735,7 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
735 return phy; 735 return phy;
736 736
737err1: 737err1:
738 clk_disable(phy->pll_u); 738 clk_disable_unprepare(phy->pll_u);
739 clk_put(phy->pll_u); 739 clk_put(phy->pll_u);
740err0: 740err0:
741 kfree(phy); 741 kfree(phy);
@@ -810,7 +810,7 @@ void tegra_usb_phy_close(struct tegra_usb_phy *phy)
810 clk_put(phy->clk); 810 clk_put(phy->clk);
811 else 811 else
812 utmip_pad_close(phy); 812 utmip_pad_close(phy);
813 clk_disable(phy->pll_u); 813 clk_disable_unprepare(phy->pll_u);
814 clk_put(phy->pll_u); 814 clk_put(phy->pll_u);
815 kfree(phy); 815 kfree(phy);
816} 816}